Digitally Implemented Novel Technique to Approach

Digitally Implemented Novel Technique to Approach Natural SPWM Mohan Renge Department of Electrical Engineering Priyadarshini College of Engineering, Nagpur, India. Email: [email protected]

Hiralal Suryawanshi Department of Electrical Engineering Visvesvaraya National Institute of Technology, Nagpur, India. Email: [email protected]

Madhuri Chaudhari Department of Electrical Engineering Visvesvaraya National Institute of Technology, Nagpur, India. Email: [email protected]

Abstract –Digital signal processor (DSP) based sinusoidal pulse width modulation (SPWM) uses symmetrical and asymmetrical regular sampling. These samplings do not attain the performance of natural SPWM at low sampling. This paper presents a simple technique using digital sampling to approach naturally sampled SPWM. The proposed technique samples the modulating waveform at every peak of the triangular carrier signal and calculates precise magnitude of modulating signal for the instant of intersection. This signal has enough information to minimize the error in switching instant. The original modulating signal appears in the PWM output spectra unattenuated, without any distortion components, and without phase delay, regardless of the frequency or modulation depth of that signal. The proposed technique is suitable for real time implementation using commercial DSP. The proposed technique is also applicable to multilevel inverter and does not generate superfluous pulses like asymmetrical sampling in the output voltage of multilevel inverter. Simulation and experimental results are presented to demonstrate and confirm the validity of the proposed technique.

Keywords: Voltage source inverter, multilevel inverter, SPWM, DSP

I INTRODUCTION

The sinusoidal pulse width modulation (SPWM) is one of the most popular modulation technique used in wide range of industrial application where power-switching converters are employed. Traditional natural SPWM system employs analog control technique. Analog control relies on large number of discrete components resulting high cost with problems of reliability, repeatability, accuracy and stability. Due to aging, it faces long-term stability problems and being untrimmed accuracy of the triangular carrier’s amplitude, and thus switching instant, is limited to ±5% [1]. This leads to poor cancellation of spectral terms in multilevel converter. Digital circuits have many advantages over analog circuits. Unfortunately, the equations relating the natural SPWM switching angles to voltage are transcendental and cannot be solved on line by a microprocessor-based controller [2]. Thus, significant off-line computation is involved in developing these strategies, which has prevented their automatic use by industry in many drive applications. In addition, the implementation of these PWM strategies involves extensive look-up tables (LUT’s) [3] and interpolation between LUT’s to provide quasicontinuous voltage control with the associated complexity. This leads to the development of a regular/uniform sampling technique. Regular sampling is based on sample and hold principle, and adaptable to microprocessor [4] and DSP implementation [5]. Digital uniform/regular sampling comes in two variants: symmetrical and asymmetrical. In symmetrical regular sampling, reference wave is sampled at only positive peak or negative peak of the carrier wave and sample (Vsamp) is held constant for the complete carrier period. In asymmetrical regular sampling, the reference signal is sampled at positive as well as at negative peak of carrier wave and held constant for the half carrier period. Asymmetrical sampling reduces the third harmonic to nearly 30% of the symmetrical SPWM value and eliminates the remaining base-band harmonics [6].

2

Usually; at high carrier frequency, asymmetrical regular sampling is very much similar to natural sampling. At low carrier frequency, uniform PWM attenuates the input signal and generates input signal harmonics and group delay. These effects become more pronounced as the frequency modulation ratio, mf (=fc/fm) demotes. This introduces phase shift between modulating signal and fundamental component of output voltage of inverter. The

phase

shift

becomes

significant at lower switching frequency particularly in high power application where converters are connected to grid system [4]. The power exchange between grid and converter depends upon the angle between their voltages. Asymmetrical sampling also produces the superfluous pulses in the output of multilevel inverter as shown in Fig. 1 (encircled). Many efforts have been made to achieve performance like natural SPWM technique [3]-[10]. DSP has high operating frequency as compared to carrier frequency therefore; high sampling rate is possible even though carrier frequency is low. Samples are taken more frequently (resampling technique) than once per switching edge at the beginning of the PWM switch period. This is called re-sampling [5]. Another method, referred to as asymmetric regular sampling , operates at double sampling frequency which samples are taken once in every subcycle. This improves the dynamic response and produces somewhat less harmonic distortion of the load currents [Holtz]. Re-sampling can achieve the performance of natural sampling but requires dedicated DSP along with FPGA. Reference [7] claims that, it is not easy to implement with single DSP since readily available DSPs do not have enough PWM output pins for multilevel inverter control and the calculations that are required to be carried out would also place a big burden on the CPU. In [9] a very cumbersome scheme is proposed. In this paper a carrier-based PWM scheme is developed for a five-level cascaded H-bridge inverter. This scheme uses one Mini DSP controller for every H-bridge module apart from one master DSP controller and a PC controller. Though a single counter is used for an H-bridge, a combination of several DSPs, their synchronization and interrupt management makes this scheme very complex, especially for a

3

medium voltage drives [11]. A mathematical modeling based on sampling theory and discretetime signal processing is proposed in [10]. Other approaches use n-grade polynomial interpolation to calculate the duty-cycle obtained if naturally sampled PWM had been used. This modulation, usually called pseudo natural PWM, can theoretically achieve excellent results, with no base-band harmonics, but requires high computational power [12]. Efficient computational technique based on space vector PWM proposed in [Kanchan] for real time application. However, accuracy of calculation of crossing instant was not pointed out in this paper. The motivation of this paper is digital implementation of naturally sampled SPWM using single DSP at the low computational cost. In this paper, simple mathematical technique is proposed to estimate the magnitude of modulating signal at the instant of switching to approach natural SPWM sampling. This method samples the modulating waveform at every peak of the carrier frequency and calculates the magnitude of modulating signal for the switching. With the proposed technique, determination of switching instant is precise as compared to symmetrical and asymmetrical regular sampling. The following are the salient features of the proposed scheme. 1. Minimization of phase shift in large at low sampling rate 2. Simple on line calculation 3. Easily implementation with single chip alone 4. Low computational cost (time and memory) 5. Suitable for multilevel inverter 6. Achieve the merits of natural sampling such as no group delay, minimum phase shift, precise instant of switching, equal side band harmonics and no superfluous pulses in multilevel inverter output In order to implement the proposed technique, experimentation is carried on laboratory model of five-level (5L) three-phase diode clamped inverter (Fig. 2). A 32 bit fixed point DSP

4

TMS320F2812 is used as central processor. Operating from 150 MHz clock speed, a performance of 150 MIPs allows higher processing speed and precision. The DSP operates in parallel to peripherals therefore; they do not add data transmission delay in implementation. The proposed modulating technique is experimentally verified on 2L-VSI and 5L-VSI. Experimental and simulation results show that the natural SPWM is achieved with precision. In section II, review of SPWM technique is done. In Section III, the theoretical principle of proposed technique for calculation of magnitude of modulating signal for the instant of switching is presented. The application of proposed technique is extended to five level inverter in section IV. Section V discusses implementation of proposed technique using single DSP for multilevel inverter. The performance of the proposed estimator is evaluated by simulation and experimentally in section VI. The final section gives the conclusions.

II.

SINUSOIDAL PULSE WIDTH MODULATION

A. Naturally Sampled Sinusoidal Pulse Width Modulation In a two level PWM inverter with sine-triangle modulation, a sinusoidal control signal ( Vm (t ) ) at a desired output frequency (fm) is compared with a triangular waveform with frequency fc. The triangular carrier waveform Vc (t ) in Fig. 3 (a) is normally kept at a constant frequency fc and constant amplitude Ac. The amplitude modulation index is defined as;

ma 

Am Ac

(1)

The output PWM signal can be produced by comparing the modulating waveform and carrier waveform. When Vm (t )  Vc (t ) , the value of the output PWM signal is ‘1’ (Fig. 3 ) and output voltage of inverter with respective to dc mid-point is  12 Vdc where, Vdc is the dc bus voltage of the inverter. When Vm (t )  Vc (t ) , the value of the output PWM signal is ‘0’ and

5

output voltage of inverter becomes  12 Vdc . The output voltage of the inverter can be considered to be a voltage switching from  12 Vdc to  12 Vdc . B. Digitally Sampled Pulse Width Modulation Uniform/regular sampling comes in two variants: symmetrical and asymmetrical. In symmetrical regular sampling, reference wave is sampled at only positive peak or negative peak of the carrier wave and sample (Vsamp) is held constant for the complete carrier period. In asymmetrical regular sampling, the reference signal is sampled at positive as well as at negative peaks of carrier frequency and held constant for half carrier period as shown in Fig. 3. Here sampling frequency is twice the carrier frequency. Asymmetrical regular sampling is preferred, since each switching edge is the result of new sample and gives better performance as compared to symmetrical regular sampling [5]. As high-power solid-state switches are generally slow, so that a low frequency triangle carrier must be used to reduce switching loss. At low carrier frequency, poor accuracy is inherent in applying asymmetrical sampling, exemplified by Fig. 3. This introduces the distortion in modulating signal results in phase shift between modulating signal and fundamental component of output voltage [1]. This phase shift becomes significant at lower switching frequency particularly in high power application. The phase shift is given by – 180°/2mf [1]. III. PROPOSED SINUSOIDAL PULSE WIDTH MODULATION A simple technique is proposed here to achieve natural sampling for digital circuit. The kth sample gives the value of the discrete time signal tk  kTc / 2 where k is an integer. The magnitude of modulating signal ma (sin (tk ) is sampled at the instant tk as shown in Fig. 3. There is time difference of tk between sampling instant and the instant of crossing of modulating signal and carrier signal. In proposed technique, approximate value of tk is calculated at each peak of carrier signal. Extrapolation process is carried out to find the intersection point of 6

modulating signal and carrier signal. From Fig. 3, for the instant of intersection of modulating signal and rising edge of carrier signal, equation can be written as

ma sin(tk  tk )  4 f c tk 1  tk 

(2)

ma kc sin (ωt k )cos(Tc / 4)  1 4 f c  ma k s cos(t k )

where k s 

(3)

sin(t k ) cos(t k ) and kc  t k cos(Tc / 4)

The equation (3) is a nonlinear equation. To calculate the approximate value of ∆tk, sinusoidal term is considered as linear. As sampling frequency approaches to infinity (natural sampling), ∆tk tends to 0 (4)

sin(tk ) ks  lim =1 tk 0 tk

But; at low sampling frequency, ∆tk has sufficient high value equal to or less than Tc/2 depending on crossing instant. Therefore, ks deviates from unity. Fig. 4 (a) shows the possible range deviation of ks from unity. This is very close to unity and hence ks can be approximated to unity. However, this approximation introduces error in calculation of switching instant. The error is introduced by approximation is negligible (Table I) as compared to asymmetrical sampling. Another term maks cos(tk ) is very small as compared to 4fc, therefore effect of approximation of ks is negligible. The value tk varies from 0 to Tc/2 depending on the ma and sampling instant tk. If cosine term, cos(tk ) is approximated to cos(Tc / 4) , the maximum deviation (Tc / 4  tk ) can be  Tc / 4 . For tk equals to Tc / 4 , kc will be unity otherwise its value will lie in the vicinity of unity in the shaded area as shown in Fig. 4 (b). If kc is considered as unity, tk will be t k' . Hence, equation (3) can be written as;

7

masin (ωtk )cos( 4c )  1 T

tk'



(5)

4 fc  macos(tk )

where tk' is approximate value of ∆tk. A sampling modulating signal at tk is modified with ma (sin  (t k  t k' ) and held constant for the period of Tc / 2 . This value of modulating signal is compared with carrier signal to decide the switching instant of respective devices. Similarly; equation can be derived as follows for the instant of intersection of modulating signal and falling edge of carrier signal.

1  masin (ωtk )cos( 4c ) T

tk'



(6)

4 fc  macos(tk )

The MATLAB program is developed using (5) and (6) to analyze the phase shift and harmonics. With asymmetrical sampling maximum error in switching time is -0.02033015 ms. This error can be reduced by averaging the kth and (k+1)th samples. With averaging the samples, maximum error is -0.0076061ms. The proposed technique reduces the maximum error to 0.00043485 ms. Table I gives instant of intersection of modulating signal and carrier signal for natural sampling, asymmetrical sampling, by averaging the sampled signals and proposed technique for the quarter cycle of modulating waveform. IV. PROPOSED SPWM TECHNIQUE FOR MULTILEVEL INVERTER Multilevel inverters are more suitable for high power applications [13]-[15]. The multilevel carrier based PWM for N-level inverter uses set of N-1 adjacent level triangular carrier waves with same peak-to-peak amplitude and frequency. Each carrier wave has a distinct dc bias level such that disposition of all the waveforms together fit the vertical span of modulating signal and none of them overlaps each other. As shown in Fig. 5 (a), four carriers (c1, c2, c3 and c4) are used for five level inverter. Modulating waveform is compared with carrier waveforms and switching patterns are developed using equation (7);

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 2  1  Sw   0  1   2

: : : : :

Vm (t ) Vc 4 (t ) Vc 4 (t )  Vm (t ) Vc3 (t ) Vc3 (t )  Vm (t ) Vc 2 (t ) Vc 2 (t )  Vm (t ) Vc1 (t ) Vc1 (t )  Vm (t )

(7)

Various level shifted carrier SPWM techniques are discussed in [16]. It is shown in previous work [16] that all carrier in phase disposition (PD) technique produces fewer harmonics on a line-to-line basis as compared to the other two techniques because it puts harmonic energy directly into a common mode carrier component, which cancels across the line-to-line outputs. PD modulation technique is considered to generate the gate pulses. For five level inverter, four carriers (c1-c4) divide whole modulating waveform with unity modulating index into four region r1 to r4 as shown in Fig. 5 (a). The application of proposed mathematical model can be extended to multilevel inverter. The crossover instant of modulating signal and carrier signal c4 defines switching of S1 and its complimentary switch S5 (Fig. 2). Similarly switching states of S2/S6, S3/S7 and S4/S8 are defined by comparing modulating signal with carrier signals c3, c2 and c1 respectively. At the instant of intersection of modulating signal and rising edge of carrier signal cx (where x = 1, 2, 3, 4), equation can be written as;

2ma sin (tk  tk )  2 fc tk  rx

(8)

Where rx is lower limit of rx and rx is higher limit.

rx  2masin (ωtk )cos( 4c ) T

tk'



(9)

2(macos(tk )  f c )

Similarly for falling edge of carrier signal

rx  2masin (ωtk )cos( 4c ) T

tk'



(10)

2(macos(tk )  f c )

9

The value of tk' is calculated using (9) and (10). At the instant of intersection (t k  t k' ) , the magnitude of modulating signal is given by

Vsamp  2ma sin(tk  tk' )

(11)

The value of Vsamp is held constant and is compared with carrier signal to decide the instant of switching. V. DSP IMPLEMENTATION To implement the proposed technique with hardware, programme is developed using DSP TMS320F2812 for 2L-VSI and 5L-VSI. The first task is to identify the carrier region to find the instant of intersection of modulating signal and carrier signal (cx). The instant of switching

(t k  t k' ) is calculated. If tk' > Tc /2 region is again redefined. Finally the instant of switching is determined by using (9) or (10) depending on the instant of intersection on rising edge or falling edge of carrier signal. The DSP TMS320F2812 has two event managers. Event manager generates virtual triangular carrier waveform. The compare register count (calculated value of modulating signal) is compared with instantaneous value of generated virtual carrier waveform to generate the gate pulses for 2L-inverter. For five level inverter, single carrier as shown in Fig. 5(b) is used for all four-carrier signals (Fig. 5(a)) to compare with piecewise modulating waveform. Therefore, there is no need of synchronization of carrier signals. One of the event manager performs this task. The DSP calculates value of tk' and corresponding Vsamp to load the compare register. The timer is set to generate the time period interrupt at the end of every Tc / 2 interval. The DSP loads count analogous to Vsamp of each phase in three respective compare resisters (CMPR1, CMPR2 and CMPR3) and starts computation process for the next crossing. The timer generates interrupts by comparing the count of compare register with single virtual carrier. Interrupt

10

service routine (ISR) executes a programme to generate the gate pulses for the inverter. The virtual carrier generated by timer plays the role of the particular carrier through which modulating signal has to be travel. During the traveling period of modulating waveform through a particular carrier region, the DSP generates gating pulses for respective switches when compare register count matches with virtual carrier. Switching function and corresponding output voltage of 5L-VSI are given in Table II. VI.

SIMULATION AND EXPERIMENTAL RESULTS

To verify the validity of the proposed technique; MATLAB/Simulink simulation is carried out for ma = 0.9 and fm=50 Hz. Three-phase five level diode clamped multilevel inverter is fabricated in laboratory to verify the validity of proposed technique. It is clear from the Fig. 6, that the proposed technique yields more accurate intersections as compared to the asymmetrical regular sampling. This technique is also implemented for 5L-VSI. Fig. 6(b) shows that the intersection instant using proposed technique is very close to that of natural sampling for 5LVSI. The calculation of crossing instant based on slope of carrier wave and frequency of the reference signal. However, this technique is not applicable to space-vector PWM technique. The dc link utilisation can be increased by adding third harmonics. Simulation results in Fig. 7 (a). shows the crossing instant with proposed scheme is matching with natural sampling and Fig. 7 (b) shows the FFT of output of two level inverter. It consists third harmonics. Discrete Fourier block from Sim-PowerSystems (MATLAB) is used to find phase shift between modulating signal and output voltage of 2L-VSI. Fig. 8(a) depicts the phase shift between modulating signal and fundamental component of the inverter output voltage for asymmetrical sampling . The simulation is carried out for different carrier frequencies, ranging from 750 Hz to 1350 Hz in the step of 50 Hz and the range of modulating index varies from 0.1 to 0.9 in the step of 0.05. The phase shift is -6.0° at 750 Hz carrier for asymmetrical sampling. For 1350 Hz carrier frequency, the phase shift is about -4.5°. The phase shift reduces as carrier frequency increases and

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approaches to natural sampling as carrier frequency approaches to infinite. As carrier as well sampling frequency reduces, this phase shift increases considerable large. It is significant in converter, which is connected to grid and operates at low carrier frequency. Fig. 8 (b) shows the phase shift between modulating signal and fundamental component of output voltage of 2L-VSI with natural sampling. Simulation result in Fig. 8(c) shows that the phase shift is below 0.08° for proposed technique for all carrier frequencies and modulating index. This phase shift is very close to natural sampling (Fig. 8(a)). For carrier frequency 1050 Hz and ma = 0.9, the phase shift is -0.017° with the proposed technique as compared to -4.263° in asymmetrical regular sampling. Fig. 8 (d) shows the simulation result for five-level inverter with asymmetrical sampling and proposed technique. To verify the feasibility of proposed technique, DSP programme is developed for 2L-VSI and 5L diode clamped inverter. The experimental model consists of five-level three-phase inverter using low voltage IGBT, dc bus voltage 650 V, mf = 21, star connected inductive-resistive load with 0.82 lagging power factor. The same experimental model was operated as 2L inverter. Experimentations are carried out to study phase shift between modulating signal and fundamental waveform of 2L-VSI for fm = 50Hz. Experimental result in Fig.8 (e) shows that the phase shift is about -4.30 for asymmetrical sampling when modulating index 0.1≤ ma ≤ 1.0 whereas 0.130 (maximum) for the proposed technique which is very near to natural sampling for modulating index 0.1 ≤ ma ≤ 0.98. These results are very close to simulation result of natural sampling (Fig. 8 (b)). The DSP processor works in parallel to peripherals therefore it they do not add data transmission delay in implementation. Maximum computation time required for asymmetrical sampling is 4.964 µs which increased to 19.684 µs for proposed technique. This time is very small as compare to the sampling time (496 µs) for carrier frequency 1050 Hz and the DSP has sufficient time to perform its other tasks. Thus; the proposed technique does not require the dedicated DSP for calculation of switching instant. DSP neither requires large

12

memory nor requires supporting circuitry. It is observed that the phase shift is increased for ma > 0.98 in experimental results because dead time becomes considerably large as compared to pulse width at peak of modulating signal. Fig. 9 (a) shows voltage spectra of output pole voltage of 2L-VSI with asymmetrical regular sampling and for the modulating index ma = 0.1, 0.3, 0.5, 0.7 and 0.9. The magnitude first upper sideband harmonic is larger than the lower sideband harmonics for asymmetrical sampling, in contrast to natural sampling where the outer sidebands have same magnitude. This is well known and already presented in [17]. Natural sampling generates side band harmonics with equal magnitude [17]. Fig. 9 (b) shows that sideband harmonics of carrier have equal magnitude with the proposed technique like a natural sampling. Fig. 1(a) shows an asymmetrical sampled modulating signal for 5L-VSI. In the asymmetrical sampling, modulating signal is held constant for half carrier time. Therefore, there are chances of superfluous pulse generation in output of inverter due to the crossing of sampled modulating signal with carrier signal (encircled in Fig. 1(a)). The excess pulses (encircled) also appear in experimental results (Fig. 10 (a)) for asymmetrical sampling. Fig. 10 (b) depicts that the superfluous pulses do not exist in experiment result with proposed technique. Fig. 11 shows line voltage and three-phase current. The FLUKE 43B power quality analyzer is used to measure the THD in inverter output voltage and current. The THD in pole voltage was observed 29.0% without sine wave filter and the THD in line voltage is reduced to 12.8%. The THD in line current is observed 3.8%. VII. CONCLUSION In this paper a simple technique to approach natural SPWM technique is presented. The proposed technique reduces phase shift, minimizes error in switching instant and incorporate all desired feature of natural SPWM. The method is discrete in nature and readily implemented with DSP and is expandable to any number of voltage levels for multilevel inverter. The proposed method does not generate superfluous pulses like asymmetrical sampling. This technique is very

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simple and easy to implement on line with DSP, and it requires neither dedicated processor nor additional circuitry like FPGA nor large digital memory for any modulating index. Time required for computation is very small and DSP has sufficient time for other tasks. The proposed technique is more effective where low switching frequency is essential, particularly high power application such as FACTs System, UPS and grid connected energy systems. This technique can also be implemented by injecting zero sequence signals in modulating signals to increase the linear range of modulating index. Further switching delay of power devices and gate drive circuit can be compensated to get more precise instant of switching. Both hardware and simulation implementation have been presented for proposed technique and provide an excellent match with natural sampling.

REFERENCES [1]

Geoffrey R. Walker, “Bandwidth Considerations for Multilevel Converters,” IEEE Trans. on Power Electron., vol. 14. no. 1, pp. 74 – 81, Nov. 1999.

[2]

S. R. Bowes, D. Holliday and S. GrewaI, “Regular-sampled harmonic elimination PWM control of singlephase two-level inverters,” IEE Proc.-Electr. Power Appl., vol. 148, no. 4, pp. 309-314, July 2001.

[3]

B. N. Chaudhari and B. G. Fernandes, “ EPROM based Modulator for synchronized asymmetrical regular sampled SPWM technique,” Proc. of IEEE conference on Industrial Technology 2000, pp. 278-282, Jan. 2000.

[4]

Bakari Mwinyiwiwa, Zbigneiw Wolanski and Boon-Tech Ooi, “Microprocessor implemented SPWM for multiconverters with phase shifted triangle carriers,” IEEE Trans. on Ind. Appl., vol. 34, no. 3, pp. 487-493, MAY/JUNE 1998.

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[5]

Geoffrey R. Walker, “Digitally-Implemented Naturally Sampled PWM suitable for Multilevel Converter Control,” IEEE Trans. on Power Electron., vol. 18. no. 6, pp. 1322 – 1329, Nov. 2003.

[6]

D. G. Holmes and T. A. Lipo, Pulsewidth Modulation for Power Converters. New York: Wiley, 2003. [Holtz]

[7]

G. Ebersohn and M.N. Gitau, “FPGA-Implemented Carrier based SPWM Multilevel Controller,” IEEE conference, AFRICON 2004, pp. 1175-1178. [Kanchan]

[8]

Jannette Von Jouanne, Prasad N. Enjeti, and Donald J. Lucas, “ DSP control of high power UPS system feeding nonlinear loads” IEEE Trans. Indl. Electron., vol.43. no.1, pp. 121-125, February 1996.

[9]

Poh Chiang Loh, Donald Grahame Holme and Thomas A. Lipo, “Implementation and Control of Distributed PWM Cascaded Multilevel Inverters With Minimal Harmonic Distortion and Common-Mode Voltage,” IEEE Trans. on Power Electron., vol. 20, no. 1, pp. 90-99, January 2005.

[10] S. A. Saleh and M. A. Rahaman, “Discrete time based model of the sinusoidal pulse width modulation technique,” Proc. of Annual conference IECON 2005, pp. 1082-1087, Nov. 2005.

[11] Amit Kumar Gupta, and Ashwin M. Khambadkone, “A Space Vector PWM Scheme for Multilevel

Inverters Based on Two-Level Space Vector PWM,” IEEE Trans. on Indl. Electron., vol. 53, no. 5, pp. 1631-1639, October 2006.

[12] Victor M. E. Antunes, V. Fernão Pires, and J. Fernando A. Silva, “Narrow Pulse Elimination PWM for Multilevel Digital Audio Power Amplifiers Using Two Cascaded H-Bridges as a Nine-Level Converter,” IEEE Trans. on Power Electron., vol. 22, no. 2, pp.425-434, March 2007.

[13] Bin Wu, “High-Power converters and AC drives,” IEEE press. John Wiley & Sons, Inc. Hoboken, New Jersey, 2006.

[14] Jih-Sheng Lai and Fang Zheng Peng, “Multilevel converters-a new breed of power converter,” IEEE Trans. [15]

on Industry Application, vol. 32. no. 3, pp 509-517, May/June 1996, J. Rodriguez, J. S. Lai, and F. Z. Peng, “Multilevel inverters: A survey of topologies, controls, and applications,” IEEE Trans. Indl. Electron., vol. 49, no. 4, pp. 724–738, Aug. 2002.

[16] Giuseppe Carrara, Simone Gardella, Mario Marchesoni, Raffaele salutary, and Giuseppe sciutto, “A New

Multilevel PWM Method: A Theoretical Analysis,” IEEE Trans. on Power Electron., vol. 7, no. 3, pp. 497505, July 1992.

[17] B. P. McGrath and D. G. Holmes, “Multicarrier Strategies for Multilevel Inverters,” IEEE Trans. On Power Electronics, Vol. 49, N0.4, pp. 858-867, August 2002.

Natural 0.25526095 0.66954377 1.27396816 1.56547641 2.28374410 2.46900726 3.27895771 3.38416447 4.25607919

Table I. Instant of intersection of modulating signal and carrier signal Error in switching instant in ms Instant of switching in ms Asymmetrical Averaging Proposed Asymmetrical Averaging Proposed -0.00000495 0.23809524 0.255256 0.25526228 -0.01716571 0.00000133 -0.00281127 0.68234809 0.6667325 0.66955135 0.01280432 0.00000758 -0.00537816 1.25363801 1.26859 1.27404409 0.00007593 -0.02033015 -0.00562941 1.57369158 1.559847 1.56551763 0.00821517 0.00004122 -0.0076061 2.26356858 2.276138 2.28401583 -0.02017552 0.00027173 -0.00660196 2.47329632 2.4624053 2.46906268 0.00428906 0.00005542 -0.00711971 3.26277341 3.271838 3.27939256 -0.01618430 0.00043485 -0.00525727 3.38585170 3.3789072 3.38420175 0.00068724 0.00003705 -0.0025519 4.24709199 4.252824 4.25641716 -0.00898720 0.00033797

Table II. Switching state, switching function and magnitude of output voltage Switching state Output Sw voltage S1 S2 S3 S4 S5 S6 S7 S8 Vdc/2 1 1 1 1 0 0 0 0 2 Vdc /4 0 1 1 1 1 0 0 0 1 0 0 0 1 1 1 1 0 0 0 - Vdc /4 0 0 0 115 1 1 1 0 -1 - Vdc /2 0 0 0 0 1 1 1 1 -2 1: Switch ON,

0 : Switch OFF

2 1 0 -1 -2

0

0.01 Time in second

0.02

(a) 2 1 0 -1 -2

0

0.01 Time in second

0.02

(b) Fig.1. Asymmetrical sampling and superflaus pulses in the output of multilevel inverter (a) sampled reference signal (b) multilevel output voltage

Five Level Diode Clamped Inverter

Vdc 4

S1

Three phase load

S2 S3

Vdc 4

S4 VA

VB VC S5

Vdc 4

S6 S7

Vdc 4

S8

DSP TMS320F2812

Driver Circuit

Fig. 2 Five-level diode clamped inverter configuration to implement proposed technique

16

ma sin(t )

 tk

1

ma sin(  (t  tk' ))

Vc(t)

ma sin(t k )

Vsamp

0

tk

tk+1

4 f c t k  1

-1

Tc 

1 fc

1

natural

0 1

asymmetrical

Error 0

Fig. 3. Comparison of natural and asymmetrical sampling and proposed technique.

1.005 1.00 0.995 0.99

(a) 1.01

1.005 1.00 750

1500

3000 Frequency (Hz)

(b)

Fig. 4. Effect of approximation (a) Range of ks (b) Range of kc

17

4500

r4+

2 c4 1 c3

r3+ = r4r2+ = r3-

0 c2 -1 c1 -2

r1+ = r2r1-

(a)

C3 S2/S6

C4 S1/S5

C3 C2 S2/S6 S3/S7

C1 S4/S8

C2 S3/S7

(b)

Fig 5. (a) PD modulating carrier, modulating waveform, regions and nature of output voltage of 5L-VSI (b) contour plot of modulating signal, carrier and corresponding switches.

(a)

(b)

Fig.6. Simulation results: Intersections of modulating signal and proposed technique signal with carrier signal (a) 2L-VSI (b) 5L-VSI

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1

0

-1 20

10 Time in ms (a)

0

Magnitude in %

125 100 75

Third Harmonics

50 25 0

1000

2000

3000 4000 Frequency in Hz

5000

6000

Fig. 7 Third harmonics injection (a) Crossing instant (b) FFT (b) of output voltage of two-level inverter.

Fig. 8. Simulation and experimental results: Phase shift between modulating signal and fundamental component of output voltage inverter with (a) asymmetrical sampling (2L VSI) (b) natural sampling (2L VSI) (c) proposed technique (2L VSI) (d) Asymmetrical and proposed technique (5L VSI) (e)experimental results(2L VSI)

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(a)

(b) Fig. 9. Experimental results: FFT of output voltage of 2L inverter (a) asymmetrical sampling (b) proposed technique (shows equal harmonics band like natural sampling) for ma = 0.1 to1.0 in step of 0.2, mf = 21, fm = 50Hz.

(a)

(b)

Fig 10. Experimental results for output of 5L-VSI. (a) asymmetrical sampling shows super flaw pulses (encircled) (b) proposed technique Scale: 100V/div, 2ms/div

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