This method of remov- ing the dc offset leads to the requirement of a larger dynamic range for the analog to digital converter (ADC). 34. IEEE POTENTIALS. Fig.
As the mobile domain continues to grow, the primary design consideration of wireless receivers is based on performance under hostile channel conditions such as multipath and Doppler effects, compatibility with the existing standards, and monolithic integration that supports system on-chip topologies. Direct conversion receiver (DCR) architecture, which has introduced the zero intermediate frequency (IF) approach, supports efficient wireless handset
architecture is not suitable for monolithic integration due to utilization of several off-chip filters that make the receiver comparatively expensive and complex for multimode designs. Hence, the superheterodyne topology is not the practical candidate for multimode receivers. Conversely, the DCR supports multimode operation while eliminating the need for multiple off-chip filters. Since the superheterodyne radio has been the dominant architecture in
Direct conversion receiver for radio communication systems
is downconverted to a nonzero IF. The selection of IF causes a tradeoff between the design requirements of the channelselect filter and the RF filter. Although the selection of high IF decreases the selectivity requirements of the image-reject filter at RF, the required quality factor of the IF channel-select filter is increased. Alternatively, if relatively low IF is selected, the requirements of channel-select filter are relaxed while the specifications for the RF filters become stringent. As shown in Fig. 1, channel selectivity is performed by a passive off-chip preselect filter. Since the selectivity of the low noise amplifier (LNA) is not sufficient to remove the interfering signals at the image frequency, a passive off-chip image-reject filter is
designs with a high level of integration. The ability to eliminate the IF stage is the significant performance characteristic unique to DCR that makes the topology suitable for cellular radios with stringent design requirements. DCR has changed the receiver architecture in mobile handsets by supporting reduced component count, smaller physical dimension, and lower production cost. Hence, the growing demand for smaller and affordable handsets has led to the utilization of DCR in modern wireless mobile terminals. The implementation of the Third Generation Wireless Communication and Network Protocol and the existence of systems based on the second generation standard have tremendously increased the need for multimode wireless receivers. The requirements to support multiple modes of operation have not only increased the complexity of baseband processes but also have introduced the need for compatibility of mobile terminals in different operating modes. The superheterodyne receiver has been the dominant architecture in the wireless handset due to its superior performance resulting from the utilization of highly linear offchip filters. Although offering an adequate performance, the superheterodyne
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©ARTVILLE, LLC.
Litifa Noor and Alagan Anpalagan
cellular radio receivers, the architecture is briefly discussed. Then, a detailed description of DCR architecture is provided. After that, dc offset which is considered the main disadvantage of DCR is investigated in detail.
Superheterodyne receiver In the traditional superheterodyne approach, the radio frequency (RF) signal
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typically utilized between the LNA and mixer to attenuate the interferers. Following, the desired RF signal is downconverted to a fixed IF using a single mixer and tunable local oscillator (LO). After the down-conversion mixer, a passive off-chip channel select filter attenuates the out-of-channel signals to a sufficiently low level. A variable-gain amplifier (VGA), which follows the IF
IEEE POTENTIALS
channel-select filter, decreases the dynamic range requirements of the following stages. Although off-chip filters offer sufficient image rejection and selectivity, the input and output of each off-chip filter requires impedance matching that increases the power consumption in the RF front-end. The superheterodyne implementation of a multimode receiver requires multiple filters that not only increase the production cost but also the physical dimension of the handset. Thus, superheterodyne receiver is not a practical topology for multimode receiver designs.
Direct conversion receiver
Preselect Filter
LNA
Image Reject Filter
IF Filter
VGA
∼ LO Fig. 1 Superheterodyne receiver
multimode receivers. According to recent research publications, the suitability of DCR for multimode designs makes the architecture a promising candidate for the next-generation applications. While comparing the superheterodyne and DCR architectures, it is difficult to conclude which architecture leads to lower power consumption. In DCR, the interface to off-chip filters, which increases power consumption, has been minimized. Conversely, signal processing at IF in comparison to baseband consumes less power. As a result, the quadrature down-conversion in DCR consumes more power than the quadrature down-conversion at IF in a superheterodyne topology. In addition, the elimination of passive channel-select filters in DCR leads to the requirement of a relatively large dynamic range for the baseband circuitry in this topology. A sufficient dynamic range at baseband considerably increases the power requirements.
of a high-performance receiver a challenging task. The design challenges of the DCR include dc offsets, I/Q mismatches, even-order distortion, and flicker noise. The I/Q mismatches produce constant dc offset that can be filtered out with the utilization of ac coupling in the signal path. The even-order distortion, which is practically dominated by the second-order distortion, is generated in the LNA, downconversion mixers and the baseband circuitry. The second-order distortion produced in the LNA can be reduced with the use of a highpass filter between the LNA and the down-conversion mixers. The second-order distortion produced in the down-conversion mixers and the baseband circuitry creates distortion that has both dc and ac components. The discussion of the techniques to minimize such distortion is beyond the scope of this paper. Flicker noise, which also contributes to the design challenge of DCR, is generated in the down-conversion mixers switching transistors. Given that MOS transistors are subject to flicker noise, replacing the MOS transistors by bipolar devices can notably reduce the adverse effects of flicker noise. Since dc offset is the intrinsic drawback of the DCR architecture, the focus of this article has VGA been directed to analysis of the phenomenon causing dc offset and the suggested techniques to compensate its adverse VGA affects. The main sources of dc offset are leakage of the LO signal and RF signal self-mixing due to leakage of a nearchannel interferer to the LO.
In the DCR, the desired channel is downconverted to dc in the first mixing stage. The receiver, shown in Fig. 2, consists of a preselect filter, LNA, quadrature down-conversion mixers, low-pass filters (LPFs), and VGAs. The preselect filter is required to attenuate the out-of-band signals before the LNA. Since there is no image frequency problem in DCR architecture, the need for an off-chip filter between the LNA and down-conversion mixers has been eliminated. As a result, the LNA output drives only on-chip loads, which consist of the input stages of down-conversion mixers, instead of off-chip filters requiring matching to a low impedance level. Since the architecture uses quadrature DCR drawbacks modulation, two down-conversion mixThe DCR architecture suffers from severs are required to avoid an unrecovereral drawbacks, which make the design able loss of information. The LO signals of the two mixers have a phase shift of 90°, which produces the in-phase x LPF (I) and quadrature (Q) components. After the downLNA Preselect Filter ∼ LO 90 conversion mixers, the signal is at baseband where the x LPF channel selection is performed by integrated LPFs. Following, VGAs are utilized Fig. 2 Direct conversion receiver to amplify the baseband signal to a suitable level. Off-chip filters required in the superheterodyne receiver x LNA LPF are preselect, image reject, and IF channel select. In DCR, the preselect filter is the only filter in the signal path that cannot be integrated with LO ∼ the available technology. It can be stated that DCR achieves considerably higher integration level, which makes the design suitable for Fig. 3 Leakage of the LO signal to the input of the LNA and mixer
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x
DC offsets due to LO signal leakage LO signal leakage to LNA and mixer Figure 3 shows the leakage of the LO signal to the input of the LNA and mixer. Since the isolation between the LO port and the inputs of the LNA and mixer
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is not perfect, the LO signal leaks to the input of the LNA and mixer. The leakage signal is mixed with the LO signal resulting in a constant dc offset. The level of the offset depends on the amount of leakage and the phase shift between the LO signal and leakage. The resulting dc offset at the mixer output can be orders of magnitude larger than the desired signal.
at RF and LO ports of the mixer affects the resulting distortion component. DCoffset cancellation schemes are effective only in removing constant dc offset. Since it is very difficult to remove the in-channel baseband distortion component due to RF self-mixing of an amplitude modulated blocker after the down-conversion, the leakage of a near-channel interferer to the LO port of a mixer should be suppressed to a sufficiently low level.
rature components introduced due to transistor mismatches. The I and Q are low-pass filtered and then converted to digital I and Q baseband signals which can be represented as follows: In = In + I dc Q n = Q n + Q dc .
LO signal leakage to the antenna Since the LO signal is at the passModeling the dc offset band of the bandpass filter (BPF), it can The following analysis provides a leak to and reflect from the antenna. brief explanation of the generated dc The leakage of the LO signal to the offset in the DCR receivers. Assuming antenna, which in indicated in Fig.4, the received signal at the input of the interferes with other receivers in the LNA is presented by system. The leaked LO signal may r 1 = xt cos(ωo t) reflect back from external objects. Since the environment contains both stationary and moving objects, the level and where xt is the transmitted signal at a phase of the reflected LO signal varies carrier frequency ωo . The I and Q comaccordingly. If the LO signal is reflected ponents of the local oscillator can be back from moving objects, the result is written as follows: a Doppler shift in the frequency of the LOI = A LO cos (ωo t) reflected signal. Therefore, the reflected LO signal is downconverted to a nonzeLOQ = A LO sin (ωo t). ro baseband frequency, which depends on the speed of the external moving The output of the I and Q mixers are object. The impact of the low-frequency expressed as follows: component generated due to the I t = (wt + αI LOI (t))LOI (t) + I dc reflected LO signal depends on the amount of LO signal at the RF input. Q t = (ωt + αQ LOQ (t))LOQ (t) + Q dc In addition, directly converting the RF signal to baseband leads to signal filwhere α indicates the LO leakage, and I dc and Q dc are the in-phase and quadtering and amplification to be performed in the frequency band between dc and the signal bandwidth. Thus, the dc offset in the signal path is Preselect Filter LNA x amplified that in turn degrades the dynamic range of the receiver. The generat∼ LO ed dc offset due to LO signal leakage has to be suppressed to relatively lower levels to maintain the receiver sensitiv- Fig. 4 LO Signal leakage to antenna ity at an acceptable level.
DC offset due to nearchannel interferer leakage to the LO The leakage of a nearchannel interferer to the LO port is shown in Fig. 5. The resulting distortion component has a dc term and a spectrum, which depend on the amplitude modulation and average power of the blocker. In addition, the phase shift between the blocking signals
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LNA
x
∼
LO
Fig. 5 Near-channel interferer leakage to the LO
As indicated in the above equations, In and Qn are the transmitted I and Q components where as and I dc are Q dc the generated I and Q dc components. The generated dc offset is suppressed either in the radio frequency part of the receiver or in the baseband processing.
DC offset compensation techniques
Various methods that either cancel or compensate the adverse effects of dc offset have been suggested in the literature. The constant dc offset of signals with no useful content at dc can be filtered out using ac coupling such as high-pass filtering in the signal path. This methodology is an attractive approach from the implementation perspective in systems that utilize modulation schemes which produce minimal dc signal component. The employment of ac coupling in such communication systems removes the dc offset without distorting the signal spectrum. In spectrally efficient modulation schemes used in modern cellular systems, considerable signal spectrum is near dc. Consequently, removal of dc offset by ac coupling introduces intersymbol interference that in turn distorts the received signal. For instance, ac coupling is impractical in systems such LPF as the global system for mobile communications, which uses modulation and synchronization schemes that require dc content. As a result, such systems require design approaches that allow the dc component of the signal to pass while minimizing the intrinsic dc offset. Another suggested method to remove the dc offset LPF involves averaging the digitized baseband signal over a specified window and subtracting an approximation of the dc offset from the received signal. This method of removing the dc offset leads to the requirement of a larger dynamic range for the analog to digital converter (ADC).
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The generated dc offset may also be subject to abrupt changes resulting from variations in RF gain, LO frequency, and baseband gain. In addition, out-of-channel blockers experiencing a sudden change in the average power at the receiver input causes transitions in the dc offset. Both analog and digital highpass filtering techniques cannot effectively eliminate the quick transitions. However, the variations in the dc offset can be removed in the digital domain using realtime averaging algorithms. If the baseband gain is limited to relatively low value and dynamic range in the ADC is sufficient to tolerate the dc offsets, digital techniques can be employed to remove the dc offset. Thus, various methods that minimize the dc offset have been suggested. The utilization of a certain scheme mainly depends on the application.
Conclusions Since transmission over wireless channels is subject to time dispersion due to multipath propagation and frequency dispersion due to Doppler effect, the design of wireless receivers are tremendously important in supporting reliable communication links. With wireless technology growing, the choice of optimal wireless receiver architecture that supports monolithic integration without performance degradation is becoming an important dimension in modern handset design. The increasing demand for mobile terminals with smaller physical dimensions has led to the investigation of DCR, which supports single chip and multimode designs. The implementation of chipsets for DCR is supported by 0.35 µm BiCMOS and 0.5 µm CMOS technology. Although the utilization of DCR in mobile terminals provides notable advantages, the architecture is subject to design challenges due
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to dc offset. The employment of different methods to compensate the dc offset leads to various trade-offs. Since DCR is a promising architecture for fourth generation mobile terminals, it is important to note that implementation of a certain dc offset technique does not compromise the benefits of low complexity receiver design.
Read more about it • A. Bateman and D.M. Haines, “Direct conversion transceiver design for compact low-cost portable mobile radio terminals,” in Proc. 39th IEEE Vehicular Technology Conf., 1989, pp. 57–62. • B. Lindquist, M. Isberg, and P.W. Dent, “A new approach to eliminate the DC offset in a TDMA direct conversion receiver,” in Proc. 43rd IEEE Vehicular Technology Conf., 1993, p. 75. • A. Abidi, “Direct-conversion radio transceivers for digital communications,” IEEE J. Solid-State Circuits, vol. 30, pp. 1399–1410, Dec. 1995. • S. Sampei and K. Feher, “Adaptive DC-offset compensatison algorithm for burst mode operated direct conversion receivers,” in Proc. IEEE Vehicular Technology Conf., May 1992, pp. 93–96. • H. Tsurumi and T. Maeda, “Design study on a direct conversion receiver front-end for 280 MHz, 900 MHz, and 2.6 GHz band radio communication systems,” in Proc. IEEE Vehicular Technology Conf., May 1991, pp. 457–462. • B. Razavi, “Design consideration for direct conversion receiver,” IEEE Trans. Circuits and Systems II, vol. 44, pp. 428–435, June 1997. • H. Yoshida, H. Tsurumi, and Y. Suzuki, “DC offset canceller in a direct conversion receiver for QPSK signal reception,” in Proc. 9th IEEE Int. Symp. Personal, Indoor and Mobile Radio Comm., 1998, vol. 3, pp. 1314–1318.
About the authors Litifa Noor is an M.A.Sc. candidate at Department of Electrical and Computer Engineering Ryerson University. She received her B.Eng.degree in electrical angineering from Ryerson University in 2004. Her current research interests include design of wireless receiver architecture for the fourth generation wireless communication protocol and analysis of radio resource management in wireless communication networks. She was chair of the IEEE Ryerson Student Branch and organizing chair of 2004 International Conference for Upcoming Engineers. Currently, she is the coordinator of the IEEE Ryerson Student Branch and the VP Finance of Graduate Student Caucus at Ryerson University. Alagan Anpalagan received the B.A.Sc., M.A.Sc., and Ph.D. degrees in electrical engineering from the University of Toronto, Canada, in 1995, 1997, and 2001, respectively. He is an assistant professor and program director for Graduate Studies in Ryerson University, Canada, where he cofounded WINCORE Lab and leads the Wireless Access and Networking R&D group. His research interests are in wireless communication, mobile networks, and system performance analysis. He was Technical Program cochair, 2004 IEEE Canadian Conference on Electrical and Computer Engineering. He is an associate editor for EURASIP Journal of Wireless Communication and Networks. He is chair of the IEEE Toronto Communications Chapter and is a member of the IEEE Technical Committee on Personal Communications and Sigma Xi. He is a Registered Professional Engineer in the province of Ontario, Canada and a Senior Member of the IEEE.
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