IEEE ELECTRON DEVICE LETTERS, VOL. 24, NO. 7, JULY 2003
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Direct Tunneling RAM (DT-RAM) for High-Density Memory Applications Charles Kuo, Tsu-Jae King, Senior Member, IEEE, and Chenming Hu, Fellow, IEEE
Abstract—A new approach to reducing the tunnel oxide thickness in floating gate memories is introduced for RAM applications. Experimental measurements and two–dimensional (2-D) device simulations are used to investigate the operating principles of a direct tunneling RAM (DT-RAM) cell. DT-RAM targets memory applications in which manufacturability, scalability, low-power, high-density, and long retention times are important considerations. Index Terms—CMOS, data retention time, DRAM, embedded DRAM, random access memories, scaling.
I. INTRODUCTION
S
CALING the tunnel oxide in floating gate memories is limited by direct and trap-assisted tunneling which reduce the data retention times [1], [2]. Previous examples of direct tunneling floating gate memories designed for RAM arrays do not overcome this problem [3], [4]. DT-RAM is unique because it can use a thin tunnel oxide for fast programming with superior retention times. while sustaining a larger Operating principles of DT-RAM are examined with transistors and MEDICI simulations. II. DT-RAM TECHNOLOGY DT-RAM cells are in either a programmed or erased state. Fig. 1(a) shows the energy band diagram for the programmed state of a DT-RAM cell with a thin tunnel oxide in which there are no net tunneling currents because the Fermi levels in all three silicon regions are aligned. Fig. 1(b) shows the erased state in which five possible sources of gate leakage are shown. The first mechanism refers to conduction band (CB) electron tunneling. Since the gate voltage required at inversion is referenced to the source potential, a positive source/drain bias raises , thereby eliminating the channel inversion charge and removing the CB electron tunneling component. To demonstrate this body effect principle in a memory device, a conventional floating gate transistor with a 60 tunnel oxide is tested. Fig. 2 shows that a cycled cell incurs more leakage V. This is expected for an erased state when since the channel’s inversion charge leaks into the floating gate due to the CB electron tunneling component of the stress induced leakage current (SILC) [2]. In contrast, the same cycled Manuscript received April 2, 2003. The review of this letter was arranged by Editor A. Chatterjee. The authors are with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720 USA (e-mail:
[email protected]). Digital Object Identifier 10.1109/LED.2003.814017
cell using V eliminates CB electron tunneling, resulting in better data retention for an erased state. There is no channel inversion charge for the programmed state since the ) and . The imfloating gate is neutral (i.e., provement in retention times occurs for any tunnel oxide thickness since the lack of inversion charge directly suppresses CB electron leakage [5], [6]. The second leakage mechanism in Fig. 1(b) occurs when electrons tunnel into the floating gate conduction band from traps at the oxide-substrate interface. An erased DT-RAM cell is V, and there are neither in deep depletion since many conduction band electrons nor valence band holes in the channel. Thus, the interface state occupancy depends mainly on thermal emission rates from the traps, which is independent of the oxide thickness. In steady state, this relationship can , where and be expressed as are the emission rates of electrons and holes from traps and are interface traps filled with electrons and while holes, respectively. In the upper half of the band gap and in the bottom half [7]. Since , interface states are vacant (i.e., filled with holes) in the upper half of the band gap while electrons occupy states in the bottom half. This is studied in Fig. 3 by a quasistatic capacitance–voltage (C–V) measurement which shows that, for V, interface states trap electrons in the lower half of the band ( : body potential : surface pogap. For tential) the measurement reflects a contribution mainly from the deep-depleted substrate capacitance. In this region, interface states do not significantly contribute to the measured capacitance. As the gate voltage increases further, inversion charge appears in the channel, resulting in the capture of CB electrons by these interface states in the upper half of the band gap. This change is reflected in the rise to an intermediate capacitance and . This means that so long as the value between ), interface states in the upper cell is in cutoff (i.e., half of the band gap are mostly vacant. Thus, a first order estito (i.e., 0.55 V) in DT-RAM. mate limits In practice, however, the interface state occupancy has a small but finite spread in the upper half of the band gap. From Fig. 3, V at the point in which the fresh and stressed V C–V curves fully overlap in depletion for [8]. This indicates that the maximum voltage drop across the V for an erased state. Using the detunnel oxide can be pletion approximation [5], Fig. 4(a) shows that large changes in the floating gate voltage can still be accomodated for such a . small
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IEEE ELECTRON DEVICE LETTERS, VOL. 24, NO. 7, JULY 2003
Fig. 1. Energy band diagrams of (a) programmed and (b) erased states in a DT-RAM memory cell. No significant tunneling occurs between the control and floating gates because of the thicker interpoly dielectric.
Fig. 2. Cells exhibit better retention only if CB electron tunneling is program/erase (P/E) cycles with V : V were applied eliminated. to the device; over P/E cycling endurance has been demonstrated with thinner oxides [3]. A S/D reoxidation step was used to thicken the gate oxides in the overlap regions, ensuring that retention measurements are a result of tunneling through the channel region.
10
10
1 = 75
In Fig. 1(b), mechanisms 3 and 4 are not possible because there are no vacant states in the Si band gap to tunnel into since . The fifth mechanism these states appear below does not contribute either since the density of holes at the interface is negligible for an N floating gate [5]. DT-RAM array blocks must be monitored by a memory controller because reading will partially program a cell over time. Fig. 4(b) shows that a large number of read operations is possible before the cells in a block need to be rewritten. Programming on the order of nanoseconds is possible [9]. Thinner oxides further improve in faster programming times. and/or larger Fig. 5(a) shows that DT-RAM cells have an offset spacing to suppress gate tunneling currents through the S/D overlap regions and can be realized in a compact AND array cell [10], [11]. Note that the offset spacing places the S/D regions further from the floating gate than in commercial FLASH cells and that
Fig. 3. Quasistatic C–Vcharacteristics for single gate transistors indicate that, for V V V, interface states above the midgap are mostly vacant and do not contribute significantly to the measured capacitance until weak inversion.
=
=1
any gate current flows predominantly through the thin tunnel oxide. Thus, after repeated cycling, leakage between the S/D and floating gate is expected to be suppressed. MEDICI simulations in Fig. 5(b) show three different regions in the curves when the cell is being read. In region 1, the standard subthreshold swing is exhibited. Region 2 occurs when the channel underneath the floating gate inverts, but less current flows because of the S/D resistance induced by the offset regions which are in cutoff. In region 3, these offset regions invert, allowing electrons to flow freely from the source to drain [12]. III. SUMMARY DT-RAM offers new possibilities for scaling the tunnel oxides in floating gate memory devices. Its compact cell structure and unique operation can be incorporated in stand-alone and embedded RAM applications. These operating principles
KUO et al.: DT-RAM FOR HIGH-DENSITY MEMORY APPLICATIONS
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1
=0
1V and is the control gate to floating = q = 3:1 V, thereby suppressing hot electron
Fig. 4. In (a) and (b), DT-RAM cells can incorporate a large threshold voltage window, where V : ). In (a), the floating gate voltage is kept below the critical value in which gate coupling ratio (typically injection created from thermal generation in the depleted substrate.
0 6
Fig. 5.
DT-RAM array cell. (a) Simulated cell structure. (b) I
-V
read characteristics.
have been studied with experimental measurements and simulations and indicate that DT-RAM is a intriguing semiconductor memory technology. REFERENCES [1] S. Lai, “Tunnel oxide and ETOX™ flash scaling limitation,” in Int. Nonvolatile Memory Technol. Conf., 1998, pp. 6–7. [2] K. Naruke, S. Taguchi, and M. Wada, “Stress induced leakage current limiting to scale down EEPROM tunnel oxide thickness,” in IEDM Tech. Dig., 1988, pp. 424–427. [3] H. Hanafi, S. Tiwari, S. Burns, W. Kocon, A. Thomas, N. Garg, and K. Matsushita, “A scalable low power vertical memory,” in IEDM Tech. Dig., 1995, pp. 657–660. [4] N. Horiguchi, T. Usuki, K. Goto, T. Futatsugi, T. Sugii, and N. Yokoyama, “A direct tunneling memory (DTM) utilizing novel floating gate structure,” in IEDM Tech. Dig., 1999, pp. 922–924. [5] W.-C. Lee and C. Hu, “Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling,” IEEE Trans. Electron Devices, pp. 1366–1373, July 2001.
[6] S.-H. Lo, D. Buchanan, and Y. Taur, “Modeling and characterization of quantization, polysilicon depletion, and direct tunneling effects in MOSFET’s with ultra thin oxides,” IBM J. Res. Develop., pp. 327–337, May 1999. [7] D. K. Schroder, Semiconductor Material and Device Characterization. New York: Wiley, 1998, pp. 269–274. [8] E. H. Nicollian and J. R. Brews, MOS Physics and Technology. New York: Wiley, 1982, pp. 329–331. [9] Y.-C. King, T.-J. King, and C. Hu, “MOS memory using germanium nanocrystals formed by thermal oxidation of Si Ge ,” in IEDM Tech. Dig., 1998, pp. 115–118. [10] M. Kato, T. Adachi, T. Tanaka, A. Sato, T. Kobayashi, Y. Sudo, T. Morimoto, H. Kume, T. Nishida, and K. Kimura, “A 0.4 m self-aligned contactless memory cell technology suitable for 256 Mbit flash memories,” in IEDM Tech. Dig., 1994, pp. 921–923. [11] C. Kuo, "Scaling CMOS Memories" Ph.D. dissertation, Univ. California, Berkeley, 2002. [12] R. Tsuchiya, K. Ohnishi, M. Horiuchi, S. Tsujikawa, Y. Shimamoto, N. Inada, J. Yugami, F. Ootsuka, and T. Onai, “Femto-second CMOS technology with high-K offset spacer and SiN gate dielectric with oxygenenriched interface,” in Proc. Symp. VLSI Technol., 2002, pp. 150–151.
