terminal diode, a 3-terminal transistor and a voltage follower. Using these .... Indeed, traditional flip-flops for data retention are based on a multi-Vth design with a ...
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Disruptive ultra-low-leakage design techniques for ultra-low-power mixed-signal microsystems Denis Flandre, Senior Member, IEEE, Olivier Bulteel, Geoffroy Gosset, Bertrand Rue and David Bol, Member, IEEE
Abstract— In this paper, we describe applications of a disruptive ultra-low-leakage design technique for drastically reducing the off current in CMOS mixed analog-digital microsystems without compromising the functional performance. The technique is based on a pair of source-connected n- and pMOS transistors, automatically biasing the stand-by gate-tosource voltage of the nMOSFET at a negative voltage and that of the pMOSFET at a positive level, thereby pushing the off current towards its physical limits. Playing with gate and drain connections, we have created a family of ULP basic blocks : a 2terminal diode, a 3-terminal transistor and a voltage follower. Using these blocks, we have developed a 7-transistor SRAM cell and an MTCMOS latch with record low stand-by leakage but still high speed performance, highly-efficient power-management units for RF and PV energy harvesting and a microwatt interface for implanted capacitive sensors. Index Terms—Ultra low leakage, Ultra low power, analog and digital CMOS circuits, logic, SRAM, power management, energy harvesting, voltage reference, SOI technology.
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I. INTRODUCTION
ltra-low-power (ULP) design has long been confined to watches, RFID or biomedical niches but new horizons are opening with the increasing expectations for mobile and ubiquitous devices. Power consumption results from dynamic switching and static or stand-by leakage. The former can be mitigated by lowering total load capacitance or supply voltage, while the later calls for a drastic reduction of the off current (Ioff). In conventional CMOS design, Ioff is basically determined by the MOSFET drain current (ID) at zero gate-tosource voltage (VGS) and can hence be decreased by increasing the MOS threshold voltage (Vth), but at the expense of functional performance (i.e. speed or frequency). To get over this limitation, we have experimented disruptive ultra-low-leakage (or ULL) design techniques in which the nMOS (resp. p-MOS) FET can be automatically biased at Manuscript received April 23, 2011. This work was supported in part by the Ministry of Région Wallonne of Belgium under the NANOTIC Program of Excellence, as well as FNRS and FRIA PhD and research grants. David Bol is Postdoctoral Researcher of National Foundation for Scientific Research (FNRS) of Belgium. The authors are with the Institute of Information and Communication Technologies, Electronics and Applied Mathematics (ICTEAM) of Université catholique de Louvain (UCL), 1348 Louvain-la-Neuve, Belgium (corresponding author is D. Flandre, phone: +32-10-472540; fax: +32-10472598; e-mail: denis.flandre@ uclouvain.be).
negative (resp. positive) VGS in stand-by mode, thereby pushing Ioff towards its physical limits [1-10]. These unique designs can be exploited in a variety of ULP applications targeting ULL in stand-by or sleep operation and high power efficiency in functional operation. Such specifications appear of paramount importance in developments of innovative components such as - complex system-on-chip for portable equipments in which the SRAM leakage can represent a significant portion of the overall power consumption, - low-duty cycle systems, e.g. environmental wireless sensor networks, - RFID or implanted electronics remotely powered by an RF or inductive telemetric link, - and autonomous microsystems harvesting energy from miniaturized power sources. In this paper, we firstly describe the principles of the ULL basic blocks. In the next sections, we present implementations of ULP voltage reference, LDO regulator, charge pump, rectifier, latch and SRAM. II. PRINCIPLES OF ULL BASIC BLOCKS Our novel basic blocks consist of only 2 transistors : an nMOS and a pMOS, but on the contrary to a standard CMOS inverter, they are connected by their sources, not their drains. Interchanging the gate and drain connections, we have created a family of ULL blocks : a 2-terminal diode [3], a 3-terminal transistor [6] and a 4-terminal voltage follower [2] (Fig.1).
Fig. 1. ULL basic block family: (a) Voltage follower, (b) Transistor, (c) Diode.
The first operation principle of the ULL basic blocks is illustrated in Fig. 2 with typical ID-VGS characteristics of nand p-MOSFETs in saturation. Their Vth are selected so that the n- and p-MOS I-V curves intercept at a low current in weak inversion, at each temperature. The nMOS Vth is here
2 close to zero or even negative for sake of clear representation but without any loss of generality. If the Vth and subthreshold slopes of the two transistors vary symmetrically with temperature, as can e.g. be well achieved in fully-depleted (FD) Silicon-on-Insulator (SOI) CMOS technology as shown below, the curves will intercept for a temperature-stable VG0 bias. Conversely, if the n- and p-MOS gates are connected to the same input voltage as in the ULL voltage follower of Fig. 1(a), their common-source voltage will automatically adapt so that the same current flows in the two series transistors. This will be used to create a voltage reference in the next section.
nMOSFET with same Vth, depending on this physical leakage limit.
Fig. 3. (a) Measured I-V characteristics of standard MOS diode and ULL diode (of Fig. 1(c)) vs. n-MOSFET ID − VGS curve and (b) Measured Ioff of standard NMOS and ULL (of Fig. 1(b)) transistors in SOI technology (W = 1µm, L = 0.13µm, Vth = ±0.3 V).
III. ULP VOLTAGE REFERENCE AND LDO REGULATOR
Fig. 2. Typical saturation ID-VGS curves of common-source nMOS and pMOS transistors with Vth selected for targeting an intercept current-voltage bias point in subthreshold regime at each temperature.
The second operation principle is introduced for the ULL diode of Fig. 1(c) obtained connecting the gates of each transistor to the drain of the other. In this configuration, the circuit auto-biases so that to drive the same current in the 2 MOSFETs while the sum of their VGS equals the voltage applied across the two terminals. In forward operation (VA>VC), the two transistors are on and the ULL diode I-V is similar to that of a standard MOS diode with drain connected to gate as well as to that of a single MOSFET (Fig. 3a). In reverse operation (VC>VA), the gate of the standard MOS diode now appears connected to the source so that its leakage current is equal to the Ioff of one of the transistors. In the ULL diode, the nMOS VGS becomes more negative and the pMOS VGS more positive as the reverse voltage is increased, so that the reverse current is reduced below Ioff towards the physical leakage current of a single MOSFET. The resulting negative impedance effect will be exploited to build bistable memory cells. In the ULL n-type transistor of Fig. 1(b), the nMOS gate and drain are the input and output nodes and the pMOS gate is connected to the nMOS drain. The leakage reduction mechanism is again based on the self-biased negative/positive VGS of the n/p-MOSFETs, i.e. equal to -/+ Vdd/2 in off conditions if the n/p I-V curves are symmetrical. Fig. 3b shows measured Ioff for standard and ULL nMOS transistors in 0.13 µm SOI CMOS at room and at high temperatures. When Vdd increases, the off current first increases because VDS of both devices increase too. Then, Ioff strongly decreases as n/pMOS VGS becomes more and more negative/positive. Physical GIDL, gate or junction leakage currents limit the lowest achievable leakage for high Vds. The ULL Ioff is reduced by a factor between 100 and 10000× compared to the standard
A ULP voltage reference is created connecting the input of the voltage follower and the pMOS drain to ground, with the NMOS drain to the supply voltage (Fig. 4). The source voltage yields a reference Vref equal to –VG0 (from Fig. 2). Fig. 4 shows the temperature sensitivity and the consumption of a voltage reference implemented in 0.15µm FD SOI CMOS, with edgeless transistors (WU = 40 µm, LU = 2µm) and a size ratio of 0.2 (xN =1, xP =5) where . The die area is only 1500µm2 and the supply voltage 1 V. The measured line sensitivity is 3 mV/V and the PSRR 90dB at 13.56 MHz. The drift is about 200 ppm/°C over the whole temperature range. This is comparable to a first-order bandgap reference based on bipolar transistors, which however typically consumes at least 104 times more power at room temperature and occupies 100 times more die area.
Fig. 4. Measured reference voltage (squares) and current consumption (line) over temperature on OKI FD SOI CMOS process with Vth = 0 / -0.3 V for n- / p-MOSFETs. Vdd = 1 V. Ratio = 0.2 (WU = 40 µm, LU = 2µm, xN =1, xP =5).
This has enabled the design of an LDO regulator with very low power dissipation, i.e. 0.25µW, 95dB PSRR at 13.56MHz, a 2mV/µA load regulation, and a 10mV/V line regulation [10]. IV. ULP RECTIFIER AND CHARGE-PUMP A ULP rectifier is realized connecting the diodes of Fig.1(c) as shown in Fig. 5 by D1 and D2. Their very low leakage current property at high reverse voltage makes them very
3 efficient when inserted in the rectifier. Indeed, in order to provide a DC output voltage as close as possible to the optimum 2.(Vin-Vth)
per stage, Vth
being the threshold voltage as defined in [9], the D1 diode sine bias sets so that VA=Vin-Vth which makes it mainly reverse biased. With the leakage current reduced by a factor 2, the efficiency of such a rectifier compared to the one using standard CMOS diodes increases from 20.4% to 64.8% when using the UCL 2µm FD SOI process and from 10.47% to 79.92% on OKI 150nm FD SOI both with an input signal of 1V peak to peak and 13.56MHz carrier frequency [7, 9].
[3-5]. Cascading two diodes in reverse with one connected to ground and one to Vdd allows us to build a latch with two stable states as illustrated in Fig. 7. Ultra-low leakage is achieved thanks to the negative-VGS self bias. This ULP latch can be used in several applications.
Fig. 7. ULP latch structure and retention characteristics (0.13µm SOI CMOS).
Fig. 5. Voltage multiplier realized with ULP diodes D1 and D2.
Despite its higher sensitivity to load current, measurements of the three-stage ULP voltage multiplier designed on OKI FD SOI technology for a nominal current of 1.5µA demonstrate the superiority of the ULL design technique on a wide range of load current (1.5µA to 30µA at least) and temperature (25°C to much more than 100°C) [9].
First, an MTCMOS flip-flop can be built with the ULP latch for power-gated circuits that need data/state retention [4]. Indeed, traditional flip-flops for data retention are based on a multi-Vth design with a fast and leaky low-Vth main latch for active operation and a slow low-leakage high-Vth shadow/balloon latch for data retention. The ULP latch in Fig. 7 combines ultra-low leakage down to 3pA with high-speed operation and a reduced transistor count [4]. Second, the ULP latch can be used to build a 7T SRAM cell [5] when combined to an NMOS pass transistor for write access and 2T read buffer, as shown in Fig. 8. Both read and write are singleended and enable dual-port operation.
Prospective research has recently been extended to an ULP Charge-Pump designed onUCL 2µm FD SOI process and dedicated to photovoltaic (PV) energy harvesting applications (Fig. 6). The PV cell can be fabricated in the SOI substrate itself, below the SOI thin film which is used for the CMOS circuits [11]. Fig. 8: ULP 7T SRAM bitcell and retention characteristics (0.13µm SOI CMOS).
Fig. 6. Charge-pump realized with ULP diodes (D1).
With a PV cell of 0.5mm2 generating 7.95µW under 100W/m2 or 0.1 sun, the proposed charge-pump is able to provide 4.5µW at its output which corresponds to a 56.6% efficiency, the breakdown being 84.3% for the charge-pump itself and 63.1% for the clock generator while the PV cell gets biased at 95% of the Maximum Power Point (MPP). V. ULP LATCH AND SRAM The ULL diode shown in Fig. 1(c) exhibits NegativeDifferential Resistance (NDR) in its reverse I/V characteristic
Successful silicon implementation of this SRAM bit cell has been demonstrated in 0.13µm SOI technology on a 256-cell column in [5]. It achieves a leakage reduction higher than 1000x when compared to conventional high-Vth 6T SRAM cells, as shown in Fig. 8. Leakage below 1pA/bit was measured at 0.8V with access time below 3ns. Studies based on predictive models show nice scaling perspectives in sub45nm CMOS technologies provided that high-K/metal gate are used to prevent gate leakage from ruining the physical leakage limit. VI. ULP EMBEDDED MICROSYSTEM Our various ULP blocks have been associated to design an implanted ULP microsystem including a capacitive sensor interface and power and data transfer units based on an inductive coupling link with a carrier frequency set at the 13.56MHz HF standard for biomedical applications (Fig. 9), in OKI 150nm FD SOI CMOS technology [10].
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Fig. 9. ULP microsystem overview.
The power management circuit is composed of two functions presented in Sections III and IV: an AC/DC voltage rectifier to convert the input 13.56MHz signal into DC power, and a low-dropout (LDO) regulator to provide a controlled 1V DC voltage to the sensor interface circuit. The sensor interface is based on a delay chain of ULP inverters built with the N- and P-type ULP transistors (of Section II) loaded by the capacitive sensor [10]. As shown in Fig. 10, we consider a capacitance range of 1-10pF, which is typical for implantable MEMS pressure sensors. A reference delay chain is added and time-to-digital conversion is achieved by enabling a simple 8 bits counter with a XOR of the delay-chain output signals. The overall capacitance-to-time conversion is plotted in Fig. 10. Resistance against PVT variations is achieved by driving the counter with a clock generator based on a 3-stage ULP ring oscillator whose drifts match those of the delay chains. The generated clock frequency is 11MHz, which results in a time resolution of 91ns. This corresponds to a 0.6% full-scale resolution on the sensed capacitance, with a maximum sampling rate of 7kS/s. The simulated power consumption is 1.1µW. Finally, Table 1 summarizes the performances of the proposed ULP circuits that allow for reaching µW power consumption for the overall microsystem. As we showed, the ULP technique can also further be extended to other circuits such as logic and SRAM presented in Section V, as well as other applications e.g. hightemperature industrial monitoring.
Fig. 10. Capacitive sensor interface with simulated capacitance-to-time conversion.
ACKNOWLEDGMENT The authors would like to thank J. Ida, formerly with OKI, for his support. REFERENCES [1] [2]
Patents : PCT/EP01/15023, US 6870229, EP2008/055239. S. Adriaensen, V. Dessard, D. Flandre, «25 to 300°C ultra-low-power voltage reference compatible with standard SOI CMOS process», Electronics Letters, vol. 38, pp. 1103-1104, 2002. [3] D. Levacq, C. Liber, V. Dessard, D. Flandre, “Composite ULP diode fabrication, modelling and applications in multi-Vth FD SOI CMOS technology”, Solid-State Electronics, vol. 48, pp. 1017-1025, 2004. [4] D. Levacq, V. Dessard, D. Flandre, “Ultra-low power flip-flops for MTCMOS circuits”, IEEE Int. Symposium on Circuits and Systems (ISCAS), pp. 4681-4684, May 2005. [5] D. Levacq, V. Dessard, D. Flandre, “Low leakage SOI CMOS static memory cell with ultra-low power diode”, IEEE Journal Of Solid-State Circuits, vol. 42, pp. 689-702, March 2007. [6] D. Bol, J. De Vos, R. Ambroise, D. Flandre, J.-D. Legat, «Building ultra-low-power high-temperature digital circuits in standard highperformance SOI technology», Solid-State Electronics, vol. 52, pp. 1939-1945, Dec. 2008. [7] G. Gosset, B. Rue, D. Flandre, Very High Efficiency 13.56MHz RFID Input Stage Voltage Multipliers Based on Ultra Low Power MOS diodes. IEEE Int. Conf. on RFID, April 16-17, 2008, Las Vegas, Nevada. [8] D. Bol, J. De Vos and, D. Flandre, " Ultra-Low-Power High-NoiseMargin Logic with Undoped FD SOI Devices", IEEE Int. SOI Conf., 2 p., Oct. 2009. [9] G. Gosset, D. Flandre, «A very high efficiency ultra-low-power 13.56MHz voltage rectifier in 150nm SOI CMOS», IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) Singapore, Dec. 2009. [10] G. Gosset, D. Bol, G. Pollissard-Quatremère, B. Rue, D. Flandre, "Disruptive ultra-low-power SOI CMOS circuits towards µW medical sensor implants", IEEE Int. SOI Conf., 2 p., Oct. 2010. [11] O. Bulteel, R. Delamare, D. Flandre, «High-efficiency solar cell embedded in SOI substrate for ULP autonomous circuits», IEEE International SOI Conference, California/USA, 5-8 Oct. 2009
