T he Libyan Arab International Conference on Electrical and Electronic Engineering LAICEEE 23-26/10/2010
Double data buffer design approach in 64-bit PCI-X Master/Target bus for high speed embedded systems and PC servers G. SumathiFaculty of Engineering, Nalla Malla Reddy Engineering College, Hyderabad, Andhra Pradesh, India, Tel: +91-9000537597
[email protected] V. Kumara Swamy, Faculty of Engineering, Dept. of EE, Sirte University, Sirte, Libya, Tel:+218917084428 / Fax: +2185465461,
[email protected] Prabhu G Benakop, Senior Member, IEEE, Director, Aurora Technological Research Institute, Hyderabad, Andhra Pradesh, India, Tel: +91-9866666651,
[email protected]
ABSTRACT: The Peripheral Component Interface-Extension (PCI-X) is a high speed bus structure, the new PCI extension, became a real standard for embedded systems as well as for PC servers. PCI-X increases PCI's bandwidth potential, especially for burst transactions. Compaq, HP, and IBM developed it. The PCI-X includes behavioral models like master, target, and arbiters. The 64-bit PCI-X master/target core is designed so that user interface can operate at any clock speed independent of the PCI bus speed. The user interface clock and PCI-X bus clock can be synchronous or asynchronous to each other. The PCI-X core utilizes double write buffer for write posting in both the master and target directions. The double data buffer design approach allows data access by the user interface and the PCI interface simultaneously and independent from each other. Thus the data transfer takes place at a faster speed in PCI-X compared to PCI bus. In this paper, we achieved higher speed and optimized transistor count compared to the other bus structures available for data transfer. This paper discusses overview of architectural design, master write buffer design, target read buffer design, target write buffer design, and master read buffer design, configuration registers design, overall design and their simulation results and proves that the double data buffer design approach enhances the speed of PCI-X Master/target Keywords: PCI, PCI-X, Master, Target, Buffer, and Controller
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signal voltages are still allowed. It also added transaction latency limits to the specification 4. PCI 2.2 Power rails to provide 3.3 volt supply voltage are now mandatory. 5. PCI 2.3 permits use of 3.3 volt and universal keying, but does not allow 5-volt keyed add-in cards. 6. PCI 3.0 is the final official standard of the bus, completely removing 5-volt capability. 7. Mini PCI is a form factor of PCI 2.2 for use mainly inside laptops 8. Card Bus is a PC card form factor for 32-bit, 33 MHz PCI 9. Compact PCI uses Euro card-sized modules plugged into a PCI backplane. 10. PC/104-Plus is an industrial bus that uses the PCI signals lines with different connectors.
Introduction
A bus is basically a collection of wires which is responsible for interconnecting the various components of a microcomputer together in order to allow the exchange of data between these components. Devices operating on a bus can be divided into three categories, i.e., Bus masters, Bus slaves and intelligent slaves as shown in figure1. Bus masters are devices capable of initiating any bus cycle (memory read/write, port addressing, etc.). Bus slaves are devices which are not capable of initiating a bus cycle but merely responding to it. Intelligent slaves have their own intelligent controlling devices but do not assert control over the bus.
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PCI BUS
It is a high performance bus for interconnecting Chips, expansion boards, and processor/memory Subsystems. It is originated at Intel in early 1990s. Standard method of interconnecting chips on a board. PCI was used in personal computers in 1994 for the Intel’s 486 processor. Fig1. Block diagram of PCI bus system 2.1. PCI Specifications: 1.
2.
3.
PCI 1.0, which was merely a component-level specification, was released on June 22, 1992. PCI 2.0, which was the first to establish standards for the connector and motherboard slot, was released on April 30, 1993. PCI 2.1, released on June 1, 1995, allows for 66 MHz signaling at 3.3 volt signal voltage (peak transfer rate of 533 MB/s), but at 33 MHz both 5 volt and 3.3 volt
Master function is to initiate PCI memory and IO read/write, automatic transfer of control between master and target, restart on target retry and disconnect. Target Function is to perform Memory or IO read/write, Configuration read/write, and supports high speed bus request. Arbiter Function is to arbitrate between multiple bus masters on the PCI bus and implementing rotating priority and fixed priority.
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PCI-X Bus and its specifications
PCI-X is a high-performance variant of 64-bit PCI designed for servers. PCI-X adapters and slots are backward-compatible with 32-bit PCI slots and adapters. 1. PCI-X 1.0 increased the maximum signaling frequency to 133 MHz (peak transfer rate of 1066 MB/s) and revised the protocol. 2. PCI-X 2.0 permits a 266 MHz rate (peak transfer rate of 2133 MB/s) and also 533 MHz rate (4266 MB/s — 32× the original PCI bus), expands the configuration space to 4096 bytes, adds a 16-bit bus variant (allowing smaller slots where space is tight), and allows for 1.5 volt signaling It is a 64-bit PCI-X bus, supports for 32/64bit data transfer. It fully supports PCI and PCI-X protocol and is designed for PLD implementations. It is an efficient user interface for different types of user devices. The user interface and PCI interface runs at different clock speed. It includes data buffer and synchronization logic to bridge the two clock domains. It automatic detects of PCI and PCI-X bus systems. It consists of combined bus master and target functions. Master initiates PCI-X memory and IO read/write, automatic transfer restart on target retry and disconnect. Target performs memory or IO read/write, Configuration read/write and Split transaction operations.
Fig 2. Architecture of 64-bit PCI-X Master/Target PCI-X master/target can operate in both PCI mode and PCI-X mode as shown in figure2. It provides easy integration with other user logic, supports PCI version 2.2 and PCI-X version1.0. User interface can operate at any clock speed independent of PCI bus speed. PCI-X utilizes double data write buffer for write operation in both the master and target direction. Double data buffer design allows data access by the user interface and the PCI interface simultaneously and independent from each other. During master operation, the controller is capable of initiating memory or I/O read and writes upon user requests. Burst size is specified by the user for each transaction. During target operation, master target core monitors the target device signal on PCI-X bus and transfer data to the user logic. All types of transfer terminations such as retry, disconnect and split response are handled by PCI-X. The target controller is capable of handling memory and IO accesses on the PCI and PCI-X bus. Configuration register read and write transactions are supported locally by the bus target without assistance from the user logic. Memory and I/O write to the target are posted in the write buffer before they
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are transferred to the user. Memory and I/O read are handled as delay read on PCI bus and as split transaction on PCI-X bus. The user interface allows the user to control the characteristics of access.
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Architectural Design
Fig 5 Interface of Master Write Buffer
In this section of paper, the concentration is on design of interface for various blocks of 64-bit PCI-X Master/Target. Configuration register as shown in figure3, has first written with control word of 8-bits based on configuration read/write signal. The output of this register is the user request signal for various operations as per user choice.
Fig 3 Interface of Configuration Register The Master Controller will receive the user request input and generates the control signals for Memory or IO read/write operations, receive/transmit mode, target retry and disconnect signals shown in fig4.
Then at the target, target read buffer reads the data from master write buffer for the user connected at the target end shown in fig6. This is the data flow from Master to target as shown in fig2. Here target acts as slave.
Fig 6 Interface of Target Read Buffer When target wants to transmit data, then master transfers the control to the target and target will hold the function of master. Thus the user request is given to the target controller from configuration register. Target controller checks for bus status whether bus is free or busy. If bus is free and target is ready for data transfer, then it will generate memory or IO read/write control signals shown in fig7.
Fig 4 Interface of Master Controller If transmit mode is selected, 64 bit data is written in to master write buffer as shown in fig 5 Fig 7 Interface of Target Controller
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Data is written in to target write buffer when chip select is enabled shown in fig8.
Fig 11 Interface of Address Buffer
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Results and Discussion
Fig 8 Interface of Target Write Buffer Master read buffer reads data from target write buffer when bus status is active shown in fig9. This operation completes the dataflow from target to master end user.
The PCI-X includes behavioral models like master controller, target controller, data and address buffers and parity generation and detection modules. All these modules are programmed using Verilog HDL and simulated using ModelSim EDA Tool from Mentor Graphics. Configuration register gives control word also called as user request to the master/ target controller based on which is transmitting the data.
Fig 9 Interface of Master Read Buffer Parity generation and detection module generates parity during transmission and detects parity during reception as shown in fig10 . Fig 12 Configuration Register Simulation Result
Fig 10 Interface of Parity Generation and Detection
Read/write buffers are designed in both the directions of data transfer from master to target and target to master. Observe the data written in to master write buffer in different locations as shown in fig13.
Address buffer (fig11) stores the address location of data stored.
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Now the data transfer taking place from target to master shown in fig16 to fig17.
Fig 13 Master Write Buffer Simulation Result Fig 16 Target Write Buffer Simulation Result
Target read buffer s reading the same data from output of the master write buffer shown in fig14 and fig15. Thus it completes data transfer from master to target.
Fig 17 Master Read Buffer Simulation Result
Fig 14 Target Read Buffer Simulation Result
This is bidirectional data transfer independent of each other with the double data buffer design approach.
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Fig 15 Target Read Buffer Simulation Result Continued
Conclusion
The 32/64-bit PCI-X master/target core is designed so that user interface can operate at any clock speed independent of the PCI-X bus speed. The user interface clock and PCI-X bus clock can be synchronous or asynchronous to each other. The PCI-X core utilizes double data buffer
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for write posting in both the master and target directions. The double data buffer design approach allows data access by the user interface and the PCI interface simultaneously and independent from each other. Thus the data transfer takes place at a faster speed in PCI-X compared to PCI bus. In this paper, the PCI-X with double data buffer design approach has achieved twice the speed (266MHz) compared to the design speed (133MHz) achieved in PCI-X without double data buffer design approach. The Simulation tool used is ModelSim and the synthesis tool is Leonardo Spectrum from Mentor Graphics.
Related work: 1. Altera is implementing Compaq's PCI-X bus controller, as a core for its FPGAs. This Altera PCI-X MegaCore function was originally implemented by Compaq in multiple ASICs. It implements a 64-bit master/target PCI-X interface, but supports both 32-bit and 64-bit operation. PCI-X able to work at both the PC system I/O bus level and at the system bus level. Drive capability is expected to reach five to seven boards. 2. In-silicon has announced a PCI-X design package, TymeWare. This package integrates a PCI-X bus controller with a bus test environment. The core is made up of synthesizable RTL blocks that can be used for ASIC or FPGA development of a PCI-X bus controller. The PCI-X development environment includes both PCI 2.2 and PCI-X behavioral models (master, target, and arbiters) and a protocol/timing monitor. 3. DCM Technologies also supplies a PCI-X bus controller core, the Corex-V10 PCI-X. This core comes in a netlist
version that supports 133-MHz, 64-bit PCI-X operation. In fact, DCM is pushing the core controller's 133-MHz operation as an enabler for high-bandwidth Gigabit Ethernet. 4. Agilent—Its E2929A PCI-X Exerciser and Analyzer supports 32-/64bit with bus rates to 133.4-MHz operation. It consists of a PCI-X Protocol Checker, a PCI-X Analyzer, a PCI-X Exerciser and a C-API Interface, and PPR (software). Its PCI-X protocol checker verifies 53 PCI-X protocol implementation rules. The tester also provides the option to link a logic analyzer to the PCI-X signals for deeper signal analysis. It comes with a ready-touse library of stress tests. The E2929 is a short PCI formfactor card. 5. Catalyst—Its TA700 PCI/PCI-X Analyzer and Exerciser supports 32-/64bit, 66-MHz bus operation. It has a 750MHz timing analyzer and a 10-GHz (100ps) set-up and hold timing violations detector. It has automated PCI Device Compliance test and verification. This unit can be controlled from the PCI-X bus itself by the system host. Additionally, the PCI-X tester card has an auxiliary PCI expansion connector on top for accepting a PCI device 6. VMEtro—Its PBT-615 PCI-X Bus Analyzer and Exerciser supports 32-/64bit operations with speeds up to 100-MHz (sampling rate). It has a 500-MHz Timing Analyzer with a 16 Msample trace buffer. It also supports PCI at rates up to 66-MHz operation. It is a short PCI formfactor card. It connects to a host PC via a front panel connector with USB or RS-232 serial connections.
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Technical Papers: 1. PCI-X Moves Out Tech OnLine Publication Date: Jun. 9, 2000 2. of
PCI-X 2.0: The Next Generation Backward-Compatible PCI Sujith Arramreddy and Dwight Riley Server Works and Compaq
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64-bit PCI-X Master/Target Eureka Technologies
References Web Sites:
www.in-silicon.com www.dcmtech.com www.eurekaTech.com
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