Self-calibration Method for Input/Output Termination ... - IEEE Xplore

2014 IEEE XXXIV International Scientific Conference Electronics and Nanotechnology (ELNANO)

Self-calibration Method for Input/Output Termination Resistance Variation Elimination Melikyan Vazgen Sh., Aleksanyan Ani L., Galstyan Vache A., Harutyunyan Ani S. Department of Microelectronics Circuits and Systems State Engineering University of Armenia Yerevan, Armenia Synopsys Armenia CJSC, [email protected], [email protected], [email protected], [email protected]

information degradation in semiconductor circuits. Hence, the calibration method of termination resistors is necessary.

Abstract — A method of on-die resistance self-calibration for receiver and transmitter Input/Output devices, without external reference resistor is presented. Resistance mismatch elimination method, using reference clock and dc current is provided. The proposed method provides opportunity to measure the difference of the termination resistor and the transmission line impedance which is assumed 50-Ohm, detect the variation and minimizing it. A self-calibration technique for termination resistors mismatch elimination is implemented. Keywords — Resistor; self-calibration; mismatch; integration; mixed-signal system; variation.

I.

INTRODUCTION

Fig. 1. The reflection of two resistors

With continuous shrinking of CMOS technology sizes, the production of integrated circuits (IC) and parameter accuracy, become technologically more complicated. As a result in high speed systems signal delays in IC long lines are an important factor and their effects cannot be ignored [2].

To avoid mentioned phenomena the termination resistance of receiver or transmitter must be equal to transmission line resistance value. Usually the impedance of transmission line [3] is assumed 50-Ohm (R0=50 Ohm). In order to avoid reflections, 50-Ohm terminations in the near and far ends of the line are required.

Interconnects are considered transmission lines if signal delays are commensurable with their transition times [1]. I/Os and transmission lines are main factors limiting the operating frequency of high speed devices by causing voltage reflections. To reduce this impact, signal termination is required [2].

Various correction methods [4,6] have been implemented to eliminate this phenomenon, which are based on usage of an external resistor [3]. Main disadvantage of these methods are the ineffective usage of IC area, as large area is required to locate the external resistor [7].

Excessive reflections in transmission lines can cause falsetriggering of logic gates, which can cause the system functionality to fail under certain PVT conditions (high temperatures, over-voltages) [3]. Signal delays in long lines are important factors in high speed systems and interfaces, hence their effects cannot be ignored.

The proposed system, in the contrary, is based on selfcalibration and all operations are being performed inside the IC, without using of any external resistor. Hence this method saves a large of part of area in PCBs (Printed Circuit Board) which is now is extremely necessary. The disadvantage of this system is that the accuracy depends on the no ideality of the schemes such as comparator. However this phenomenon doesn’t affect the final required results more that 10%.

The signal amplitude reflected at the end of a transmission line is determined by the reflection coefficient Kr(1) [3].

Kr ~

R −R Iin ~ term 0 Irefl Rterm + R0

(1)

II.

The diagram representing self-calibration circuit principle is presented in Fig.2. The calibration starts with the “start” signal, during which the ‘clk’ signal should be present. “Control logic” is the control block which triggers operation of the rest sub blocks with help of the synchro signal. As mentioned the work of this system is based on the reference clock (synchro signal). Pulse width of ‘clka’ signal is decreased 3 times after passing through a special digital circuit in the “Control logic” block.

where R0 is the characteristic impedance of transmission line, Rterm is the termination resistor in the far end of line (Fig.1.). As it is seen from (1), in order to eliminate reflections (Kr=0), Rterm and R0 must be matched (i.e. the same). If source impedance and R0 are not equal, reflections also occur at the near end of the transmission line. Each end of the line has its own value of reflection coefficient. The inequality of output resistance and interconnect resistance will cause a signal reflection and therefore the

978-1-4799-4580-1/14/$31.00 ©2014 IEEE

PPROPOSED SELF-CALIBRATION CIRCUIT ARCHITECTURE

156


Fig. 3. Active Integrator

In the first case the integration begins, when a bias voltage is given to the one input of operational amplifier, and a constant resistance is attached to the other input. From the scheme of the active Integrator is known that (Fig.3,(a)).

(V

Fig. 2. Self-calibration circuit of Resistors

Vout1 =

Main functional blocks of the I/O edge resistance equalizer are the operational amplifier, the resistance chain (matrix) (1) which is responsible for integration and the analog to digital converter (2). The other blocks provide the correct performance and stability of overall circuit (3), as well as the control functions and connection to subblocks (4). At first the Logic block sends the “clka” to the “Analog block” for integration, the “clk_2” synchro signal to the ADC (Analog Digital converter) [9] with binary encoded output which gives binary codes to the logic block for second integration and clk_3 to the “logic block” where are located the Memory device, divider, Successive Approximation Register (SAR), and digital blocks which are synthesized by “Design Compiler” using of Verilog code [10]. Taking into account the logic of the Successive Approximation Register (SAR) is used here. At first due to controlling by Control logic block the SAR is reset to the initial state, by waiting the upcoming binary codes.

− V )t in RC

(2)

In the second case (Fig.2,(b)), R - resistance in parallel with the parallel chain of resistors (RT), of Fig.1 (b) of the integrator scheme is derived by the following eqaution:

Vout 2 =

( R + R )(V − V )t T ref in RR C T

(3)

From the (2) and (3) the differences of the voltages with help of OA’s deep feedback loop are adjusting the resistance value. Vout1 and Vout2 comparison is equivalent to 1 / R and 1 / (RT + R) comparison:

V

R out 1 = T (4) V (R + R) out 2 T According to the (4), theVout1 ,Vout2 ratio shows the variation of the resistors. Difference between Vout voltages will be caused only by resistors mismatch in the case, when both resistors (R and R|| RT) are charged with the constant current and the capacitor value(C) is the same.

The “Control Logic” block controls and regulates the delays of the clocks of the different blocks, providing the correct work between subblocks. After getting generated binary codes the control logic issues the “end” signal which informs that the calibration is completed. III.

ref

It is worth to mention, that as the formula states, voltage difference in this method is proportional the resistance deviation, variations of capacitance and t don’t affect the comparison results, and the variation of Ic depends on the resistance variation. Depending on the comparison results the value of RT can be changed by means of parallel resistances. (Fig.2,(b)). The idea in this method is that the values of the differences of two integrated signals is compared and captured, which is transformed to an appropriate code, which after comparison with the already existed code of an ideal condition, takes the difference of that codes with help of OA feedback loop, i.e by connecting or disconnecting parallel resistances in the second variant, gets the requested resistance value.Parallel resistances switch turn on or off with help of transistors which gates are controlled by binary codes. The common formula for resistance circuit is defined as follows:

THE ANALOG CIRCUIT DESCRIPTION

The “Analog logic” is the main circuit, which is responsible for integration, the offset detection and regulation the value of resistance chain.The mentioned block is activated with the positive edge of “clka” signal which is generated from “control logic” block. The main subblock of the Analog circuit is the integrator without and with resistance chain in. Resistance chain is turn on or off with help of switch. Presented system is based on integration phenomenon implemented with synchronous signal. As known, active integrator can be implemented on operational amplifier (Fig.3,(a)). In this scheme a cascade telescopic operational amplifier is used with differential output as a operational amplifier. Integrator starts work only when the synchro signal is available and the integration begins with the positive slope of the synchro signal.

157


1 1 1 = + RT Rb Ri

“Analog block” to switch on or off the appropriate resisters of resistance chain. After getting the required code one testing cycle goes again to test the code and if the code is correct and the comparator does not switched and the “Control block” produces the “End” signal which means that the operation is finished and the Dcntrl code is saved in memory register.

63

∑ bi

(5)

i=0

Here the bi is the binary code, Rb is the initial resistance, whom must be parallel connected the resistance circuit (chain), Ri is the unity resistance value of resistance circuit, RT is the value of derived overall resistance of the resistance chain. IV.

V.

SELF-CALIBRATION CIRCUIT OPERATION PRINCIPLE

As was mentioned above, the integrator starts its work with positive slope of tclk which generates “Control block” when the “start” signal is active and after integration the output of the “Integrator and Resistance chain” (Fig.4) will be defined as:

Vout =

(Vref −(Vdd −Vref )) Δt

(6) RC In the first integration when input voltage of operational Amplifier is connected only with Rref without resistance chain in the (6) equation R=Rref and after the second integration R=Rref|| ∑ RT where:

The high level of “clka” used for integration is three times longer than the reference clock’s high level duration. In order to get a measurable differences of two integration graphs, the sychro signal integration time should be greater, therefore clka’s high level’s time is greater than the time of low level (Fig.5 ). The first integration begins (Fig.5) when a bias voltage Vdd/2 is given to the one input of the operational amplifier, and the other is connected only to the constant resistance (R=Rref) without resistance chain (Fig.2,(a)).

63

Rb Ri ∑ bi i =0 ∑ RT = 63 Rb + Ri ∑ bi i =0

SIMULATION RESULTS

The main block is self–calibration circuit of the resistors shown Fig.3. Simulations are performed using HSPICE simulator [11] for a number of PVT corners including 5 main conditions (TT, FF, SS, FS and SF processes with respective voltage and temperature values) [11]. Fig.5 and Fig.6 show the simulation TT(55) typical corner.

(7)

Fig. 4. Self-calibration circuit

Fig. 5. The graphs of synchro signal and the first phase of integration

Where Rb is the initial basic resistance with which must be connected the resistance chain, Ri is the unit resistor’s value of the resistance chain (matrix) step and bi is the binary code. From the first integration’s voltage value (6) ADC with binary encoded output gives the appropriate binary code dRref (Fig.4.) which is in this case is 6 bit which is saved in memory register in“memory block” for waiting to the second code dRref||dRT appropriates voltage of the second integration voltage. Due to divider the difference code between two binary codes dRref and dRref||dRT is given to the logic block where it was compared with already exist ideal code which was already counted by the (7) with help of digital mechanism in “logic block” and the output Dcntrl1 binary code, for which: Dcntrl1 = F(dRideal,dRref/dRref||dRT). With help of Decoder (6X64) Dcntrl1 binary code is changed to the Dcntrl unitary code which from “Logic Block” goes to the

During the second integration, R resistance is used in parallel with the resistance chain of RT resistors (Rref ||RT ). The second integration compared with the previous integration is faster, because the parallel connected resistance chain decreases the overall value of the resistance and the current becomes greater (Fig.6). It is seen from waveforms that the differences between Vout1 and Vout2 voltages at dt moment represents the actual difference in the Rref and Rref ||RT resistances which is the key objective of this technique. The results of integration (Fig.4) of the differences between ∆Vout1 and ∆Vout2 where:

ΔVout1 =

158

dt (Vref −Vdd ) Rref C

(8)


ΔVout 2 =

(Vref −Vdd ) dt ( RT + Rref ) Rref RC

Increasing the number of the bits (d[n:0]) allows achieve higher output accuracy, which is limited by the sensitivity of comparator.

(9)

The accuracy of the scheme is the deviation from the resistance value, depending on the scheme of parameters deviations such as non ideality of comparator which switches in case when the difference of input voltages is 0.086mV, which does not introduces no more than 10% total accuracy error. The maximum value resistance offset this technique is 8.6% ( correspondent to the worst case of conditions), which is appropriate the standards of I/O devices as DDR2, DDR3, LPDDR2, PCI and USB. VI.

CONCLUSIONS

An on-die resistance self-calibration system for receiver and transmitter I/O devices is presented and the respective circuit is designed without external reference resistor. The presented solution of resistance mismatch elimination is based on usage of reference clock and dc current. It also provides opportunity to measure the difference of the termination resistor and the transmission line impedance (which is assumed 50-Ohm). The scheme of this method is the system of mixed signals. Circuit simulation is performed and the results of the simulation are presented.

Fig. 6. The integrating impulses of the comparator’s output voltages with switched off and on the resistance chain switched off and on

From (8) and (9) is the ratio of the voltages is the following:

The shown self-calibration technique can be used in the special input/output circuits of several standards such as Peripheral Component Interconnect (PCI), Universal Serial Bus (USB), Double Data Rate (DDR) etc.

ΔVout1 RT = (10) ΔVout 2 ( RT + Rref ) The value of the resistance will be corrected by the feedback and by the code of the corresponding ratio.

REFERENCES [1]

After mentioned two integrating cycles, additional test cycle is performed by the control logic block in order to check the already generated binary code which is the digitized value of the appropriate voltage which corresponds to the corrected value of termination resistor and wire resistances.

[2]

In ideal case (transmission line resistance and wire resistance are equal, i.e 50ohm), the output voltage operational amplifier is 0.563v and the appropriate binary code of D1=011011 is generated by the ADC/Encoder block. The generated binary code is then transferred to the unitary code triggering 27 parallel resistors on, with help of deep feedback of operational amplifier. All resistances in the resistance chain are switched off in the reset state.

[3]

[4]

[5]

In this simulation the actual transmission line resistance is given 15% of offset which is equal to the 59.5 ohm. In this case the difference of the integration voltages (∆Vout1 and ∆Vout2) is 0.527v which is different from the ideal (0.563v) by 0.0361v. The appropriate binary code for this offset is 001101, which is compared with binary code of the ideal state. Then the unitary code of the difference is passed to the resistance chain and appropriate resisters are switched.

[6] [7]

[8] [9]

Getting adjusted resistance value “Control Logic” block gives ''stop'' signal to the integrator (Fig.4) and the output binary code is registered in the register.

[10] [11]

159

Tao Liang, Stephen Hall, Howard Heck, Gary Brist “A Practical method for Modeling PCB Transmissin Lines with Conductor Surface Roughness and Wideband Dielectic Properties” IEEE , 2006. Reydezel Torres-Torres, Víctor H. Vega-González “An Approach for Quantifying the Conductor and Dielectric Losses in PCB Transmission Lines” IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, Portland, OR, pp.235-238, 2009.

Hiroki Shimada, Shohei Akita, Yusuke Kuribara, Ikuo Yoshihara, and Moritoshi Yasunaga ‘Signal Integrity Improvement in Lossy Transmission Line Using Segmental Transmission Line’ 2012 Yongping Fan and Jeffrey E. Smith “On-Die termination Resistors With Analog Impedance Control for Standard Cmos Technology” IEEE Journal of solid-state circuits , vol.38, no.2, Fabruary 2006 YC. H. Line, C. H. Tsai, C. N. Chen, S. J. Jou ”4/2 PAM Serial link Transmitter with Tunable Pre Emphasis,” IEEE ISCAS pp.952-955, May 2004 Altera Corporation, San Jose ,CA (US), Ver 1.1, Aug 2005 H. Chang-Kyu , Stevan J. Cahill ”Parallel Resistor circuit, on die termination device having the same, and semiconductor memory device having the on-die termination device ” Dec. 31, 2009 Baker, Kevin Thiele, Johan Huijsing, A High Swing CMOS telescopic operational amplifier, by Anton 2000. Yun Chiu, High-Performance Pipeline A/D Converter Design in Deep-Submicron CMOS, University of California, Berkley, 2004. Michel John Sebastian Smith Application-Specific Integrated Circuits an Introduction VHDL & VERILOG HDL,2001. Hspice Application Manual, Synopsys Inc. -2010., -196p.