DRAM Data Retention and Cell Transistor Threshold ... - IEEE Xplore

406

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 12, NO. 2, JUNE 2012

DRAM Data Retention and Cell Transistor Threshold Voltage Reliability Improved by Passivation Annealing Prior to the Deposition of Plasma Nitride Layer Chung-Yuan Lee, Chao-Sung Lai, Senior Member, IEEE, Chia-Ming Yang, and David H.-L. Wang

Abstract—We report, for the first time, that the fail bit counts of dynamic random access memory (DRAM) reduced by 18% and the yield loss after packaging induced by data retention degradation decreased by 1.16% for a trench DRAM cell; this reduction was attributed to a change in the process position of passivation annealing. Moreover, the cell transistor threshold voltage (CTVth) shift was reduced to 53 mV, and the uniformity of the CTVth was improved from 100 to 38 mV; this provided the DRAM cell with a large margin for further reducing both the dose of the threshold implant and the electrical field. We proposed a possible mechanism of carrying out passivation annealing prior to the deposition of a plasma nitride layer in order to increase the supply of hydrogen for the passivation of the crystalline defects as well as improving data retention. The CTVth was increased by breaking of weak Si–H bonds by plasma charging during the deposition of the plasma nitride layer. Data retention degradation after the packaging process (∼ 250 ◦ C) reduced because of the presence of a number of strong Si–H bonds, indicating the presence of a greater number of interface trap states near the storage trench than near the bit line, as observed in the case when hot-carrier stress was applied under two conditions. Results of data retention analysis show that the fail bit counts are primarily influenced by the junction leakage current and not the gate-induced drain leakage current. Above observation is dependent on device process flow, which provided us an easy way for DRAM device optimization and maximized manufacturing process window. Index Terms—Annealing, data retention, dynamic random access memory (DRAM) chips, passivation.

I. I NTRODUCTION

O

NE of the main concerns related to a dynamic random access memory (DRAM) is data retention degradation after packaging. Yin et al. reported that the hydrogen in passivation nitride could improve the refresh performance of a DRAM [1]. Chang et al. reported that the breaking of a Si–H bond and Manuscript received December 16, 2011; revised February 3, 2012; accepted February 15, 2012. Date of publication February 24, 2012; date of current version June 6, 2012. C.-Y. Lee is with Inotera Memories, Inc., Taoyuan 333, Taiwan, and also with the Department of Electronic Engineering, Chang Gung University, Taoyuan 333, Taiwan. C.-S. Lai and C.-M. Yang are with the Department of Electronic Engineering, Chang Gung University, Taoyuan 333, Taiwan (e-mail: [email protected]. edu.tw). D. H.-L. Wang is with the Technology Development Division, Inotera Memories, Inc., Taoyuan 333, Taiwan. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TDMR.2012.2188895

trap generation at the gate and drain overlap region are the root causes of data retention degradation of a DRAM after its packaging [2]. However, an improvement in data retention and a reduction in data retention degradation after the packaging process by changing the position of passivation annealing have not yet been reported. Further, it is difficult to control the cell transistor threshold voltage (CTVth) in a DRAM. It should be noted that the CTVth cannot be increased by simply increasing the dose of the threshold implant, which may cause an increase in the junction leakage. Thus, it is essential to introduce a negative word-line bias scheme to increase the cell transistor turn-on current (ION ) with a desired turn-off current (IOFF ) [3], [4]. Eriguchi et al. reported that an instability in the threshold voltage shift was induced by plasma charging damage [5], and Li et al. reported that the threshold voltage shift was induced by the damage due to a mechanical stress-enhanced plasma process [6]. However, only a few reports on the effect of the position of passivation annealing on the shift in the CTVth exist. It is interesting to note that irrespective of the plasmaassisted process used for CMOS fabrication. The gate oxide will get charged, the trapped charge will increase [7], and/or interface states will be formed [8], and/or the leakage current will increase [9], [10]. Hydrogen chemistry plays a key role in the reliability of CMOS technologies because molecular hydrogen passivates some of the electrically active defects at Si−SiO2 interface [11]. Therefore, to passivate the aforementioned defects, passivation annealing in hydrogen ambient atmosphere is usually carried out after CMOS fabrication. In this paper, we report, for the first time, that a change in the passivation anneal position significantly reduced the instability in the CTVth shift, improved data retention, and reduced data retention degradation of a trench DRAM after its packaging. To further investigate the data retention behavior of a DRAM chip, different substrate bias voltages (Vbb) and negative word-line low voltages (Vnwl) were applied to the DRAM chips. Hotcarrier stress was adopted to realize the device mechanism to reduce both the instability in the threshold voltage shift and data retention degradation of a DRAM chip after its packaging. DRAM development is extremely fast and three major challenges need to be resolved. There are CTVth control, signal margin and data retention. Signal margin usually happen when cell transistor low drive current is connected to high resistance.

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LEE et al.: DRAM DATA RETENTION AND CTVTH RELIABILITY IMPROVED BY ANNEALING

Fig. 1.

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Process flow map of the two key processes.

Data retention caused by low storage capacitance or leakage attributed to high electrical field. In the past, there are some researches to improve these three challenges. Lin et al. reported a novel trench capacitor enhancement approach [23]. Chen et al. reported DRAM technology using high-K MIM capacitor at 40-nm node and beyond [24]. Lin et al. also reported that Gate-Induced Drain Leakage (GIDL) improved by Millisecond Flash Anneal (MFLA) in DRAM [25]. Chang et al. reported the enhancement of data retention time for DRAMs using high-pressure deuterium annealing [26]. Schloesser et al. reported that a buried word-line DRAM cell for 40 nm and beyond for signal margin improvement [27]. In this paper, we report a easy way for DRAM device optimization to balance these three detractors for maximizing the manufacturing process window.

II. E XPERIMENTAL A 1-Gbit buried strap for a trench DRAM cell was fabricated with a ground rule of 70 nm using a boron-doped (100)-oriented 12 wafer. The key components of the trench DRAM cell included a deep trench capacitor with nitride dielectrics, a cell transistor with a triple-well structure, a shallow trench isolation and a buried strap junction formed by poly with adequately doping. For the passivation process, the wafer was deposited by ozone TEOS with 85 nm and plasma nitride with 480 nm during the power of 1200 watt. Then, the fabricated wafer was annealed at 400 ◦ C for 30 min in 100% hydrogen ambient atmosphere. To evaluate the influence of passivation annealing on DRAM cells, the experiments performed in this study involved passivation annealing before and after the deposition of the plasma nitride layer as shown in Fig. 1. A MOSAID tool is used to characterize the data retention of a 1-Gbit DRAM chip. Hot-carrier stress was applied on the cell transistor under two different conditions (on the deep trench (DT) capacitor side and the bit-line side) to determine the position of the interface trap and to understand the mechanism of data retention degradation.

Fig. 2. paths.

Cross-sectional view of the trench DRAM, indicating the leakage

III. R ESULTS AND D ISCUSSIONS A. DRAM Data Retention Improved by Junction Leakage Current Reduction It is very important to control the data retention time distribution of DRAM chips, given the fact that the refresh time of these memory chips doubles with each successive generation [12]. Data retention time is defined as the duration for which data is stored in the memory before it is read out. Further, as shown in Fig. 2, several types of leakage currents are observed in trench DRAM cells. These currents include 1) the gateinduced drain leakage (GIDL) current at the storage node, 2) the junction leakage current originating from the storage node, 3) the subthreshold leakage current of the cell transistor, 4) the leakage current in the deep subthreshold region of the cell transistor, 5) the vertical parasitic leakage current flowing between the storage node and the buried plate under collar oxide, 6) the isolation leakage current flowing between the neighboring cells from the buried strap (BS) to the cell bit line (CB) or from one BS to another BS below shallow trench isolation oxide, 7) the node dielectric leakage current, 8) the gate dielectric leakage current, and 9) the isolation leakage current flowing between the trench and passive word line (PWL) through trench top oxide. Fig. 3 shows that the data retention time improved by 18%; that is, the fail bit count (FBC) reduced by 15 counts, from 85 to 70; this result is obtained by analyzing 3 417 wafers. To investigate the mechanism for improving data retention, the dependence of the FBC on the substrate bias voltages (Vbb) and the negative word-line low voltages (Vnwl) was examined for a retention time of 256 ms measured by a MOSAID tool with checkboard test pattern. The FBC is around 10 counts under normal operation condition (Vbb = −0.4 volt and Vnwl = −0.9 volt). When Vnwl raised from −0.9 volt to −1.1 volt with fixed Vbb = −0.4 volt, FBC increased from 10 to 30 counts. Relatively, when Vbb slightly raised from −0.4 volt to −0.5 volt with fixed Vnwl = −0.9 volt, FBC significantly

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Fig. 3. Comparison and analysis of data retention fail bit counts for cases when passivation annealing is carried out before and after the deposition of the plasma nitride layers. Retention fail bit counts versus Vbb and Vnwl for duration of 256 ms under physical “1” condition. The result indicates that the data retention fail bit counts are primarily influenced by the junction leakage current and not by the GIDL current.

Fig. 5. Schematic of the proposed mechanism to explain different data retention behaviors attributed to the change in the passivation anneal position.

(SRH) mechanism. The SRH generation rate GSRH can be expressed as follows: GSRH

δn δp Vth Dt × np − n2i = E −E E −E δn × n+ni exp − tpKt i +δp × p+ni exp − ikT tp (1)

Fig. 4. Cross-sectional view of the crystalline defects between polydoped junctions of the storage trench and p-well of the cell transistor. The crystalline defects are the sources of the junction leakage current. The leakage mechanism of the Shockley–Read–Hall (SRH) thermal generation current is illustrated.

increased from 10 to 100 counts. The results of this examination indicated that the FBC was strongly dependent on the Vbb and not on the Vnwl. Although the GIDL junction leakage current dominated the cell leakage current for the previous 0.14 μm technology generation [4], the weak dependence of the FBC on Vnwl here means that the GIDL current is not a dominant part of the weak bit leakage current in the case of the 70-nm trench DRAM technology. Further, the junction leakage current is strongly attributed to the trench etching damage, shallow junction, and high channel doping concentration. We proposed that the crystalline defects are responsible for the generation of the junction leakage current between the polydoped junctions of the storage deep trench and p-well of the DRAM cell, as shown in Fig. 4. The junction leakage current [13]–[15] is mainly introduced by the Shockley–Read–Hall

where δn and δp are the electron and hole capture cross sections, respectively. Dt is the trap density, Vth is the carrier thermal velocity, ni is the intrinsic carrier density, Ei is the intrinsic Fermi level, and Etp is the trap energy level. Previous studies reported that the weak cell (tail distribution) of data retention time has a large junction current at a local area, which is mainly attributed to the proximity of the trap level to the Si midgap and the enhanced electric field in the depletion region. To improve the data retention time, it is necessary to control the energy-level distribution of the traps and reduce the electric field applied to the depletion region. B. Repair of Crystalline Defects by Carrying Out Passivation Annealing Before the Deposition of the Plasma Nitride Layer Fig. 5 shows the schematic of the proposed mechanism that explains the different data retention behaviors attributed to the change in the passivation anneal position. When passivation annealing is carried out after the deposition of the plasma nitride layer, the cap nitride layer acts as a diffusion barrier, limiting the lateral diffusion of hydrogen and causing insufficient passivation of the crystalline defects. In contrast, when passivation annealing is carried out before the deposition of the plasma nitride layer, sufficient amount of hydrogen is generated for repairing the defects, reducing the junction leakage current, and enhancing data retention. Chetlur et al. reported that the position of the final forming gas anneal is critical to the interface state passivation of the DRAM chips [16]. Chen et al. reported that the threshold voltage shift could be recovered by hydrogen annealing at 400 ◦ C–450 ◦ C [17]. Hamamoto et al. reported two methods for reducing the “tail distribution” in trench DRAM cells. One method involved a


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TABLE I C OMPARISON OF C ELL T RANSISTOR T HRESHOLD VOLTAGE S HIFTS BY C HANGING THE PASSIVATION A NNEAL P OSITION

reduction in the electric field of the storage node by lowering the pn junction doping concentration; the other method involved a reduction in the deep level defects for controlling the generation of point defects such as interstitial silicon atoms [18]. Weber et al. reported that an increase in the threshold voltage lead to an increase in the junction leakage current because of an increase in the implant damage and the fact that high electric fields were applied at the buried junction in the trench DRAM cells [19]. Okonogi et al. reported that triangular intrinsic stacking faults in the depletion layer increased the junction leakage current [20]. Kim et al. reported that an increase in the hydrogen annealing temperature caused the hydrogen electrical defects to become inactive, which in turn reduced the thermal degradation of the DRAM retention capacity [21]. We believe that the crystalline point defects are responsible for the generation of the junction leakage current when a high electrical field is applied at the DT buried strap junction in trench DRAM cells.

Fig. 6. Comparison of CTVth uniformity within the wafer for cases when passivation annealing was carried out before and after the deposition of the plasma nitride layer.

C. Increase in Threshold Voltage by Carrying Out Passivation Annealing Before the Deposition of the Plasma Nitride Layer Table I lists the values of CTVth carrying out Passivation Annealing before the Deposition of the Plasma Nitride Layer measured between the first level metal (metal 0) test and the passivation test performed before and after the deposition of the plasma nitride layer. From this table, it was found that when the plasma nitride layer was deposited after passivation annealing, the value of CTVth obtained from the passivation test was lower than that obtained from the metal 0 test by 45 mV; when the plasma nitride layer was deposited prior to passivation annealing, the value of CTVth obtained from the passivation test was higher than that obtained from the metal 0 test by 8 mV. This result indicates that the shift in CTVth significantly differed with respect to the passivation annealing position change. Furthermore, the poor uniformity of CTVth within the wafer significantly improved from the center to the edge of the wafer. Fig. 6 shows the result of the analysis of the volume of the wafer; this result indicates that the uniformity of CTVth was found to significantly improve from 100 mV to 38 mV within the wafer. This improvement in the uniformity of CTVth provided the DRAM cells with a larger margin for further reducing both the threshold voltage and the dose of threshold implant. The electrical field can be further reduced and increased via the ION while maintaining a desired IOFF . To the best of our knowledge, a plasma nitride layer deposited by plasma-enhanced chemical vapor deposition

Fig. 7. Comparison between the yield losses induced by data retention degradation after packaging between passivation anneal post nitride and prior nitride process.

(PECVD) exerts a plasma antenna effect. We believe that the plasma charge breaks some of the weak Si–H bonds in the gate oxide interface during the deposition of the plasma nitride layer and increases CTVth. D. Presence of Strong Si–H Bonds When Passivation Annealing Is Carried Out Before the Deposition of the Plasma Nitride Layer The packaging process of DRAM chips involves the following steps. First, the DRAM chips are treated by a burn-in process; second, the chips are subjected to infrared radiation at around 250 ◦ C, which enables the mounting of the DRAM chips via Sn soldering. This process causes data retention degradation, which in turn caused a yield loss in DRAM chips. Fig. 7 shows that the yield loss induced by data retention degradation improved by 1.16% when passivation annealing was carried out before the deposition of the plasma nitride layer; this result was obtained by analyzing 832 DRAM chips. From the above result, it is found that not only does a simple hydrogen passivation mechanism for the dangling bonds in the gate oxide interface exists but more complicated mechanisms also exist depending on the change in the position of the passivation annealing.

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TABLE II C OMPARISON OF I NITIAL C ELL T RANSISTOR D EVICE PARAMETERS B EFORE THE A PPLICATION OF H OT-C ARRIER S TRESS BY C HANGING THE PASSIVATION A NNEAL P OSITION

Fig. 9. Comparison between the results obtained when hot-carrier stress was applied under the two aforementioned conditions for cases when passivation annealing was carried out before and after the deposition of the plasma nitride layer. This figure shows that the effect of passivation annealing carried out after the deposition of the plasma nitride layer was more intense at the DT than at the bit line.

Fig. 8. Two conditions under which hot-carrier stress was applied by changing the passivation anneal position. In one case, the hot-carrier stress was applied at DT for interface trap at bit-line dominated; in the other case, the hot-carrier stress was applied at bit line for interface trap at DT dominated.

To investigate the reason for the improvement of the yield loss induced by data retention degradation after packaging, hot-carrier stress is applied to characterize the cell transistors. Table II lists the initial cell transistor parameters before the application of hot-carrier stress; the wafers for different passivation anneal positions have been tested with the same impact ionization rate. The ratio of the maximum substrate current (Isub) to the drain current (Ids) is the same before the application of the hot-carrier stress, such that the lateral electric field at the drain is constant. Fig. 8 shows two conditions under which hot-carrier stress was applied by changing the passivation annealing position. In one case, the hot-carrier stress was applied at DT for interface trap at bit-line dominated; in the other case, the hot-carrier stress was applied at bit line for interface trap at DT dominated. Fig. 9 shows that the effect of passivation annealing carried out after the deposition of the plasma nitride layer was more intense at the DT than at the bit line. The aforementioned results proved that the CTVth increased when passivation annealing was carried out before the deposition of the plasma nitride layer, and data retention

degradation reduced after packaging owing to the breaking of the weak Si–H bonds. It should be noted that the FBC is mainly influenced by the junction leakage current and not the GIDL leakage current; this explains why the retention performance of DRAM cells does not degrade when the interface states are increased. The cell leakage currents should be carefully controlled in order to meet the desired requirement of data retention time for the reliable operation of gigabit density DRAMs [22]. The required cell leakage current is calculated as a function of the storage capacitance using various operation voltages for specified data retention times, calculated by the following equation: ILEAK =

CS ×

1

2 VCC

− ΔVBL − CB × ΔVBL TREF

(2)

where TREF , VCC , ΔVBL , CS , and CB are the data retention time, operating voltage, bit-line sensing voltage, storage capacitance, and parasitic bit-line capacitance, respectively. It should be noted that the data retention time can be increased by increasing the storage capacitance; however, an increase in the storage capacitance is likely to cause issues related to the device reliability due to the thinner capacitor dielectric. Further, the channel doping concentration increases with a decrease in the channel length of the cell transistor in order to suppress the short-channel effect (SCE) and to minimize the subthreshold leakage current. Therefore, the junction leakage current is considered to be one of the most dominant currents among the other leakage currents that exist in the cell transistor. In addition, it is important to reduce both the number of point defects generated in the depletion region and the electric field in this region. However, it is very difficult to reduce the channel doping concentration without degrading the subthreshold characteristics of the cell transistor.


From the results of carrying out passivation annealing prior to the deposition of the plasma nitride layer, it is found that the CTVth shift reduces and its uniformity within the wafer improves; this improvement provides cell transistor with a larger margin for further reducing both the threshold voltage and the dose of the threshold implant. The electrical field can be either further reduced or increased via ION , while maintaining a desired IOFF ; appropriate control of the electrical field led to an improvement in the bit-line coupling and data retention. IV. C ONCLUSION The position of the passivation anneal used in the fabrication of DRAM chips is found to be critical to the CTVth shift, data retention, and data retention degradation after the packaging of these chips. When passivation annealing is carried out prior to the deposition of the plasma nitride layer, sufficient hydrogen is generated, which repairs the crystalline defects, which in turn reduces the junction leakage current and improves data retention. The deposition of a passivation nitride layer plays a key role in the breaking of weak Si–H bonds. Consequently, it not only increases CTVth but also significantly improves the CTVth uniformity within the wafer. Superior CTVth uniformity enables the threshold voltage to be reduced further as well as cell transistor ION increased while maintaining a desired IOFF . Data retention can also be improved by reducing the electrical field and junction leakage current. Furthermore, when hot-carrier stress was applied to DRAM cells, demonstrated the less degradation due to strong Si–H bonds is remained or incomplete interface passivation before the hot-carrier stress for passivation anneals prior nitride. We verified that the interface states are generated near the trench side than near the bitline side maybe because of the plasma damage caused by the trench etching process. The results indicate that the FBC is primarily influenced by the junction leakage current; we believe that the crystalline defects play a key role in inducing junction leakage currents and that the influence of interface states on the GIDL current is not significant. By changing the position of the passivation anneal in the fabrication process flow, we find that the CTVth shift is reduced and data retention and data retention degradation after packaging are improved. For further reducing the electrical field, the threshold implant is adjusted at the deep trench side, and hence, DRAM data retention is further improved and becomes more robust to the backend packaging process.

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ACKNOWLEDGMENT

[20]

The authors would like to thank B. Wu of Nanya Technology Corporation for assisting in the collection of device measurement data and for the extremely valuable discussions on the device mechanisms.

[21] [22]

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Chung-Yuan Lee received the B.S. degree in electrophysics from National Chiao Tung University, Hsinchu, Taiwan, in 1987 and the M.S. degree in electrical engineering from National Cheng Kung University, Tainan, Taiwan, in 1989. He is currently working toward the Ph.D. degree in the Department of Electronic Engineering, Chang Gung University, Taoyuan, Taiwan. During 1989–1996, he has been employed by United Microelectronics Corporation, Hsinchu, where he was engaged in device development, device modeling and reliability, SRAM integration, and electrostatic discharge/latchup improvement. In 1996, he joined Nanya Technology Corporation, Taoyuan, where was coordinated of DRAM technology development for 0.28 and 0.2 μm. In 2000, he was assigned to coordinate for the Nanya/IBM joint development for 0.14- and 0.11-μm DRAM technology at IBM Advanced Silicon Technology Center, New York. In 2002, he was promoted to Director of the Process Development Division. Responsibilities have included Nanya/Infineon joint development for 70-nm, 58-μm, and emerging technology development. Since 2007, he has been employed by Inotera Memories, Inc., Taoyuan, as Special Assistant for President responsible for coordinating of invention disclosure, knowledge management, I.D.E.A. review board, and some tasks of advanced module technology. He holds 36 U.S. patents and 59 Taiwan patents, and he is the author of 12 international published papers and conference.

Chao-Sung Lai (SM’11) received the B.S. and Ph.D. degrees from National Chiao Tung University, Hsinchu, Taiwan, in 1991 and 1996, respectively. In 1996, he joined National Nano Device Laboratories, Hsinchu, where was engaged in the research of silicon-on-insulator devices. He then joined Chang Gung University, Taoyuan, Taiwan, as an Assistant Professor. He was promoted to Full Professor in 2006 where he has been engaged in the research of the characterization and reliability of MOSFETs, Flash memory, high-k dielectrics, metal gates, and biosensors. In 2001, he visited the Department of Electrical Engineering, University of California, Berkeley, for sabbatical research on fin-shaped FETs. Since 2007, he has been the Chairman of the Department of Electronic Engineering and the Director of the Biosensor Group of the Biomedical Research Center, Chang Gung University, for the research-related biotransistor application on ions, proteins, DNA, and biomarker analysis. He holds 5 U.S. patents and 13 Taiwan patents, and he is the author of more than 100 SCI journal papers, 150 conference papers, 6 international invited talks, 6 IEEE IEDM papers, and 2 book chapters. Dr. Lai is the Guest Editor of the SCI journals, including Microelectronics Reliability (2010), Nano-Scaled Research Letters (2011), and Solid-State Electronics (2012). He is the Director of Electronics Device and Material Association, Taiwan. He was the recipient of the Lam Award in 1997.

Chia-Ming Yang was born in Kaohsiung, Taiwan, on November 27, 1976. He received the B.S. degree in electrical engineering from Chang Gung University, Taoyuan, Taiwan, in 1999, the M.S. degree in electronic engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2001, and the Ph.D. degree in electronic engineering from Chang Gung University, in 2006. He is currently an Assistant Professor in the Department of Electronic Engineering, Chang Gung University, after working for 5 years in Inotera Technology, Inc. for DRAM device and retention optimization as a Department Manager. His research interests include DRAM retention and VRT, VLSI, and MEMS technology; biomedical and chemical sensors; and nanotechnology.

David H.-L. Wang received the M.S. and Ph.D. degrees from National Cheng Kung University, Tainan, Taiwan, in 1993 and 1998, respectively. In 1998, he joined the DRAM maker ProMOS Technologies, Hsinchu, Taiwan, where he was in charge of trench DRAM process integration and prime wafer coordination. In 2001, he joined Kao Yuan University, Kaohsiung, Taiwan, as an Assistant Professor of the Department of Electronic Engineering. In 2003, he returned to DRAM industry and joined Inotera Memories, Inc., Taoyuan, Taiwan, as a Process Integration Manager. He holds 6 Germany patents, 6 U.S. patents, and 2 Taiwan patents, and he is the author of more than 10 SCI journal papers.