for comprehensive simulation, and timing simulators can use DSPF for delay
analysis. DSPF also lists circuit-level debugging information so you can identify ...
Hierarchical PRE
DSPF Format
Extracting Parasitic Resistance (PRE)
The DSPF format contains complete extracted circuit information, including designed and parasitic devices. Circuit simulators can use DSPF for comprehensive simulation, and timing simulators can use DSPF for delay analysis. DSPF also lists circuit-level debugging information so you can identify parasitic layout components and study their effects. DSPF has two sections: a net section and an instance section. The net section consists of a series of net description blocks. Each net description block corresponds to a net in the physical design. A net description block begins with a net statement followed by pins, instance pins, subnodes, and parasitic resistor/capacitor (R/C) components that characterize the electrical behavior of the net. The instance section consists of a series of SPICE instance statements. SPICE instance statements begin with an X. The DSPF format is as generic and as much like SPICE as possible. While native SPICE statements describe the R/C sections, some nonnative SPICE statements complete the net descriptions. These nonnative SPICE statements start with the notation “*|” to differentiate them from native SPICE statements. Each file consists of hierarchical cells and interconnects only. When the data also contains designed devices, the DSPF excludes these extracted devices (MOSFETs, bipolar transistors, and so on). These devices are not reported in DSPF.
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DSPF Sample
The following sample circuit is shown in DSPF format.
B INV1 DF1
IN
C
OUT
A
IN
OUT
IN:2
R23 B
C3
R22
C5
C
IN
A
IN R20
R21
C2
C4
C6
C9
OUT R25
IN:1
C1
DF1
OUT:1
INV1
R24
C7
R26
C8 OUT C10
In this example, nonnative SPICE statements start with the notation “*|” to differentiate them from native SPICE statements. .SUBCKT BUFFER OUT IN * * Net Section * *|GROUND_NET VSS * *|NET IN 1.221451PF *|P (IN I 0.0 0 10) *|I (DF1:A DF1 A I 0.0 10.0 10.0) *|I (DF1:B DF1 B I 0.0 10.0 20.0) *|S (IN:1 5.0 10.0) *|S (IN:2 5.0 20.0) C1 IN VSS 1.17763E-01PF C2 IN:1 VSS 2.76325E-01PF C3 IN:2 VSS 2.86325E-01PF C4 DF1:A VSS 2.70519E-01PF C5 DF1:B VSS 2.70519E-01PF R20 IN IN:1 1.70333E00 R21 IN:1 DF1:A 1.29167E-01 R22 IN:1 IN:2 1.29167E-01 R23 IN:2 DF1:B 1.70333E00 * *|NET BF 2.87069E-01PF *|I (DF1:C DF1 C O 0.0 10.0 10.0)
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*|I (INV1:IN INV1 IN I 0.0 30.0 20.0) C6 DF1:C VSS 2.08719E-01PF C7 INV1:IN VSS 7.83500E-02PF R24 DF1:C INV1:IN 1.80833E-01 * *|NET OUT 1.48478E-01PF *|S (OUT:1 45.0 10.0) *|P (OUT O 0.0 50.0 5.0) *|I (INV1:OUT INV1 OUT O 0.0 40.0 20.0) C8 INV1:OUT VSS 1.47069E-01PF C9 OUT:1 VSS 6.32813E-03PF C10 OUT VSS 7.76250E-03PF R25 INV1:OUT OUT:1 3.11000E00 R26 OUT:1 OUT 3.03333E00 * * Instance Section * XDF1 DF1:A DF1:B DF1:C DFF XINV1 INV1:IN INV1:OUT INV .ENDS
Note: This example does not contain coupling capacitors. Coupling capacitors would normally be listed at the end of the net description block that includes the first node name of the capacitor. Non-native SPICE syntax and conventions are described below. NET netName netCap NET indicates the beginning of a new net description. netName assigns each net statement a unique net name. netCap specifies the total capacitance associated with the net. netCap includes capacitances to ground and capacitances to nearby wires. It includes a numerical value (which can sometimes be zero) and a unit name, usually PF, with no space between. Because the NET statement includes the total capacitance, you can examine the NET statement to extract the sim.cap format from the DSPF format. Pins, instance pins, subnodes, and all the R/C descriptions that characterize the net follow the NET statement. P {(pinName pinType pinCap [xCoord yCoord])} Note: You must specify all pin capacitance values in the timing view library for computation. P denotes pins in the net. Each pin description is delimited by parentheses and contains the information for its name (pinName), its type (pinType), its generalized capacitance value (pinCap), and its
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x coordinate location (xCoord) and its y coordinate location (yCoord). Multiple pin descriptions can be listed on one line. pinType can be P (power), G (ground), C (clock), I (input), O (output), B (bidirectional), and X (unspecified). pinCap consists of a capacitance value followed by any number of optional R/C pairs. For example C0 [R1 C1 R2 C2 ...].
This format lets you model the pin characteristics by a higher order equivalent R/C ladder circuit than is represented by a single capacitor. The order of the equivalent circuit is increased from the first order (represented by C0) by attaching R/C pairs. The value of each capacitance is determined by a numerical value and a unit specifier such as PF. Use the generalized pin capacitance only if the pin type is I, O, or B. With other pin types, pinCap is dropped. In this case, you should use a number (for example, 0) as a place holder. xCoord and yCoord describe a pin location (optional). Generalized Pin Description Rn
R1
C0
C1
Cn
I {(instPinName instName pinName pinType pinCap [xCoord yCoord]..)} I describes instance pins in the net. Each instance pin description is delimited by parentheses. The pinName, pinType, pinCap, and xCoord and yCoord follow the same format as described in the P statement. The description of the instance pin location is optional. Multiple instance pin descriptions can be listed on one line. The xCoord and yCoord can be repeated for feedthrough pins. instPinName is the instance pin name component obtained by concatenating the instName and the pinName with a delimiting character specified by the DELIMITER statement. instName is the instance name component. pinName is the name of the pin in the master of the instance.
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S {(subnodeName [xCoord yCoord])} S denotes subnodes in the net. Each subnode description is delimited by parentheses and contains the name of the subnode and its location. A subnode name is obtained by concatenating the net name and a subnode number by a colon (netname:1). Multiple subnode descriptions can be listed in one line. GROUND_NET netName GROUND_NET specifies the ground net for loading capacitors. It must precede the NET statement. netName is the name of the ground net. DELIMITER “C” This statement specifies the character C as the delimiter used to construct the instance pin name instPinName. If you do not include this statement, the default delimiter character, colon (:), is used. For native SPICE statements, a continuation line begins with a plus sign (+) in the first column. For other statements, a continuation line begins with an asterisk and a plus sign (*+) in the first and second columns. The maximum number of continuation lines allowed is 1000. Note: You might see instances of resistors and capacitors starting with the instance names RD and CD, respectively. These are dummy instances created for the CDC, which requires a pie model (capacitor-resistorcapacitor) for the RC mesh. If there are cases that do not fit the pie model, dummy resistors or capacitors with a value of zero are added where needed.
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