DTM: Dynamic Transfer Mode Based on Dynamically ... - CiteSeerX

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PAPER

DTM: Dynamic Transfer Mode Based on Dynamically Assigned Short-Hold Time-Slot Relay Naoaki YAMANAKA† and Kohei SHIOMOTO† , Members

SUMMARY This paper proposes a new high-speed network architecture called Dynamic Transfer Mode, DTM. At the entrance of the DTM network, destination addresses such as IP addresses are converted into DTM routing information and attached to the packet header. In a DTM network, a connection is set up on-the-fly by sending a series of routing link identifiers to the destination, so burst data transfers like WWW traffic are efficiently carried. A connection between adjacent nodes is created and released dynamically within the burst transfer period. This yields higher statistical multiplexing gain and improved bandwidth efficiency compared to with conventional STM. Time division multiplexing is utilized so delay jitter or cell loss, the major drawbacks of Asynchronous Transfer Mode, are avoided. This paper analyzes the performance of a DTM network and describes an implemented switching system. Because a DTM network uses source-routing and passive STM switching, it simplifies the core transit switch while localizing intelligence to edge nodes. A simplified core transit switch is well suited for future high-speed backbone networks. key words:

network, burst, STM, traÆc, switch

1.

Introduction

Since the invention of the Worldwide Web (WWW), the Internet has become very popular and Internet traffic has been growing at an exponential rate [1]. The capacity of the future wide-area backbone network must be large enough to handle such traffic. To best realize transmission capacity expansion, the transmission mechanism of the backbone network should be simple. This can be achieved by localizing routing intelligence to the edges of the backbone network. Several high-speed networking technologies have been proposed to date such as burst switching [2], [3], fast circuit switching [4], and Asynchronous Transfer Mode (ATM) [5]. These technologies do not, however, suit WWW traffic because they are connectionoriented. Even though each session transfer a fairly large amount of data, it is still too short to carry efficiently using a connection-oriented protocol because it is wasteful to setup a connection between source and destination before sending data. In addition, because a circuit switch allocates static bandwidth to each connection, bandwidth efficiency degrades if we carry bursty traffic using circuit switches. Even though ATM carries bursty traffic efficiently, cell transfer delay jitManuscript received May 19, 1998. Manuscript revised August 12, 1998. † The authors are with NTT Network Service Systems Laboratories, Musashino-shi, 180-8585 Japan.

ter and cell loss may occur unless appropriate traffic control is performed necessitating higher layer retransmission. In this paper we propose a new communication network mode called Dynamic Transfer Mode (DTM). This is based on using source-routing and on-the-fly connection setup. In other words, source routing converts an IP address to link information using time-slot relay to the destination port. The time-slot relay information is set at the top of the burst frame. A connection between adjacent nodes is created and released dynamically using time division switching. That means simple time-slot exchange is used for internode connection. At the link, simple synchronous time division data transfer is used without any overhead. Table 1 compares DTM to conventional transport techniques such as circuit switching, packet switching (Datagram), and ATM. First, the space overhead is low for DTM and for circuit switches, because they use time division switching; switching is performed by exchanging time-slots between input and output links, so no packet header is needed. In contrast, the space overhead for ATM amounts to about 10% (=100 × 5/53) even if a continuous stream is transported. Second, the efficiency for burst traffic is high for DTM, packet switches, and ATM. In a DTM network, connections are created and released dynamically on a burst-byburst basis. A connection is established only when a packet is sent. In contrast, in a circuit switch network, a connection is held whether a packet is present or not, so the bandwidth efficiency is low for bursty traffic. Third, DTM and circuit switches provide good quality of service because they are based on time division multiplexing. In contrast, ATM and packet switches are based on statistical multiplexing, so we cannot avoid cell/packet loss and transfer delay jitter. Fourth, DTM and packet switches are suited for short-lived transfer of fairly large data groups like WWW traffic because they do not require a pre-established connection. In a DTM network, a connection is created on-the-fly. Figure 1 shows the concept of DTM. A DTM network consists of edge and transit nodes. Each edge node knows the network topology. When a source edge node receives a packet, it determines the address of the destination edge node. Once it has done that it makes a relay of link identifiers to the address (we call it the time-slot-relay). The time-slot-relay is attached to the

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Table 1

Comparison of DTM with conventional methods.

Fig. 1

Concept of DTM.

packet, which is then injected into the DTM transit network. Connections are set up while the time-slot-relay is enroute to the destination. User data immediately follows the time-slots-relay. Each node is a passive STM switch, and translates the link identifier in the time-slot-relay, determines the appropriate output time-slots, and configures a connection by setting the association between input and output time-slots into address control memory (ACM). Thus the onward connection is configured at the transit node. If the proper output time-slot can not be assigned, the information is held in a buffer pool until a vacant output time-slot is available. This procedure takes place at every transit node between the source and destination edge nodes. Let us compare the conventional connection less, ATM and DTM protocols. Figure 2 illustrate data transfer with these protocols. The connection less protocol demands that the routing function be realized at each node as software. In addition, resources are not reserved, i.e. best effort basis. ATM is connection oriented, so call-setup is performed before information is transferred. User must wait until call-setup acknowledgment is achieved before sending the data. DTM is

Fig. 2

Comparisons of CL, ATM and DTM.

based on source routing and connections are not setup before information transfer. Resource (time-slots) are dynamically assigned on-the-fly during the information transfer period. If the resource can not be secured, the data is held in a buffer pool. Because buffer pool overflow causes bust loss, the pool is designed to minimize

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Fig. 3

DTM switching node.

overflow probability. Using source-routing and passive STM switching in the DTM network simplifies the core transit switch and localizes intelligence to the edge nodes. A simplified core transit switch is well suited for future high-speed backbone networks. 2.

Details of DTM Switches

2.1 Principle The mechanism for configuring a connection by setting the association between input and output time-slots is explained in detail below. Figure 3 shows the N × N switch fabric of a DTM transit node. This switch fabric is a passive STM switch. Each link is time-multiplexed and each connection is multiplexed into an input link in STM fashion. All input links are multiplexed again into a single core-highway in STM fashion. All time slot data are stored into data buffer memory, DBM. Time slots within a frame over the highway are exchanged by the read order which is controlled by address control memory, ACM. The single core-highway is demultiplexed into output links. Exchanging timeslots switches a circuit. In more detail, information in each time-slot is copied to the DBM to an address associated with the time-slot. The ACM decides the address of the DBM, from which data is read out. The ACM is composed of a set of registers, each of which indicates the address of the DBM memory associated with the time-slot of the output. Setting a into the i-th register of the ACM exchanges the a-th time-slot of the input with the i-th time-slot of the output. In conventional STM networks, the contents of ACM are configured via an out-of-band setup signal-

ing message. This takes several seconds, because of the complicated software control to set up at each node. In contrast, in DTM networks, the ACM contents are configured via an in-band message, i.e., the time-slotrelay. The time-slot corresponding to the node (say the a-th time slot) in the time-slot-relay is extracted. This time-slot indicates the destination output link identifier of the switch. The header controller determines the ACM value from the link identifier set at the top of the burst data. The switch finds idle time-slots associated with the output link and then sets a into the ACM registers associated with the slots. The packet delineation mechanism and packet format are detailed below. The packet format used in DTM networks is shown in Fig. 4. Because the timeslot-relay is transferred in an in-band fashion in DTM networks, a packet delineation mechanism is needed. For this purpose, a preamble pattern is attached to the front of a packet. The time-slot-relay field follows the preamble pattern. If a preamble pattern is detected at a node, the time-slot-relay field is extracted. There are several way to identify the end of IP packet. For the proposed DTM, we use ‘LEN’ field to show the packet length. In other words, DTM node keep it’s connection for the packet size identified by the ‘LEN’ field. The length of the time-slot-relay field is variable, so its last time-slot is marked by all ‘1’s. Each DTM node uses a different timeslot; for example, the 1st node uses #a, second node uses #b . . . etc. Used timeslot are marked by “1” at the LSB bit. The mechanism of the buffer-pool is detailed below. When sufficient time-slots are unavailable at the destination output link, the connection request is blocked and diverted to a common buffer pool as shown in Fig. 3. This buffer pool is connected to the passive STM switch via input and output links. The diverted

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Fig. 4

Fig. 5

Mechanism of idle-time-slot manager.

connection is queued in a packet-by-packet fashion. If the buffer pool is full, the new arriving packet is discarded. For the waiting packet, the connection setup request is retried after a random back-off timer expires. The retry request is treated in the same way as other newly arriving requests. The advantage of this retry mechanism is that it isolates the buffer-pool management from the time-slot manager. We might maximize time-slot utilization by allocating idle time-slots immediately after they are freed. To do this, we would have to implement a communication mechanism between the buffer-pool and the time-slots manager. 2.2 Idle-Time-Slot Manager Several alternative time slots exist on the time division multiplexed transmission link, for example #0, #8, #16 . . . , that are transmitted to the same next node. The on-the-fly packet header identifies one of the next node time slot, for example, only #0, that is called the output link ID. The OFHC hosts the idle-time slot manager as shown in Fig. 5. The mechanism for translating link identifiers into time slots is detailed below. This translation is handled by the idle-time-slot manager, whose block diagram shown in Fig. 5. Idle-time-slot identifiers of the output link are maintained in a chain. Once

Packet format.

an output link has been determined, time-slot identifiers are selected from the chain associated with it. Those time-slots are assigned to a new connection. The conventional method needs to locate idle time-slots by using output link ID. Then requires Nm table searching. On the other hand, the proposed chain-based approach just looks at output link ID pointer, that is N table searching. The ratio of Nm /N is approximately 2000 for 64 kb/s connection on the 150 Mb/s link. This chain-based management achieves quicker response than the table-based method which stores the states of all time-slots (busy or idle). As mentioned above, ACM is composed of registers associated with the time-slots of the TSI output. In addition, each register has an information field that identifies which output link the time-slot belongs to. When the connection is released, the time-slots allocated to the connection are freed and their identifiers are attached to the end of the chain. Note that each time-slot is used only during packet transfer. In other words it is used dynamically and held only for a short time. 2.3 Multiple Time-Slot Rate Multimedia, multi-rate connections can be transferred using the multiple time-slot technique. The mechanism for implementing a connection requiring multiple timeslots is explained below. In DTM networks, a variable transmission rate is implemented by using multiple time-slots within a frame. The time-slot-relay should permit all time-slots associated with a connection to be assigned to the same output link. To associate multiple time-slots to one connection, a connection identifier sub-field is introduced in the time-slot field of the time-slot-relay. If only part of the multiple time-slot can be assigned, the buffer pool is used as shown in Fig. 6. The connection identifier sub-field only has to be unique within an input link and an output link. The multi-slot DTM frame format is shown in Fig. 7. In the example, 3 time-slots are used for communication. The top of the slot carries master information that points to the following multi-slots. All multiple time slot connections have the same connection identifiers. We may change its value hop-by-hop to ensure that it is unique

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Fig. 6

Issue in multiple time-slot connection. Fig. 8 Total size requirement for DTM node (256 × 256 switch).

Fig. 7

Multiple time-slot packet format.

within a link like a VCI. Using this method, link capacity can be used as much as possible. 3.

Performance Evaluation

When sufficient time-slots are not available at connection setup, the burst data connection is diverted to the buffer-pool. In this section, we evaluate the performance of DTM. First, the required size of the buffer pool is evaluated as shown in Fig. 8 under the condition of load equal to 0.6. According to the results, buffer size equal to 128 burst, is enough buffers to guarantee the small packet last probability (connection block) of 10−6 for an 8 time-slot link system. DTM offers the advantage of quick connection setup comparing with conventional ATM-SVC. Figure 9 shows the connection setup delay of conventional ATMSVC and DTM. ATM-SVC needs link-by-link connection addmission control. However, as described before, DTM is an on-the-fly setup mechanism, and so only the first node performs source routing setup without any transmission link resource reservation. For this evaluation, mean call arrival time is set to 1.0 sec and setup time of ATM SVC and DTM is 0.5 and 0.2 sec, respectively. Note that, DTM is based on source routing so its performance is independent of the number of transit nodes. According to our calculations, ATM incurs large connection setup delays when the network becomes large. DTM packet transfer delay will be discussed later. In a DTM switch, each input link is monitored. When a preamble pattern is detected, the procedure for a new connection setup is initiated. The output link designated by the time-slot-relay is checked to see

Fig. 9 Call setup delay comparisons between ATM and DTM.

if it has sufficient idle time-slots. If it does, the connection is setup. Otherwise, the connection is diverted to the buffer-pool, where it is delayed. When sufficient time-slots become available, the diverted connection is served. Connections in the buffer-pool are served in a best-effort fashion, so when a new connection arrives at the output link, a diverted connection may not be served. Even though the network should be engineered so that the diversion probability is small, we need to determine how much the diversion affects the packet transfer delay. Next, we evaluated the relationship between load and end-to-end delay. We assumed that a homogeneous connection transmission rate is used and that the input link speed is an integer multiple C of the connection transmission rate. We also assumed that connection setup requests arrive according to a Poisson distribution and that the holding times are exponentially distributed. We calculated end-to-end packet transmission delay time for a network composed of 6 and 10 tandem nodes. Figure 10 shows the relationship between offered load and end-to-end mean packet transmission delay time. In figure, the vertical axis is normalized by average burst holding time. For comparison, end-to-end mean packet delay time with Fast Reservation Protocol/Delayed Trans-

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mission (FRP/DT) in an ATM network [8] is also plotted in Fig. 10. We used the analysis of FRP/DT in Ref. [9]. As the number of hops increases, maximum throughput of FRP/DT decreases. This is explained as follows. A packet is not allowed to be sent until all links toward the destination node are reserved in FRP/DT. The more nodes a packet traverses, the more it is likely to encounter link block. In contrast, a packet is trans-

(a)

mitted through a DTM network until it encounters a link block. Thus DTM outperforms the FRP/DT protocol in ATM networks. 4.

Experiment

An experimental DTM network was constructed, as shown in Fig. 11, by connecting a server host and three client hosts. The packet generator created IP packets. The time slot relay transported IP packets using the DTM mechanism. As a first step, we confirmed the feasibility of the DTM network. Performance measurements are being conducted using the experimental network. A detail block diagram of the trial DTM switching node is shown in Fig. 12. The multiplexer, TSI, demultiplexer, and buffer-pool were each implemented using a single FPGA. Figure 13 shows a photograph of our implemented DTM switching node and switching board. The buffer-pool collects and reports statistics on the total number of packets and the number of lost packets. Limited by the standard FPGA (Field Programmable Gate Array) devices used in this prototype system, it can handle a 10 Mb/s DTM signal. DTM

(b) Fig. 10 Offered load vs. end-to-end mean system time. (a) Link capacity C=4, (b) Link capacity C=16.

Fig. 12

Fig. 11

Experimental DTM network.

Block diagram of implemented DTM switching node.

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(a)

(b) Fig. 13 Photograph of implemented DTM switching node. (a) DTM node, (b) Switch board.

may offer line speeds of more than 2.4 Gb/s line and throughputs of about 100 Gb/s, because the conventional highest time division switch module has Gb/s throughput [10] and considering the-state-of-the-art CMOS technology [11]. 5.

Closing Remarks

Our goal is to make a high-speed backbone network architecture. DTM is a new communication method based on using source-routing and on-the-fly connection setup. Using source-routing avoids complicated routing processes at the transit nodes which results in a simple high-speed backbone switch. Because DTM makes use of circuit-switching technology, there is no delay jitter, so traffic management is simplified. Thus DTM is well-suited for future high-speed backbone networks. A future study will consider the non-ideal resource allocation and scalability that can be created by source routing. More detail studies on implimentations are required and the performance of multiple slot DTM must be examined in more detail. We are now experimentally evaluating DTM network performance and will report the results in detail in the near future. References [1] “http://www.mit.edu/people/mkgray/net” [2] S.R. Amstuts, “Burst switching—An introduction,” IEEE Commun. Mag., Nov. 1983. [3] S.R. Amstuts, “Burst switching—An update,” IEEE Commun. Mag., Nov. 1989. [4] C. Bohm, M. Hidell, P. Lindgren, L. Ramfelt, and P. Sj¨ odin, “Fast circuit switching for the next generation of high performance networks,” IEEE J. Select. Areas Commun., vol.14, no.2, pp.298–305, Feb. 1996.

[5] J.P. Coudreuse and M. Servel, “Prelude: An asynchronous time-division switched network,” Proc. IEEE ICC ’87, Seattle, June 1987. [6] T.H. Cormen, C.E. Leiserson, and R.L. Rivest, “Introduction to Algorithms,” McGraw-Hill, 1990. [7] E. Gelenbe and I. Mitrani, “Analysis and Synthesis of Computer Systems,” Academic Press, 1980. [8] D.P. Tranchier, P.E. Boyer, Y.M. Rouaud, and J.Y. Mazeas, “Fast bandwidth allocation in ATM networks,” Proc. ISS’92, pp.7–11, 1992. [9] H. Suzuki and F.A. Tobagi, “Fast bandwidth reservation scheme with multi-link & multi-path routing in ATM networks,” Proc. IEEE INFOCOM’92, pp.10A.2.1–10A.2.8, 1992. [10] S. Kikuchi and N. Yamanaka, “An expandable time-division circuit switching LSI and network architecture for broadband ISDN,” IEEE J. Select. Area Commun., vol.14, no.2, pp.328–336, 1996. [11] Y. Ohtomo, S. Yasuda, M. Nogawa, J. Inoue, K. Yamakoshi, H. Sawada, M. Ino, S. Hiro, Y. Sato, Y. Takei, T. Watanabe, and K. Takeya, “A 40 Gb/s 8 × 8 ATM switch LSI using 0.25 µm CMOS/SI max,” Proc. IEEE SSSCC, pp.154– 155, 1997.

Naoaki Yamanaka was born in Sendai-city, Miyagi prefecture, Japan, on July 22, 1958. He graduated from Keio University, Japan where he received B.E., M.E. and Ph.D. degrees in engineering in 1981, 1983 and 1991, respectively. In 1983 he joined Nippon Telegraph and Telephone Corporation’s (NTT’s) Communication Switching Laboratories, Tokyo Japan, where he was engaged in research and development of a high-speed switching system and high-speed switching technologies such as ultra-high-speed switching LSI, packaging techniques and interconnection techniques for Broadband ISDN services. Since 1989, he has been active in the development of Broadband ISDN based on ATM techniques. He is now researching future ATM based broadband ISDN architecture, and traffic management and performance analysis of ATM networks. He is currently a senior research scientist, supervisor, distinguished technical member in Broadband Network System Laboratory at NTT. Dr. Yamanaka received Best of Conference Awards from the 40th and 44th IEEE Electronic Components and Technology Conference, TELECOM System Technology Prize from the Telecommunications Advancement Foundation, two times of IEICE Switching System Research Award and IEEE CPMT Transactions Part B: Best Transactions Paper Award in 1990, 1994, 1994, 1996, 1998 and 1996 respectively. Dr. Yamanaka is Broadband Network Area Editor of IEEE Communication Surveys, Associate Editor of IEICE Transaction, IEICE Communication Society International Affairs Director as well as Secretary of Asia Pacific Board at IEEE Communications Society. Dr. Yamanaka is a senior member of IEEE.

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Kohei Shiomoto received the B.E., M.E., and Dr.E. degrees in Information and Computer Sciences from Osaka University, Osaka, Japan, in 1987, 1989, and 1998 respectively. He joined the Nippon Telegraph and Telephone corporation (NTT), Tokyo, Japan in 1989. From 1989 to 1994, he was engaged in research and development of ATM switching system in NTT Communication Switching Laboratories. From 1995 to August 1996, he was engaged in research on traffic controls for B-ISDN at NTT Network Service Systems Laboratories. From August 1996 to September 1997, he was engaged in research on high speed networking as a Visiting Scholar at Washington University in St. Louis, U.S.A. Now he is engaged in research of high speed network architecture at NTT Network Service Systems Laboratories as a Senior Research Engineer. He received the Young Engineer Award of the Institute of Electronics, Information and Communication Engineers from the Institute of Electronics, Information and Communication Engineers (IEICE) in 1995. Dr. Shiomoto is a member of IEEE.