DWDM data receiver based on monolithic integration of an echelle grating demultiplexer and waveguide photodiodes A. Densmore, V.I. Tolstikhin and K. Pimenov A practical approach for the design and manufacture of a monolithically integrated, multiple wavelength data receiver is presented. It utilises an InP-based, birefringence compensated echelle grating demultiplexer and high speed, singlemode, vertically integrated waveguide photodiodes. As an example of this approach, a 32-channel, C-band, polarisation independent data receiver chip operating at OC-3 (155 Mbit=s) bit rate is demonstrated with a compact footprint of 5 16 mm.
Introduction: In DWDM transmission systems, data receiving requires demultiplexing prior to photodetection. Standard approaches to achieve such functionality are based on the use of stand-alone demultiplexers and photodetectors. At high channel counts, this becomes bulky, complex and costly owing to the large number of hybrid components and connections. An alternative solution is monolithic integration of a planar waveguide demultiplexer with an array of waveguide photodetectors (WPD) in a single photonic chip, which for common communication wavelengths should presumably be based in the InP material system. In this way, labour-intensive optical alignment of multiple discrete components is eliminated, whereas footprint, reliability and cost are greatly improved. However, the design of such a device is challenging since the component must demultiplex the signal with minimum insertion loss, polarisation dependence and crosstalk while efficiently combining low-loss transparent waveguides with highly absorbing photodetectors. The integration technique must be practical, robust and have little to no wavelength and polarisation sensitivity over the entire operating wavelength band exceeding 35 nm. This eliminates butt-coupling integration techniques, which require multiple etch and regrowth steps from a practicality=cost point of view, and those vertical integration schemes, which do not address the polarisation and wavelength stability issues from a performance point of view. As a result, in spite of the evident advantages of monolithic integration and past efforts to implement them [e.g. 1–3], the success of InP-based DWDM receivers to adequately meet these requirements has been limited. In this Letter, we present a solution based on a compact echelle diffractive grating (EDG) planar demultiplexer having WPDs singlemode vertically integrated (SMVI) within its output waveguides. To illustrate this approach, a 32-channel, 100 GHz spaced DWDM data receiver chip is demonstrated.
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pin double heterostructure is grown atop a transparent GaInAsP=InP waveguide on an InP substrate. The epitaxial structure is similar to that described in [5] with the exception that smoothing layers are inserted at the p-side heterojunction to reduce heavy hole pile-up and in this way improve the WPD linearity and response speed. Polarisation independence of the demultiplexer is achieved through compensation of the birefringence in the slab waveguide area by etching a planar prism therein [6]. The polarisation dependent responsivity of the integrated photodetectors is minimised by design using the SMVI method [7] with WPDs of sufficient length to absorb greater than 95% of the input optical signal over all states of polarisation (SOP). The SMVI method differs from other vertical integration schemes since the waveguide photodetectors support only one optical mode, which closely matches that of the single supported mode in the passive waveguide. This allows stable and efficient passive-to-active waveguide coupling to be achieved over all SOP and the C-band, leading to near polarisation and wavelength independent operation.
Characterisation: The EDG demultiplexer transmission spectra were measured by a swept wavelength scanning technique using on-chip WPDs. Typical results obtained by taking photocurrent from each of the device’s 32 channels are shown in Fig. 2. The average value of the peak external responsivity (relative to the fibre-coupled optical power) is 0.2A=W, whereas the internal responsivity (relative to power coupled into the passive waveguide immediately before the WPD) was measured to be 1.1A=W. The difference, due to insertion loss, combines 1.4 dB for fibre to waveguide coupling loss and 6.0 dB for the inherent loss of the EDG demultiplexer (including propagation loss). The polarisation dependence of frequency and peak external responsivity is typically less than 3 GHz and 0.3 dB, respectively. The optical crosstalk for adjacent (determined by channel spacing and passband shape) and nonadjacent (determined mainly by scattering at the EDG facets) channels were measured to be below 35 and 37 dB, respectively. The low loss and low crosstalk performance exhibited by the EDG demultiplexer is largely accomplished by strict optimisation of the reactive ion etch process used to fabricate the echelle grating and passive waveguides.
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Fig. 2 Responsivity spectrum of 32-channel device operating at 3V reverse bias voltage (TE, TM polarisations shown)
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Fig. 1 Layout of 5 16 mm data receiver die
Design: The component utilises our earlier reported monolithic integration platform [4], which includes a birefringence compensated planar EDG demultiplexer and passive waveguide circuitry. The integration of high speed photodiodes on such a platform for data receiving applications is now reported, which maintains its advantages for DWDM (e.g. minimal loss, crosstalk and polarisation sensitivity). The layout of the device is shown in Fig. 1. The multi-wavelength signal is directed by a transparent ridge waveguide to the planar demultiplexer. The demultiplexer consists of an EDG operating in reflection mode, singlemode, shallow-etched input=output ridge waveguides and a slab waveguide region. After entering the slab waveguide the multi-wavelength signal laterally diverges and is diffracted by the EDG, thereby being demultiplexed into the corresponding output ridge waveguides, which each contain a vertically integrated 4 mm-wide, 475 mm-long WPD. The device layers are grown using a single MOCVD epitaxial run, in which a GaInAs=InP
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The on-chip WPDs exhibited a room temperature average dark current of 0.2 nA at 3V reverse bias, corresponding to 100 nA=mm2, which is among the lowest reported values for mesa-style GaInAs pin photodetectors. These low values are achieved by careful surface preparation and passivation during fabrication. The internal CW responsivity and rise time against reverse bias voltage are shown in Fig. 3. It is seen that the responsivity sharply increases at lower voltages V < VCW and then saturates at nearly 1.1A=W at higher voltages V > VCW , where the saturation voltage VCW depends on the waveguide-coupled input power and SOP. This behaviour is attributed to the field-assistant collection of heavy holes piled up at the p-side heterojunction at the GaInAs absorbing layer and the p-InP contact layer, such that at lower bias they recombine before being collected. The sharp drop of the rise time at voltages below a certain saturation voltage VRT, V < VRT , has a similar explanation. For optimum performance, the operating bias voltage is set higher than either of the saturation voltages above, over the optical power and SOP ranges. Both VCW and VRT are reduced to below 3V at 0 dBm input power, by inserting heterojunction smoothing layers between the i-GaInAs absorbing and p-InP contact layers. The polarisation dependent internal responsivity of the WPD was measured to be below 0.2 dB.
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Since the SMVI method relies on small confinement of the guided mode with the absorbing layer, which is compensated for by increasing the WPD length, it faces a strict responsivity=bandwidth trade-off [7]. At V > VRT, the bandwidth is limited primarily for by the capacitance, which combines the inherent capacitance of the pin junction, parasitics and that of the electrical circuit. The former, proportional to the WPD length, is measured to be 1.2pF=mm at a reverse bias voltage 3V. Parasitic capacitance from the metal leads used to route the photocurrent signals becomes appreciable for high channel counts. By covering the WPDs with 2.5 mm-thick dielectric and optimising the layout of the metal tracks the parasitic capacitance is limited to below 1 pF. S-parameter reflection measurements yield an average total capacitance of 1.6 pF for a 475 mm-long WPD (including parasitics) and a 3 dB bandwidth exceeding 1.25 GHz when loaded to 50 O. Although the reported device was designed for lower bit rate applications (described below), with further optimisation up to 2.5 Gbit=s (OC48 bit rate) operation is achievable (to be reported elsewhere). A particular application of the DWDM receiver chip that has recently generated significant interest is high channel count data reception in passive optical networks featuring a common central office transmitter [8]. In such a network, the upstream data is generated by modulating the same carrier that delivers the downstream data, but at considerably lower, typically 155 Mbit=s (OC-3) bit rate. To evaluate the device under such conditions, an evaluation board was constructed, which contained transimpedance=limiting amplifiers for each of the component’s 32 channels. The selected amplifiers had an input referred noise p of 1.3 pA= Hz, a bandwidth of 130 MHz and differential outputs.
Using an NRZ pseudorandom bit sequence of length 223 1 and a modulation ratio of 6.6, an average sensitivity of 23 dBm was achieved per channel at a bit error rate of 109. Conclusions: A compact 5 16 mm, 32-channel DWDM data receiver has been demonstrated by monolithically integrating an InP-based echelle grating demultiplexer with singlemode vertically integrated waveguide photodetectors. The reported design overcomes many of the practicality, cost and performance issues faced by manufacturers of such components and provides an attractive alternative to hybridbased solutions. # IEE 2005 Electronics Letters online no: 20051130 doi: 10.1049/el:20051130
28 March 2005
A. Densmore, V.I. Tolstikhin and K. Pimenov (MetroPhotonics Inc., 1887 St. Josephs Blvd., Ottawa, Ontario, Canada K1C 7J2) E-mail:
[email protected] References 1 2 3 4
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Chandrasekhar, S., et al.: ‘Monolithic eight-wavelength demultiplexed receiver for dense WDM applications’, IEEE Photonics Technol. Lett., 1995, 7, (11), pp. 1342–1344 Cremer, C., et al.: ‘Grating spectrograph integrated with photodiode array in InGaAsP=InGaAs=InP’, IEEE Photonics Technol. Lett., 1992, 4, (1), pp. 108–110 Tong, F.: ‘Multiwavelength receivers for WDM systems’, IEEE Commun. Mag., 1998, pp. 42–49 Tolstikhin, V., et al.: ‘InP-based monolithic integration of echelle grating (de)multiplexer, passive waveguide circuitry and active waveguide devices for applications in DWDM transmission systems’. 29th European Conf. on Optical Communication, Rimini, Italy, September 2003, Vol. 3, pp. 666–667 Tolstikhin, V., Densmore, A., et al.: ‘Monolithically integrated optical channel monitor for DWDM transmission systems’, J. Lightwave Technol., 2004, 22, (1), pp. 146–153 He, J.J., et al.: ‘Integrated polarization compensator for WDM waveguide demultiplexers’, IEEE Photonics Technol. Lett., 1999, 11, (2), pp. 224–226 Tolstikhin, V.I.: ‘Single-mode vertical integration of active devices within passive waveguides of InP-based planar WDM components’. Integrated Photonics Research (IPR02) Conf., Vancouver, Canada, July 2002, Paper IFC4 Takesue, H., and Sugie, T.: ‘Wavelength channel data rewrite using saturated SOA modulator for WDM networks with centralized light sources’, J. Lightwave Technol., 2003, 21, (11), pp. 2546–2556
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