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An 8 2.5 W 1%-THD 104 dB(A)-Dynamic-Range Class-D Audio Amplifier With Ultra-Low EMI System and Current Sensing for Speaker Protection Angelo Nagari, Member, IEEE, Emmanuel Allier, François Amiard, Vincent Binet, and Christian Fraisse
Abstract—Class-D amplifiers for portable devices are now demanding more than 2 W 1% THD output power on 8 speakers in smartphone and tablet for a better multi-media user experience. However higher acoustic power brings a lot of additional constraints such as speaker damage, more EMI energy and battery reset. The presented paper demonstrates a 2.5 W 1% THD into 8 Class-D amplifier with 104 dB(A) dynamic range using a new power stage architecture to reduce silicon area. The design includes a ULEMI system to reduce high frequency energy without impact on audio band noise and an embedded load current sensing for speaker protection algorithm. Index Terms—Switching amplifier, audio amplifier, class-D, pulse width modulation, speaker driver, EMI, EMC, speaker protection, current sensing.
I. INTRODUCTION
A
NEW concept of mobile phones has emerged in recent years: new definitions such as smart phone, feature phone, high-end phone or even the new entry netbook or tablet mean that in the user’s hands there’s much more than a simple telephone. Adding more features to a mobile system usually has the effect of increasing the current from the battery; applications such as video and imaging functions, large color display tasks, speech recognition or MPEG decoding are quite power-hungry. Having the audio domain to support a lot of multimedia new features such as music, movie playback, mobile TV and gaming, this has the effect of drawing further current from the battery. While older handsets just required a mono loudspeaker to play a ringtone for perhaps a few seconds every few hours, recent multimedia phone designs incorporate stereo speakers which are active for much longer periods, e.g., several minutes during TV streaming or gaming. These application features also require a higher level of audio quality at the speaker outputs than before and higher levels of volume: 1 W speaker output power is today a fairly typical requirement for most of loud applications. Other use cases such as media sharing are becoming popular as well: sharing a song with friends or information with colleagues is a powerful feature that could happen in areas of high ambient noise such as train stations, airports or simply along a populated Manuscript received April 17, 2012; revised September 07, 2012; accepted September 30, 2012. Date of publication November 30, 2012; date of current version December 21, 2012. This paper was approved by Guest Editor Wing Hung Ki. The authors are with ST-Ericsson, 38019 Grenoble Cedex, France (e-mail:
[email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2012.2225762
street; this would require even more power toward the objective of obtaining more than 2 W in a portable device. Class-D amplifiers for portable devices are typically specified for supply voltage range ideal for use with lithium batteries [1]–[5]. The high efficiency of Class-D amplifiers makes them ideal for operation from boosted supplies in order to provide output peak power on 8 integrated speakers higher than 2 W for a better user experience in all multi-media applications. In addition, new speakers can achieve better linearity and sensitivity leading to lower THD and noise specification in amplifier designs. To better respond to this challenge, this work presents a 2.5 W 1% THD Class-D amplifier on 8 load with 104 dB(A) dynamic range, having a set of features to cope with all high-power constraints such as high frequency energy, battery reset and speaker damage. In Section II, the conventional Class-D amplifier topologies are reviewed and the main directions of the proposed design are presented. In Section III, the new Class-D power stage based on dual-N architecture is illustrated. In Section IV the speaker protection problem is widely exposed with main focus on the implementation of the load current sensing circuitry needed to provide the required feedback to the protection algorithm. In Section V the Ultra-Low EMI (ULEMI) system is proposed with system simulation results. Finally, Sections VI and VII outline the experimental results and the conclusion, respectively. II. PROPOSED ARCHITECTURE Class-D amplifiers for portable devices are typically specified for operation from below 3 V to above 4.2 V, ideal for use with lithium ion or lithium polymer batteries. Across this voltage range the available power changes with battery voltage. For example, into an 8 load, 3 V gives about 500 mW, and 4.2 V gives about 1.1 W. Whenever more than 1 W output power into 8 , regardless of battery voltage, is required, the Class-D amplifier must operate with more than 5 V boosted supply. The proposed amplifier has been integrated into a system illustrated in Fig. 1(a). An embedded step-up DC-DC converter provides the required constant high voltage from battery and a high-resolution D/A steering current converter driven by a IV order 1-bit sigma delta modulator completes the audio system for a better placement close to the speaker. Some drawback has to be considered in boosting Class-D amplifiers: one is the additional coil required by the step-up and also the size of this new component that must be compliant with
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Fig. 1. (a) Block diagram of Class-D amplifier sub-system including all features: step-up, AGC, ULEMI, and Load Current Sensing path (b) AGC curve example.
the very high peak current of a more than 1 W amplifier; then, being the step-up switching at 1.6 MHz the Class-D PWM frequency must a multiple of it to avoid any intermodulation effect between the two blocks (with a very careful layout to isolate their respective grounds). Moreover, being the overall system supplied by a battery, a dedicated fast automatic gain control (AGC) system should prevent the Class-D power requirements from resetting the system in case the battery is no longer able to sustain a certain amount of peak current (i.e., Class-D exceeding A cur1 W output power needs a boost that can cause rent spikes at battery domain. The current spikes also increase dramatically when battery voltage becomes lower, eventually leading to the situation that causes the system reset when exceeding the current budget of the battery). AGC should react fast to the battery voltage changes; a typical value in today’s products is never less than 20 s/dB gain reduction for the attack time. This value should be anyhow changeable with a register setting. To avoid “pumping” sound, the output release time for the gain should be higher; typical value of 1600 ms/dB with 0.5 dB steps are quite common, this value too should be changeable from register settings [9]. In conclusion AGC monitors the battery voltage and the audio
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signal, automatically decreasing gain when battery voltage is low and audio output power is high. It finds the optimal gain to maximize loudness and minimize battery current, providing louder audio and preventing early shutdown at end-of-charge battery voltages. AGC decreases amplifier gain when the audio signal exceeds the limiter level. The limiter level automatically is below the “trip” decreases when the supply voltage point. Fig. 1(b) shows an example of the programmable limiter level as a function of the supply voltage. Another issue is related to speaker choice: mobile phones cannot afford big size speakers, thus feeding more than 1 W on small components leads to a high risk of permanent damage. Another way to increase output power without the need of a step-up circuit is to reduce speaker impedance. Several products show the capability of providing 3 W on 3 minimum load in very tiny packages such as 9-ball Wafer Level Chip Scale Package (WLCSP). This trend requires a particular care in mobile phones design: driving a big amount of power on very low impedance loads increases dramatically the losses due to interconnection parasitic. This does justify the choice of mentioned packages without bonding wires and of small size, in order to shorten as much as possible the distance between amplifier and speaker. However “small” 4 speakers are not yet available on the market, thus most solutions have to face 8 load with boosted supply. The proposed Class-D amplifier has a classical second order closed-loop architecture as illustrated in Fig. 2 based on classical Natural Sampling Double-Sided (NBDD) PWM ternary modulation [7], [8]. The amplifier’s power stage is based on cascoded dual-N topology to optimize overall die area, plus a set of additional high-voltage features: Ultra-Low EMI (ULEMI) system to reduce high frequency peak energy and load current sensing A/D path in order to obtain, with a dedicated speaker protection algorithm, a real-time spectrum image of the load. These three main topics will be presented in the following sections. III. DUAL-N POWER STAGE In Class-D amplifier’s design suitable for output power higher than 2 W, the output stage area represents more than 75% of the whole audio amplifier. Optimizing the power stage size is by consequence an important challenge to save silicon area and cost. Another important point in high-power Class-D design is the associated power supply. To reach 2 W of output power or even more, the supply voltage has to be higher than 5 V. In the proposed design, to reach the target of 2.5 W 1% THD on 8 load a supply voltage of at least 6.5 V has to be provided by the boost. Such higher voltage for deep sub-micron technology can induce severe issues on the silicon reliability. In this design a 130 nm CMOS technology has been used with a gate oxide tolerating voltage up to 4.8 V without any reliability issue. To deliver high power and support voltages higher than 4.8 V, cascoded architectures have to be implemented to protect MOS devices from Hot Carrier Injection (HCI) and avoid the use of high voltage transistor whose require more complex driving system and extra-mask in the required technology [6].
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Fig. 2. Closed Loop Filter implementation of the proposed Class-D amplifier based on Ternary NBDD PWM modulation.
Fig. 3. Class-D half bridge power stage schematic comparison between (a) P/N and (b) dual-N cascoded devices with integrated bootstrap capacitor (assuming ). as unit area ‘A’ the NMOS device one with equivalent
The well known cascoded P/N architecture can be used for the purposes of this design. Nevertheless, such architecture consumes a lot of area due to bad drain-source ON resistor [Rdson] of the PMOS (around 3 times more resistive than an NMOS with equivalent dimension). If we consider ‘A’ the area of one NMOS with given dimension ), the total area W/L (Rdson is proportional to of the H-bridge output stage is then ‘4 A’ ` ' ` '. PMOS Rdson is obviously the weak point of the cascoded P/N architecture. Another important point is also the voltage bias the Class-D supply of the cascode PMOS gate. Being the given battery voltage (i.e., the input of voltage and the boost dc-dc converter), to insure all devices reliability, the ”. cascode PMOS gate voltage has to be “
To generate such voltage an extra circuitry is needed (such as an external LDO or an internal active clamp), and the cost of extra silicon area. One possible improvement is to use a cascoded dual-N architecture, in this case the total area can be decreased by 50% down to ‘8 A’ as only NMOS are used. Fig. 3 illustrates the comparison between cascoded P/N and dual-N topologies. The main difference of dual-N topology vs. the classical one is the presence of the bootstrap capacitor (one for each Class-D power stage branch) required to supply the driver and to bias the cascode of the high side NMOS devices. The main drawback is the control and the integration of those bootstrap capacitors in order to shift the ‘high side’ NMOS gate control associated with a dedicated circuitry to recharge them when the ‘low side’ NMOS is conducting (an embedded MOS diode is present to recharge the
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Fig. 4. Dual-N cascoded devices with integrated bootstrap capacitor working phases: (a) First phase with conduction on low side NMOS and charge of bootstrap embedded diode. (b) Second phase with conduction on high side NMOS and discharge of bootstrap capacitor to bias the driver and capacitor through the the high side NMOS.
Fig. 5. Voltages diagram of Dual-N cascoded working phases (being
the C_bootstrap capacitor voltage).
capacitor). Two control phases are required during normal operation as shown in Fig. 4. The first phase is the capacitor charging phase (Fig. 4(a)). An input signal set to ‘0’ is driving the input of the logic block is then present allowing the low side NMOS conduction. on the low side NMOS gate. The Class-D output is at GND (considering half bridge only). The bootstrap capacitor is thus (where charged through the diode at is the threshold diode voltage in forward bias). The end of this phase occurs when the input signal is set to ‘1’ at the input of the logic block. The second phase is the capacitor discharge phase (Fig. 4(b)). As soon as the input signal is set to ‘1’ at the input of the logic block, the high side NMOS gate voltage is raised up to voltage, thanks to the associated level shifter, in order to allow the device conduction. During this phase, the low side NMOS is OFF. At the beginning of the capacitor discharge phase, being is thus equal to the output node at GND, (exactly equal to the value after the charging phase). Then the high side NMOS starts conducting and ; by consequence the pulling the output node to (corresponding to the output node plus the
voltage across the capacitor) is following and it increases up to “ “ as clearly illustrated in the timing diagram in Fig. 5. Moreover, during the increase, the voltage across the diode becomes strongly negative and thus the diode turns into reverse mode. voltage represents the amount of charge taken The from the capacitor to bias high side cascode NMOS gate and to supply the driver. This amount of discharge is proportional to the whole high side NMOS gate area; due to this, the bootstrap capacitor has to be properly dimensioned to keep the voltage across the capacitor as high as possible in order to have the best high side NMOS Rdson. A drawback of this architecture is obviously the recharge of the capacitor. If the bootstrap capacitor is not recharged enough at each cycle of low side NMOS conduction, the system could freeze in a blocking state. To guarantee the recharge, a 50 ns minimum pulse duration system has been implemented in the PWM modulator to force the charging phase duration for a minimum given time ensuring the recharge of the bootstrap capacitors. The embedded charging diode has been designed using a simple MOS structure suitable to ensure the full recharge of the bootstrap capacitor in the given constant time; the equivalent diode area is then negligible compared to the overall amplifier.
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Fig. 6. Adaptative Loudspeaker Protection [ALP] System and typical integrated miniature speaker impedance vs. frequency.
Analyzing the dual-N power stage in term of reliability it can be noticed how, when high side NMOS devices are ON, the ; by consequence the cascode OUT voltage is set to low side NMOS sees across its gate and drain a voltage equal to: . To insure that no device breakdown happens, this voltage must not go above 4.8 V (as maximum allowed voltage in used technology). Thus the worst case is when is at lowest value down to 2.3 V, thus the maximum voltage must not exceed 7.1 V. These values are in line with the design requirements: 7.1 V is more than enough to ensure the 2.5 W 1% THD on 8 load even for worst case devices; moreover the AGC system will never allow having maximum voltage for very low . The last point to be considered in the dual-N power stage design is the bootstrap capacitor area. To ensure the good behavior of the 2.5 W power stage an integrated capacitor of 800 pF is required to achieve the required high side NMOS Rdson. However, thanks to the technology used in the presented design having a 5 fF/ m MIM capacitor, the bootstrap capacitor has been stacked exactly over the power stage without any area impact. The stack of the MIM capacitor over active power devices doesn’t show any problem to the normal behavior of the amplifier; only the bottom plate parasitic capacitor can cause a slight loss of overall efficiency during the charging phase (but negligible at system level). IV. LOAD CURRENT SENSING In inductive speakers the sound is produced by a membrane displacement mechanically coupled with a magnetic core, which is electrically controlled by inductive coupling. If the electrical signal level is too high at specific frequencies, membrane displacement can cause damage to occur, either by
self-heating or by mechanical constraint. In addition, above more than 50% of the speaker maximum electrical power, most of the speakers are clipping (which means the membrane touches the case) producing audible cracking, but if signal is around the impedance resonance frequency (in the range of 500–1000 Hz for most common integrated miniature speaker in acoustic box), the membrane moves easily and small amounts of power can push the speaker beyond its limit. To protect the speaker from those behaviors an Adaptative Loudspeaker Protection (ALP) system has been defined as in Fig. 6 by a complex path including signal processing at the platform level to compute in real time the Speaker impedance transfer function of the load and drive a dynamic re-equalization, in order to limit the energy around speaker resonance frequencies, avoid damages and increase loudness. To allow this computation a sensing path has been designed to provide a temporal image of the current flowing into the load as illustrated in Fig. 7(a). The sensing devices are a couple of suitably designed resistors of 80 m each, placed between the lower H-bridge side and the ground ball (thus a real connection to ground plane including the package lines). The voltage drops through these resistors is fully differentially sensed by a low-noise amplifier (LNA) acting at the same time as anti-aliasing filter (AAF) and as gain error compensation, plus trimming before feeding an embedded 1-bit A/D converter. As a matter of fact, the gain of the load current sensing path takes into account the gain variations of the DAC and Class-D path due to the AGC feature described in session I, because this setting is not provided out of the device, as it depends on the system power environment. Thus each gain variation of the AGC is directly corrected in an opposite way in the Low Noise Amplifier. The overall group delay of the current sensing path has no impact on the whole
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Fig. 7. (a) Load current sensing schematic based on parasitic sensing resistors with Temperature variation compensation and AGC gain adjustment (b) Current output (Gain @ 22 sensing path simulations results: on top spectrum Class-D FS output signal (PWM and filtered on Rload), on bottom spectrum mismatch). dB) and 1-Bit ADC PDM output (with some offset in LNA and 1% of
ALP loop as the algorithm has to compensate quite slow variation of the speaker impedance. The 80 m H-bridge sensing resistors are elaborated with copper parasitic resistors redistribution layers into the package. The matching of these two resistors has only an effect on the THD of the current sensing path, which has no sensible effect on the software equalization. However, the absolute value spread provides directly a gain error on the current sensing channel.
This process dependent variation is corrected during the test manufacturing, through a dedicated trimming, addressing an auxiliary bank of gain adjustment, into the Low Noise Amplifier, in combination with the main inverted gain adjustment from AGC setting. Another variation of current sensing gain can occur vs. temperature, due to the temperature coefficient of the sensing resistors as described in Fig. 7(a). Being, in the embedded ADC, the
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showing the ADC 1-Bit PDM0 output spectrum analysis with a 1% sense resistor mismatch and several mV of LNA offset. V. ULTRA-LOW EMI SYSTEM
Fig. 8. Load current sensing path gain: (a) Variation with temperature and package process spread. (b) After ADC compensation.
absolute gain inversely proportional to the reference value, the temperature variations are compensated through the ADC reference itself using resistors with an equivalent temperature coefficient. The reference voltage buffer of the A/D Converter uses poly two types of resistors from the 0.13 um CMOS process: and high ohmic poly resistors, their temperature behavior and mismatch coefficients being perfectly known. The sensing path gain variation vs. temperature and process due to the reference buffer has thus an opposite behavior to the one shown in Fig. 8(a). At least, implementing 5 trimming bits in the dB to dB range and 0.5 dB Low Noise Amplifier with a steps, the total sensing path variations according to temperature dB to 0.6 dB as and process are bounded in a range of shown in Fig. 8(b). The A/D Converter is a 1-bit second order double sampling sigma delta modulator [10] with a dedicated ball for its clock (mainly for Class-D analog inputs use case). The input referred noise of the amplifier is about 1.2 Vrms A-weighted. The overall current sensing dynamic range is better than 80 dB(A), dB with an additional current with sense gain of up to consumption of about 2 mA. Fig. 7(b) shows a single sine-wave simulation results of the current sensing path with an LNA gain of 22 dB (suitable to have FS signal at the ADC ouput) and
The Class-D amplifier is a switching circuit and falls under the category of electro-magnetic interference (EMI) susceptible circuits, because the power stage provides a lot of wide band energy in the radio bands. This wide-output spectrum can lead to high-frequency RF emission and interference by electric field and magnetic field combination (Electro-magnetic radiations). Most of today’s Class-D amplifiers use a PWM based on ternary modulation as preferred choice, leading to a high-frequency minimum RF emission and interference and no differential switching across the load for very low audio signal and idle mode. In addition, for the power supply levels selected for this design, common mode signal doesn’t provide a lot of magnetic field, as that energy could become problematic in higher power design as explained in [11]. Nevertheless, in many applications using long connections (acting as an antenna) from power stage to the speaker, the out of band spectrum energy is too high and it is necessary to filter the Class-D amplifier output to comply with FCC/CEM standard limits (thus electro-magnetic compliance EMC) and to reduce emission at higher frequencies, especially if a frequency sensitive circuit operating higher than 1 MHz is nearby (i.e., RF circuits, FM radio, etc.). Usually ferrite beads placed as close to the device as possible are very effective as shown in Fig. 9. Unfortunately, more selective is the chosen ferrite (i.e., more selective is the filter) and more non-linearity is introduced on the speaker path with consequent degradation of audio performance. To allow the use of less selective ferrite (thus better audio performance) and to keep high EMI immunity, the high frequency energy at the output of the Class-D amplifier should be further reduced. Several techniques have appeared in the literature claiming to be EMC without any extra components [12]–[14], based on new approaches such as spread spectrum modulation or new digital modulation of the PWM signal, in order to reduce peak energy in high frequency range. This spread spectrum is generally done with additional pseudo-random noise on the PWM clock modulation. In this case a high period jitter noise is provided, following a lot of shaped noise, by the modulation, with consequent degradation effect of the signal to noise ratio in audio band. The novelty of the proposed design consists of a spread spectrum on clock generation for the PWM block using a programmable delay line to reduce the high frequency spurs of about 11 dB, without affecting idle noise in the audio band and overall efficiency. The ULEMI delay line is composed of digital buffered RC wires driven by a well known signal, in order to control the higher timing jitter with the lower period jitter as shown in Fig. 10. The timing jitter is the difference edge and the between the time of the spread clock time of the clock CLK edge. We call the gap between two the successive periods of the spread spectrum clock period jitter. Timing jitter is the integral of period jitter. Low period jitter doesn’t disturb much the double ramp of Class-D ternary modulation and spectrum energy stays within a notch,
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Fig. 9. Classical EMC solution for Class-D amplifier based on ferrite chip bead filter. More selective is the ferrite (i.e., Ferrite 1) and higher degradation of audio performance has to be expected.
Fig. 10. ULEMI block diagram: (a) 5-bit programmable delay line; the sequencer provides the sine-wave to control the jitter spread. (b) Output timing jitter evolution.
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following minimum noise into the audio-band; on the contrary the higher timing jitter is spreading enough the wide band energy reducing its peak energy. For those reasons the best choice is to use a single tone sine-wave jitter signal as follows:
where is the amplitude of the period jitter and is the amplitude of the timing jitter. kHz (equal to With a carried frequency of the PWM modulation frequency), we choose a timing jitter frekHz; this value has been quency at selected as the optimal one vs. in band spurious amplitude and noise folded energy, and in order to obtain the best high frequency energy reduction vs. the jitter quantization LSB. With the proposed delay-line, the minimum to maximum amplitude of the timing jitter will be 62 ns and, in our case:
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The Class-D saw-tooth spectrum concentration is around 1 GHz due to the 1 ns extra bit, thus from that frequency the energy is no longer spread but a good attenuation (more than 10 dB) is obtained between 10 MHz and 1 GHz. All components at N 1 GHz fall into “Ultra” frequencies range; the Class-D ternary modulation doesn’t provide high energy in this spectrum area, thus it is acceptable to limit the spread effect till that value. The last consideration on ULEMI delay line is about the unitary time generated by all RC time constants, which have % to % due to process a Gaussian distribution from spread (spectral concentration from 700 MHz to 1.3 GHz). However, because speaker connections could be very short, the equivalent antenna can provide more easily electromagnetic radiation in very short waves (i.e., very high frequencies above 30 MHz) and much less at medium waves and long waves (i.e., lower frequencies). Thus, it is more necessary to reduce those high frequencies energies above 30 MHz. Moreover, into the “Ultra High” frequencies range above 300 MHz, the radiated energy is quite low due to the finite slew-rate of the Class-D Bridge. Based on all above considerations, even with 700 MHz worst cases for no spread energy, corresponding to 1 ns jitter %, no EMI issues are expected. quantization with VI. EXPERIMENTAL RESULTS
The maximum amplitude between two consecutive periods of PWM modulation clock will be very low: 1.5217 ns. The continuous time repartition of the jitter will be a sine wave for the timing jitter with amplitude equal to 1.5217 ns, related to cosine wave for the period jitter with amplitude equal to 31 ns performed into the delay-line. Because we can’t modulate the -bit quanperiod jitter with an infinite number of values, a tization is enough for the designed delay line as illustrated in Fig. 10(a); having possible combinations, the resulting ns. quantization time is equal to 62 ns/32 More in detail: the delay line LSB (period jitter) is 2 ns (R*2C). The bigger weight is equal to ns for a total of 5-bit quantization (R*32C). An extra bit with 1 ns resolution (1/2 LSB thus R*C) is added in order to keep the duty cycle at 50% for each programmed delay. In such way the two ramps of the saw-tooth Class-D modulation will always have the same time length. The delay line input digital code is provided by a sequencer at the modulation frequency obtained from the carrier frequency divided by 128 (i.e., kHz, kHz); this results in a single sine wave modulation around the carrier frequency. At a may comprise, given time, the spread spectrum clock depending on the 5-bit input code, a quantified cosine wave timing jitter and a 2 ns pulse density modulated at 76% sine % nsec) as wave for the period jitter ( illustrated in Fig. 10(b), keeping energy in narrow domain around PWM frequency (3.125 kHz for 400 kHz modulation); this lead to minimum shaped noise intermodulation minimizing the folded energy into audio band.
The proposed Class-D amplifier is fabricated in a 0.13 m CMOS process with 5 fF/ MIM capacitor and can be supplied up to 6.6 V by the embedded step-up. The product has been done in WLCSP 20 balls, 1.98 2.80 0.63, 0.5 mm pitch package as shown in Fig. 12; the highlighted tracks on the right side are the two 80 m sensing resistors drawn for the load current sensing path. The linearity and the efficiency performances are shown in Fig. 11. To better evaluate the ULEMI system performance we should know how, in general, the FCC standard gives 40 dB V/m maximum EMI at 30 MHz and 46 dB V/m at 300 MHz. This measurement makes sense only in the final application, including PCB layout. However, we can measure the efficiency of the proposed spread spectrum technique with a comparison of the out-of-band energy provided with and without ULEMI clock control as pictured in Fig. 13. This spectrum analysis shows a real efficiency into the radiobands with more than 10 dB reduction of the energy level. Other spread spectrum techniques provide equivalent radio bands efficiency though with SNR degradation into the useful audio bandwidth; on the contrary, with ULEMI system, which use delay-line controlled by sinusoidal jitter, we can’t exclude that some visible effect will appear, as illustrated in Fig. 14. It can dBr be noticed how, with a very high input audio signal, at relatively to 2.5 W on 8 load, we observe into the audio-band the 3.125 kHz tones, modulated by the signal, at dBr level. These tones’ amplitude is lower than that of harmonic distortions, and, if we consider those acoustically perceptible only, same tones are hidden by the distortion itself in presence of a high amplitude signal. On the contrary, with a low input dBr, only the jitter quantization noise of audio signal, at the modulation clock itself appears (3.125 kHz and multiples)
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Fig. 11.
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and efficiency versus output power (1 kHz sine-wave) for 8
Fig. 12. Chip photograph: WLCSP 20 balls, 1.98
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load with ULEMI enabled.
0.63, 0.5 mm pitch. On bottom left the current sensing metal resistors are highlighted.
at dBr level, therefore inaudible on most of speakers. Finally, in terms of power, the added idle noise is at dBr only for the jitter contribution, quite negligible compared to overall noise performance. All those low-energy spurious disappear when ULEMI system is disabled. In summary, the proposed amplifier exhibits 0.025% of W output power on 8 for 1 kHz input signal. The measured idle channel noise is 28 (A-weighted) leading to an SNR of 104 dB(A) referred to a 2.5 W output power full scale at 1% THD with only 2 mA quiescent current (with ULEMI enabled and current sensing disabled). The table
in Fig. 15 compares the audio performances of the presented design with the most recent published closed-loop Class-D amplifiers for mobile application in same conditions and load. The presented amplifier matches with state-of-the-art performances reducing EMI energy up to more than 500 MHz and including the current sensing feature for the speaker protection algorithm. VII. CONCLUSION load with A 2.5 W 1% THD Class-D amplifier on 8 104 dB(A) dynamic range is proposed in this paper. The presented amplifier matches with state-of-the-art performances
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Fig. 13. ULEMI measurement results: out of band energy.
Fig. 14. ULEMI measurement results: FFT
dBr &
dBr.
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Fig. 15. Performance summary.
with a very low quiescent current and having a set of features to cope with all high-power constraints. Overall Class-D area has been reduced using a dual-N power stage. With ULEMI system the proposed design reduces EMI peak energy by more than 10 dB in a wide frequency range without any audio performance degradation (both SNR and THD). Finally the current sensing feature for the speaker protection algorithm has been introduced allowing (with the ALP algorithm) to have music loudness at the limit of the speaker’s power specification without any damage. ACKNOWLEDGMENT The authors would like to thank all those at ST-Ericsson, whose invaluable help made this design possible, in particular: Philippe Marguery, Philippe Sirito-Olivier Alain Chianale and Danika Perrin for the final product specification discussions, Gregoire Jouan, Christine Gonfaus, Catherine Popon, Sandrine Majcherczak, Noureddine Zitouni, Jiri Hejda, Marek Kijovsky, Radek Zeleny and Lizabeth Villapando for the layout. Special thanks go to Cedric Rechatin for all discussions on dual-N topology and to Simon Valcin for the valuable work of measurement and validation. REFERENCES [1] M. Teplechuk, T. Gribben, and C. Amadi, “Filterless integrated and 96 dB Class-D audio amplifier achieving 0.0012% PSRR when supplying 1.2 W,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2011, pp. 240–241. [2] “SSM2315 filterless, high efficiency, mono 3 W Class-D audio amplifier datasheet,” Analog Devices Inc.. Norwood, MA, Aug. 2008. -mW [3] B. Forejt, V. Rentala, J. D. Arteaga, and G. Burra, “A Class-D design with direct battery hookup in 90-nm process,” IEEE J. Solid-State Circuits, vol. 40, pp. 1880–1887, Sept. 2005. [4] “TFA9881 3.4 W PDM input Class-D audio amplifier datasheet,” NXP Semiconductor B.V., Apr. 2011. [5] M. Wang, X. Jiang, J. Song, and T. Brooks, “A 120-dB dynamic range 400 mW Class-D speaker driver with fourth-order PWM modulator,” IEEE J. Solid-State Circuits, vol. 45, pp. 1427–1435, Aug. 2010. [6] M. Berkhout, “An integrated 200-W Class-D audio amplifier,” IEEE J. Solid-State Circuits, vol. 38, pp. 1198–1206, July 2003.
[7] L. Risbo and C. Neesgaard, “PWM amplifier control loops with minimum aliasing distortion,” 120th Audio Engineering Society Convention, May 2006, paper 6693. [8] K. Nielsen, “A review and comparison of pulse width modulation (PWM) methods for analog and digital input switching power amplifiers,” 102nd Audio Engineering Society Convention, Mar. 1997, paper 4446. [9] “TPA2015D1 2 W constant output power Class-D audio amplifier with adaptive boost converter and battery tracking speakerguard AGC datasheet,” Texas Instrument Inc.. Dallas, Texas, Nov. 2011. [10] A. Nagari, A. Mecchia, E. Viani, S. Pernici, P. Confalonieri, and G. Nicollini, “A 2.7-V 11.8-mW baseband ADC with 72-dB dynamic range for GSM applications,” IEEE J. Solid-State Circuits, vol. 35, pp. 798–806, June 2000. [11] P. P. Siniscalchi and R. K. Hester, “A 20 W/channel Class-D amplifier with significantly reduced common-mode radiated emissions,” in ISSCC Dig. Tech Papers, Feb. 2009, pp. 448–449. [12] C. Edwards, “Efficient Low EMI Switching Output Stages and Methods,” US Patent 7 190 225, Mar. 13, 2007. [13] “Spread-spectrum-modulation mode minimizes electromagnetic interference in Class-D amplifiers,” Maxim Integrated Products Inc., Sept. 13, 2006, APP 3881. [14] R. Cellier, E. Allier, A. Nagari, C. Crippa, and R. Bassoli, “A fully differential digital input class D with EMI spreading method for mobile application,” in Proc. AES 37th Int. Conf., Aug. 2009, pp. 39–47.
Angelo Nagari (S’92–M’96) was born in Cilavegna, Pavia, Italy, in 1968. He received the degree in electronic engineering (summa cum laude) from the University of Pavia, Italy, in 1993. He has been with ST-Microelectronics, Milan, Italy, since 1993, where he was involved as a Design Engineer in the analog and mixed IC development for cellular telecommunications. His main research interests are in the fields of Nyquist and Oversampled converters for System-on-Chip in Audio, RF and Auxiliary applications. Since February 2008 is IP design manager in ST-Ericsson, Grenoble, France. His main role is to define mixed-signal architecture and partitioning for mobile phones platforms and provides IP design on Audio and Power Management fields. Recently he has been appointed “Analog & System IP” Core Competence responsible for ST-Ericsson analog system development area, having as a main objective to drive all related R&D development. He is a reviewer of several IEEE journals (TCAS, JSSC) and conferences (ISCAS, ESSCIRC) and, within ST-Ericsson, he holds several patents.
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Emmanuel Allier was born in Blois, France, in 1975. He received the degree in electronic engineering from the “Institut Supérieur d’Electronique du Nord”, Toulon, France, in 1998, then a Master degree and a Ph.D. degree in microelectronics from the “Institut National Polytechnique de Grenoble”, Grenoble, France, in 1999 and 2003 respectively. From 2003 to 2005, he was a research and teaching assistant at the “Ecole Nationale Supérieure de Radioélectricité de Grenoble”, Grenoble, France. He joined STMicroelectronics then ST-Ericsson, Grenoble, France, in 2005 and 2009 respectively, where he is involved in the design of audio and monitoring CMOS mixed/analog IPs for cellular phones, in particular Class-D amplifiers, A/D converters and current gauge.
François Amiard was born in Caen, France, in 1977. He received the degree in electronic engineering from the engineering school of ENSERG in 2001. He joined ST Microelectronics, Rousset, France in 2003. Since 2009 he is with ST-Ericsson in Grenoble where he is involved in the development of audio IPs for mobile platform as an analog and mixed signal designer.
Vincent Binet was born in Clermont-Ferrand, France, in 1982. He received the degree in electronic engineering from the engineering school of SUPELEC in 2005. In 2007, he also received the M.Sc. degree in microelectronic from the “Ecole Polytechnique de Montréal”, Quebec, Canada. He joined ST Microelectronics, Grenoble, France in 2007. Since 2009 he is with ST-Ericsson where he is involved in the development of audio IPs for mobile platform as an analog and mixed signal designer.
Christian Fraisse was born in Aigues-Vives, France in 1955. He received the 2nd degrees in electronics from the “Conservatoire National des Arts et Métiers”, Paris, France in 1984, and the title of Engineer D.P.E (Diplomé Par l’Etat, Journal Officiel 29 fevrier 1992) in electronics from the “Ecole Nationale Supérieure d’Electronique et de Radioélectricité de Grenoble”, France, in 1991. He worked on the first generation of modems design, at EFCIS and SGS-Thomson since 1979 until 1987 and on the second generation of modems and audio converters, based on sigma-delta principle, until 1998. In quality of Design Project Leader, he worked on the firsts ADSL modem analog-front-end, developing high speed pipelined Analog-to-Digital Converters and auto-calibrated steering current Digital-to-Analog Converters until 2002. Since 2009 he is with ST-Ericsson as Member of the Technical Staff where he is working as an expert design engineer in audio systems.
