Text: Charles H. Roth Jr., Fundamentals of Logic Design, 4th ed., 1992, ISBN
0534954731. The 4th edition is strongly recommended. Grading: Course grading
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ECE 349 Background Study in Digital Computer Fundamentals Course Syllabus and Schedule
Instructor: James F. Frenzel, PhD, PE Phone: 800-824-2889 (x-7532) E-mail:
[email protected] Web: www.uidaho.edu/~jfrenzel Text: Charles H. Roth Jr., Fundamentals of Logic Design, 4th ed., 1992, ISBN 0534954731. The 4th edition is strongly recommended. Grading: Course grading differs from that discussed in the lectures. There are six semester exams, each worth 50 points, and a final exam worth 100 points. In order to pass this course, all exams must be completed on schedule, each with a minimum grade of 60%, and a minimum exam average of 70%. If you have any questions, contact Jim Frenzel. Reading: You should complete reading assignments prior to the lectures, and will be responsible for material covered in both the readings and the lectures. Homework: Homework will be assigned but not collected or graded. Solutions are available in PDF format from the course web page. Exams: There will be 6 semester exams, each worth 50 points. Final Exam: There will be a comprehensive final exam, two hours in length, and worth 100 points. Due Dates: You should view three lectures every week and take an exam approximately every two weeks. (Exams are assigned a lecture number in the table below.) Each exam must be received within one week of viewing the preceding lecture. Any exam taken after that date will be assigned a grade of zero. If you have any questions please contact the instructor, Jim Frenzel.
Exam Number 1 2 3 4 5 6 Final
Lecture Number 7 13 21 30 37 42 After Lecture 44
Lec # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Topics Numbers, Digital Systems Boolean Algebra, Gates Complements, Duality XOR, Pos & Negative Logic Minterms, Maxterms, & Don’t Cares Minimization: K-Maps Exam 1: Units 1, 2, 3, 5 K-Maps Quine-McCluskey Method Petrick’s & Branching Methods Map-Entered Variables All Nand & Nor Circuits Exam 2: Units 6, 7, Handout Multiple Output Ckts. Multiplexers & Decoders ROMs & PLAs PALs & SR Flip-Flops D & T Flip-Flops JK Flip-Flops State Machines Exam 3: Units 9, 11, Handout State Machine Analysis State Machine Analysis More State Machine Analysis Counter Design JK-Based Design Sequence Detector Design Design Examples Exam 4 (Take Home): Units 12, 13, 16 Registers & Register Transfer ROM & PLD-Based Machines Adders, Two’s Complement Parallel Multiplier Design Static and Dynamic RAM State Machine Timing Exam 5: Units 18 – 22 More State Machine Timing Output Glitches Asynchronous Inputs Review Exam 6: Handouts Introduction to Microprocessors Introduction to Microprocessors Microprocessor Architecture Final Exam
Reading/HW Unit 1 Unit 2 3.1 – 3.3 3.4 – 3.5, HW #1 Unit 5 6.1 – 6.4, HW #2 6.5 – 6.7 7.1, 7.2, & 7.4, HW #3 7.3 & Handout 7.5 Unit 8, HW #4 9.1 – 9.3 9.4 & 9.5 9.5 – 9.6 9.7, 11.1 – 11.2, HW #5 11.3 – 11.4, & Handout 11.5 – 11.9, 13.1, HW #6 13.2 – 13.3 13.2 – 13.3 13.3 – 13.4 12.1 – 12.3, 12.6, HW #7 12.4, 12.9 Unit 14 16.1 & 16.2 HW #8 Unit 18 Unit 19 Unit 20 21.1 – 21.2 Handout, HW #9 Handout Handout Handout Handout, HW #10 Handout Handout
