ECE 4510 Introduction to Microprocessors Chapter 10

ECE 4510 Introduction to Microprocessors Chapter 10 Dr. Bradley J. Bazuin Associate Professor Department of Electrical and Computer Engineering College of Engineering and Applied Sciences

Material from or based on: The HCS12/9S12: An Introduction to Software & Hardware Interfacing, Thomson Delmar Learning, 2006.

Chapter 10 • Serial Peripheral Interface (SPI) – Extended serial string transmission

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2 Material from or based on: The HCS12/9S12: An Introduction to Software & Hardware Interfacing, Thomson Delmar Learning, 2006.

What is Serial Peripheral Interface (SPI)? • • •

SPI is a synchronous serial protocol proposed by Motorola to be used as standard for interfacing peripheral chips to a microcontroller. Devices are classified into the master or slaves. The SPI protocol uses four wires to carry out the task of data communication: – – – –

MOSI: master out slave in MISO: master in slave out SCK: serial clock SS: slave select

•

An SPI data transfer is initiated by the master device. A master is responsible for generating the SCK signal to synchronize the data transfer. • The SPI protocol is mainly used to interface with shift registers, LED/LCD drivers, phase locked loop chips, memory components with SPI interface, or A/D or D/A converter chips. ECE 4510 Material from or based on: The HCS12/9S12: An Introduction to Software & Hardware Interfacing, Thomson Delmar Learning, 2006.

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Memory Addresses

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The HCS12 SPI Modules • •

The MC9S12DP512 has three SPI modules: SPI0, SPI1, and SPI2. By default, the SPI0 share the use of the upper 4 Port S pins: – – – –

•

PP3  SS1 PP2  SCK1 PP1  MOSI1 PP0  MISO1

(can be rerouted to PH3) (can be rerouted to PH2) (can be rerouted to PH1) (can be rerouted to PH0)

By default, the SPI2 shares the use of the upper 4 Port P pins: – – – –

•

(can be rerouted to PM3) (can be rerouted to PM5) (can be rerouted to PM4) (can be rerouted to PM2)

By default, the SPI1 shares the use of the lower 4 Port P pins: – – – –

•

PS7  SS0 PS6  SCK0 PS5  MOSI0 PS4  MISO0

PP6  SS2 PP7  SCK2 PP5  MOSI2 PP4  MISO2

(can be rerouted to PH7) (can be rerouted to PH6) (can be rerouted to PH5) (can be rerouted to PH4)

It is important to make sure that there is no conflict in the use of signal pins when making rerouting decision.

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Adapt9S12DP512 I/O Pins

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SPI Related Registers (1 of 6) •

The operating parameters of each SPI module are controlled via two control registers: – SPIxCR1: (x = 0, 1, or 2) – SPIxCR2

• •

The baud rate of SPI transfer is controlled by the SPIxBR register. The operation status of the SPI operation is recorded in the SPIxSR register. • The contents of the SPIxCR1, SPIxCR2, SPIxBR, and SPIxSR registers are illustrated in Figure 10.1 to 10.4, respectively. • The SS pin may be disconnected from SPI by clearing the SSOE bit in the SPIxCR1 register. After that, it can be used as a general I/O pin. • If the SSOE bit in the SPIxCR1 register is set to 1, then the SS signal will be asserted to enable the slave device whenever a new SPI transfer is started. ECE • 4510The equation for setting the SPI baud rate is given in Figure 10.3. Material from or based on: The HCS12/9S12: An Introduction to Software & Hardware Interfacing, Thomson Delmar Learning, 2006.

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SPI Related Registers (2 of 6) reset:

7

6

5

4

3

2

1

0

SPIE

SPE

SPTIE

MSTR

CPOL

CPHA

SSOE

LSBFE

0

0

0

0

0

1

0

0

SPIE: SPI interrupt enable bit 0 = SPI interrupts are disabled 1 = SPI interrupts are enabled SPE: SPI system enable bit 0 = SPI disabled 1 = SPI enabled and pins PS4-PS7 are dedicated to SPI function SPTIE: SPI transmit interrupt enable 0 = SPTEF interrupt disabled 1 = SPTEF interrupt enabled MSTR: SPI master/slave mode select bit 0 = slave mode 1 = master mode CPOL: SPI clock polarity bit 0 = active high clocks selected; SCK idle low 1 = active low clocks selected, SCK idle high CPHA: SPI clock phase bit 0 = The first SCK edge is issued one-half cycle into the 8-cycle transfer operation. 1 = The SCK edge is issued at the beginning of the 8-cycle transfer operation. SSOE: slave select output enable bit The SS output feature is enabled only in master mode by asserting the SSOE bit and the MODFEN bit of the SPIxCR2 register. LSBF: SPI least-significant-bit first enable bit 0 = data is transferred most-significant bit first 1 = data is transferred least-significant bit first

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Figure 10.1 SPI control register 1 (SPIxCR1, x = 0, 1, or 2) Material from or based on: The HCS12/9S12: An Introduction to Software & Hardware Interfacing, Thomson Delmar Learning, 2006.

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7

6

5

0

0

0

0

0

0

4

3

MODFEN BIDIROE

0

1

2

1

0

0

SPSWAI

SPC0

0

0

0

MODFEN: Mode fault enable bit 0 = Disable the MODF error 1 = Enable settinig the MODF error BIDIROE: Output enable in the bidirectional mode of operation 0 = Output buffer disabled 1 = Output buffer enabled SPSWAI: SPI stop in wait mode 0 = SPI clock operates normally in stop mode 1 = Stop SPI clock generation in Wait mode SPC0: Serial pin control bit 0 With the MSTR bit in the SPIxCR1 register, this bit enables bidirectional pin configuration as shown in Table 10.1. Figure 10.2 SPI control register 2 (SPIxCR2, x = 0, 1, or 2)

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SPI Related Registers (4 of 6)

Table 10.1 SS input/output selection MODFEN

SSOE

0 0 1 1

0 1 0 1

Master Mode SS not used by SPI SS not used by SPI SS input with MODF feature SS output

Slave mode SS input SS input SS input SS input

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7

6

5

4

3

2

1

0

0

SPPR2

SPPR1

SPPR0

0

SPR2

SPR1

SPR0

0

0

0

0

0

0

0

0

SPPR2~SPPR0: SPI baud rate preselection bits SPR2~SPR0: SPI baud rate selection bits BaudRateDivisor = (SPPR + 1) 2(SPR + 1) Baud Rate = Bus Clock BaudRateDivisor 7 reset:

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Figure 10.3 SPI baud rate register (SPIxBR, x = 0, 1, or 2) 6 5 4 3 2 1

SPIF

0

0

0

SPTEF MODF 1

0

0

0

0

0

0

0

0

0

0

SPIF: SPI interrupt request bit SPIF is set after the eight SCK cycles in a data transfer, and it is cleared by reading the SP0SR register (with SPIF set) followed by a read access to the SPI data register. 0 = transfer not yet complete 1 = new data copied to SPIxDR SPTEF: SPI data register empty interrupt flag 0 = SPI data register not empty 1 = SPI data register empty MODF: mode error interrupt status flag 0 = mode fault has not occurred 1 = mode fault has occurred Figure 10.4 SPI status (SPIxSR) Material from or based on: The HCS12/9S12: An register Introduction to Software & Hardware Interfacing, Thomson Delmar Learning, 2006.

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SPI Related Registers (6 of 6) • Example 10.1 Give a value to be loaded to the SPIxBR register to set the baud rate to 2 MHz for a 24 MHz bus clock. • Solution: 24 MHz  2 MHz = 12. One possibility is to set SPPR2-SPPR0 and SPR2-SPR0 to 010 and 001, respectively. The value to be loaded into the SPIxBR register is $21. • Example 10.2 What is the highest possible baud rate for the SPI with 24 MHz bus clock? • Solution: The highest SPI baud rate occurs when both the SPPR2-SPPR0 and SPR2-SPR0 are 000. In this case the baud rate is 24 MH  2 = 12 MHz. ECE 4510


SPI Transmission Format (1 of 3) • The data bits can be shifted on the rising or the falling edge of the SCK clock. • Since the SCK can be idle high or idle low, there are four possible combinations as shown in Figure 10.5 and 10.6. • To shift data bits on the rising edge, set CPOL-CPHA to 00 or 11. • To shift data bits on the falling edge, set CPOL-CPHA to 01 or 10. • Data byte can be shifted in and out most significant bit first or least significant bit first. ECE 4510


SPI Transmission Format (2 of 3) Transfer SS (O) master only

Begin

End

SS (I) SCK (CPOL = 0) SCK (CPOL = 1) Sample I MOSI/MISO Change O MOSI Pin Change O MISO Pin tL MSB first (LSBF = 0) LSB first (LSBF = 1)

MSB LSB

tT Bit 6 Bit 1

Bit 5 Bit 2

Bit 4 Bit 3

Bit 3 Bit 4

Bit 2 Bit 5

Bit 1 Bit 6

tI

tL

LSB Minimum 1/2 SCK for tT, tI, tL MSB

Figure 10.5 SPI Clock format 0 (CPHA = 0)

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SPI Transmission Format (3 of 3) Transfer SS (O) master only

Begin

End

SS (I) SCK (CPOL = 0) SCK (CPOL = 1) Sample I MOSI/MISO Change O MOSI Pin Change O MISO Pin tL MSB first (LSBF = 0) LSB first (LSBF = 1)

tT MSB LSB

Bit 6 Bit 1

Bit 5 Bit 2

Bit 4 Bit 3

Bit 3 Bit 4

Bit 2 Bit 5

Bit 1 Bit 6

tI

tL

LSB Minimum 1/2 MSB SCK for tT, tI, tL

Figure 10.6 SPI Clock format 1 (CPHA = 1)

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Bidirectional Mode (MOMI or SISO) • • • • • • • • • •

A mode that uses only one data pin to shift data in and out. This mode is provided to deal with peripheral devices with only one data pin. Either the MOSI pin or the MISO pin can be used as the bidirectional pin. When the SPI is configured to the master mode (MSTR bit = 1), the MOSI pin is used in data transmission and becomes the MOMI pin. When the SPI is configured to the slave mode (MSTR bit = 0), the MISO pin is used in data transmission and becomes the SISO pin. The direction of each serial pin depends on the BIDIROE bit of the SPIxCR2 register. The pin configuration for MOSI and MISO are illustrated in Figure 10.7. To read data from the peripheral device, clear the BIDIROE bit to 0. To output data to the peripheral device, set the BIDIROE bit to 1. The use of the this mode is illustrated in exercise problem 10.8.

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Normal and Bidirectional Mode When SPE = 1

Serial Out

Normal Mode SPC0 = 0

Slave Mode MSTR = 0

Master mode MSTR = 1

MOSI

SPI MISO

SWOM enables open-drain output

Serial Out

SPI Serial In

MOSI

SPI

Serial In

Bi-directional mode SPC0 = 1

Serial In

MOMI BIDIROE

MISO

Serial Out

SWOM enables open-drain output

Serial In

SPI

BIDIROE

Serial Out

SISO

Figure 10.7 Normal mode and bidirectional mode

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Mode Fault Error • If the SSx signal goes low while the SPIx is configured as a master, it indicates a system error where more than one master may be trying to drive the MOSIx and SCKx pins simultaneously. • The MODF bit in the SPIxSR register will be set to 1 when mode fault condition occurs. • When mode fault occurs, the MSTR bit will be cleared to 0 and the output enable for the MOSIx and SCKx pins will be deasserted.

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SPI Circuit Connection • In an SPI system, one device is configured as a master. Other devices are configured as slaves. • The circuit connection for a single-slave system is shown in Figure 10.8. • A multi-slave system may have two different connection methods as illustrated in Figure 10.9 and 10.10. • In Figure 10.9, the master can exchange data with each individual slave without affecting other slaves. • In Figure 10.10, all the slaves are configured into a larger ring. A data transmission with certain slaves will go through other slaves. ECE 4510


Single IC Interconnection Master SPI Shift register

MISO

MISO

MOSI

MOSI

SCK Baud Rate Generator

VDD

Slave SPI

Shift register

SCK SS

SS Figure 10.8 Master/slave transfer block diagram

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SS Multiple IC Interconnection +5V

Slave 0 Shift register

SPI Master (HCS12) SS

MOSI SCK MISO SS

Slave 1 Shift register MOSI SCK MISO SS

Slave k Shift register

...

MOSI SCK MISO SS

SCKx MOSIx MISOx PP0 PP1 . . .

. . .

PPk Figure 10.9 Single-master and multiple-slave device connection (method 1)

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Daisy Chained Multiple IC Interconnection Slave 0 SPI Master (HCS12)

+5V

Shift register MOSI SCK MISO SS

SS

Slave 1

Slave k

Shift register

Shift register

...

MOSI SCK MISO SS

MOSI SCK MISO SS

...

SCKx MOSIx MISOx Figure 10.10 Single-master and multiple-slave device connection (method 2)

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Example 10.3 • Example 10.3 Configure the SPI0 to operate with the following setting assuming that Eclock is 24 MHz: – – – – – – –

6 MHz baud rate Enable SPI0 to master mode SCK0 pin idle low with data shifted on the rising edge of SCK Transfer data most significant bit first and disable interrupt Disable SS0 function Stop SPI in Wait mode Normal SPI operation (not bidirectional mode)

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Example 10.3 • Solution: fE / baud rate = 24 MHz/6 MHz = 4. We need to set SPPR2-SPPR0 and SPR2-SPR0 to 001 and 000, respectively. Write the value $10 into the SPI0BR register. – The following instruction sequence will configure the SPI0 as desired: movb #$10, SPI0BR ; set baud rate to 6 MHz movb #$50, SPI0CR1 ; disable interrupt, enable SPI, SCK idle low, data ; latched on rising edge, data transferred msb first movb #$02, SPI0CR2 ; disable bidirectional mode, stop SPI in wait mode movb #0, WOMS ; enable Port S pull-up

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SPI Desirable Utility Functions • The following operations are common in many applications and should be made into library functions to be called by many SPI applications: – – – –

Send a character to SPI Send a string to SPI Read a character from SPI Read a string from SPI

 putcspix (x = 0, 1, or 2)  putsspix (x = 0, 1, or 2)  getcspix (x = 0, 1, or 2)  getsspix (x = 0, 1, or 2)

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Function putcSPI0 putcspi0:

brclr staa pcsp0_lp: brclr ldaa rts

SPI0SR,SPTEF, putcspi0 SPI0DR SPI0SR,SPIF, pcsp0_lp SPI0DR

void putcspi0 (char cx) { char temp; while(!(SPI0SR & SPTEF)); SPI0DR = cx; while(!(SPI0SR & SPIF)); temp = SPI0DR; }

; wait until write operation is permissible ; output the character to SPI0 ; wait until the byte is shifted out ; clear the SPIF flag

/* wait until write is permissible */ /* output the byte to the SPI */ /* wait until write operation is complete */ /* clear the SPIF flag */

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Function putsSPI0 ; the string to be output is pointed to by X putsspi0: ldaa 1,x+ ; get one byte to be output to SPI port beq doneps0 ; reach the end of the string? jsr putcspi0 ; call subroutine to output the byte bra putsspi0 ; continue to output doneps0: rts

void putsspi0(char *ptr) { while(*ptr) { /* continue until all characters have been output */ putcspi0(*ptr); ptr++; } }

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Function getcSPI0 ; This function reads a character from SPI0 and returns it in accumulator A getcspi0: brclr staa gcsp0_lp: brclr ldaa rts

SPI0SR,SPTEF, getcspi0 SPI0DR SPI0SR,SPIF, gcsp0_lp SPI0DR

char getcspi0(void) { while(!(SPI0SR & SPTEF)); SPI0DR = 0x00; while(!(SPI0SR & SPIF)); return SPI0DR; }

; wait until write operation is permissible ; trigger eight clock pulses for SPI transfer ; wait until a byte has been shifted in ; return the byte in A and clear the SPIF flag

/* wait until write is permissible */ /* trigger 8 SCK pulses to shift in data */ /* wait until a byte has been shifted in */ /* return the character */

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Function getsSPI0 ; This function reads a string from the SPI and store it in a buffer pointed to by X ; The number of bytes to be read in passed in accumulator B getsspi0:

donegs0:

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tstb beq jsr staa decb bra clr rts

donegs0 getcspi0 1,x+ getsspi0 0,x

; check the byte count ; return when byte count is zero ; call subroutine to read a byte ; save the returned byte in the buffer ; decrement the byte count ; terminate the string with a NULL character

void getsspi0(char *ptr, char count) { while(count) { /* continue while byte count is nonzero */ *ptr++ = getcspi0(); /* get a byte and save it in buffer */ count--; } *ptr = 0; /* terminate the string with a NULL */ } Material from or based on: The HCS12/9S12: An Introduction to Software & Hardware Interfacing, Thomson Delmar Learning, 2006.

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SPI ICs: The HC595 Shift Register • The HC595 consists of an 8-bit shift register and a D-type latch with three-state parallel output. • The shift register provides parallel data to the latch. • The maximum data shift rate is 100 MHz (Philips part). DS

15

14

Shift register SC

11

Reset 10 12 LC 13 OE

Latch

1 2 3 4 5 6 7

9

QA QB QC QD QE QF QG QH

SQH

VCC = Pin 16 GND = Pin 8

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Figure 10.11 The 74HC595 block diagram and pin assignment Material from or based on: The HCS12/9S12: An Introduction to Software & Hardware Interfacing, Thomson Delmar Learning, 2006.

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Signal Pins of the HC595 • DS: serial data input • SC: shift clock. A low-to-high transition on this pin causes the data at the serial input pin to be shifted into the 8-bit shift register. • Reset: A low on this pin resets the shift register portion of this device. • LC: latch clock. A low-to-high transition on this pin loads the contents of the shift register into the output latch. • OE: output enable. A low on this pin allows the data from the latches to be presented at the outputs. • QA to QH: tri-state latch output • SQH: the output of the eight stage of the shift register

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Applications of the HC595 (1 of 2) • The HC595 is often used to add parallel ports to the microcontroller. • Both the connection methods shown in Figure 10.9 and 10.10 can be used to add parallel ports to the MCU.

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Example 10.5

•

Example 10.5 Describe how to use two 74HC595s to drive eight common cathode seven-segment displays assuming that the E clock frequency of the HCS12 is 24 MHz. Solution: Use the circuit in figure 10.12 to connect two 74HC595s to the HCS12. 5V #7

300 

reset OE 74HC595

QG QF . . . QA

DS SC LC SQH

MOSI0 SCK0 PK7

HCS12

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300 

. . .

. . . . . .

a b

g

. . . g

. . .

g

common cathode

common cathode

common cathode

R 2N2222 R

SC

Q. G LC . . OE QA

#0

a b

5V reset DS QH

#6

a b

. . .

2N2222

R

74HC595 Material from or based on: The HCS12/9S12: An Introduction to Software & Hardware Figure 10.12 Two 74HC595s together drive eight2006. seven-segment displays Interfacing, Thomson Delmar Learning,

IMAX = 70 mA

•

2N2222

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ASM Program to display 87654321 on display #7 to #0 (1 of 2) #include .org dispTab: icnt: .text _main::

forever: loop:

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“c:\miniide\hcs12.inc" $1000 .byte $80,$7F,$40,$70,$20,$5F,$10,$5B .byte $08,$33,$04,$79,$02,$6D,$01,$30 .blkb 1 ; loop count

lds bset jsr ldx movb ldaa jsr ldaa jsr bclr bset ldy jsr dec bne bra

#$3C00 DDRK,$80 openspi0 #dispTab #8,icnt 1,x+ putcspi0 1,x+ putcspi0 PTK,BIT7 PTK,BIT7 #1 delayby1ms icnt loop forever

; set up stack pointer ; configure the PK7 pin for output ; configure SPI0 ; use X as a pointer to the table ; set loop count to 8 ; send the digit select byte to the 74HC595 ; " ; send segment pattern to 74HC595 ; " ; transfer data from shift register to output ; latch ; display the digit for one ms ; " ; ; if not reach digit 1, then next ; start from the start of the table


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ASM Program to display 87654321 on display #7 to #0 (2 of 2) openspi0:

#include #include

movb #0,SPI0BR movb #$50,SPI0CR1 movb #$02,SPI0CR2 movb #0,WOMS rts "c:\miniide\delay.asm" "c:\miniide\spi0util.asm"

; set baud rate to 12 MHz ; disable interrupt, enable SPI, SCK idle low, ; latch data on rising edge, transfer data msb first ; disable bidirectional mode, stop SPI in wait mode ; enable Port S pull-up

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C Program #include “c:\egnu091\include\hcs12.h” #include “c:\egnu091\include\spi0util.c” #include “c:\egnu091\include\delay.c” void openspi0(void); void main (void) { unsigned char disp_tab[8][2] = {{0x80,0x7F},{0x40,0x70},{0x20,0x5F},{0x10,0x5B}, {0x08,0x33},{0x04,0x79},{0x02,0x6D},{0x01,0x30}}; char i; openspi0(); /* configure the SPI0 module */ DDRK |= BIT7; /* configure pin PK7 as output */ while(1) { for (i = 0; i < 8; i++) { putcspi0(disp_tab[i][0]); /* send out digit select value */ putcspi0(disp_tab[i][1]); /* send out segment pattern */ PTK &= ~BIT7; /* transfer values to latches of 74HC595s */ PTK |= BIT7; /* " */ delayby1ms(1); /* display a digit for 1 ms */ } } ECE 4510 36 } Material from or based on: The HCS12/9S12: An Introduction to Software & Hardware Interfacing, Thomson Delmar Learning, 2006.

The TC72 Digital Thermometer • • • • •

10-bit resolution and SPI interface Pin assignment and block diagram shown in Figure 10.13. Capable of reading temperature from -55oC to 125oC. Can be used in continuous temperature conversion or one-shot conversion mode. Has internal clock generator to control the automatic temperature conversion sequence VDD

NC 1 CE

2

SCK 3 GND 4

8 VDD TC72

7 NC 6 SDI 5 SDO

Internal diode temperature sensor 10-bit sigma Delta A/D converter temperature register GND

TC72

Manufacturer ID register

Serial Port Interface

CE SCK SDO SDI

Control Register

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37 pin assignmentAnand functional block diagram MaterialFigure from or10.13 basedTC72 on: The HCS12/9S12: Introduction to Software & Hardware Interfacing, Thomson Delmar Learning, 2006.

Temperature Data Format • • • • •

Temperature is represented by a 10-bit two’s complement word with a resolution of 0.25oC per least significant bit. The converter is scaled from -128oC to +127oC with 0oC represented as 0x0000. The temperature value is stored in two 8-bit registers. Whenever the most significant bit is 1, the temperature is negative. A sample of temperature reading is shown. Table 10.3 TC72 Temperature output data Binary high byte/low byte 0010 0100 0001 0000 0000 1111 1111 1110 1100

0001/0100 1010/1000 1010/1100 0001/1000 0000/0000 1111/1000 0010/1100 0111/0000 1001/0100

0000 0000 0000 0000 0000 0000 0000 0000 0000

Hex

Temperature

2140 4A80 1AC0 0180 0000 FF80 F2C0 E700 C900

33.25 oC 74.5 o C 26.75 oC 1.5 o C 0 oC -0.5o C -13.25 o C -24 o C -55 o C

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TC72’s Serial Interface • • • • • • •

The CE input to the TC72 must be asserted (high) to enable SPI transfer. Data can be shifted on the rising edge or the falling edge depending on the idle polarity of the SCK source. Data transfer to and from the TC72 consists of one address byte followed by one or multiple data (2 to 4) bytes. The TC72 registers and their addresses are shown in Table 10.4. The most significant bit of the address byte determines whether a read (A7 = 0) or a write (A7 = 1) operation will occur. A multiple byte read operation will start from high address toward lower addresses. The user can send in the temperature result high byte address and read the temperature result high byte, low byte, and the control registers. Table 10.4 Register for TC72 Register Control LSBtemperature MSBtemperature ManufacturerID

Read Write address address 0x00 0x01 0x02 0x03

0x80 N/A N/A N/A

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0 T1 T9 0

0 T0 T8 1

0 0 T7 0

OS 0 T6 1

0 0 T5 0

0 0 T4 1

0 SHDN 0 0 T3 T2 0 0

Note. 1. OS is One-Shot 2. SHDN is Shutdown ECE 4510 Material from or based on: The HCS12/9S12: An Introduction to Software & Hardware Interfacing, Thomson Delmar Learning, 2006.

Value on POR/BOR 0x05 0x00 0x00 0x54 39

Procedure for Reading Temperature (1 of 2) •

Step 1 – Pull the CE pin high to enable SPI transfer.

•

Step 2 – Send the temperature result high byte read address (0x02) to the TC72. Wait until the SPI transfer is complete.

•

Step 3 – Read the temperature result high byte. The user needs to write a dummy byte into the SPI data register to trigger eight clock pulses.

•

Step 4 – Read the temperature result low byte. Again, the user needs to write a dummy byte into the SPI data register to trigger eight clock pulses.

•

Step 5 – Pull CE pin to low so that a new transfer can be started.

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Procedure for Reading Temperature (2 of 2) CE 1

2

3

4

5

6

7

8

A 5

A 4

A 3

A 2

A 1

A 0

9

10

11

12

13

14

15

16

D 7

D 6

D 5

D 4

D 3

D 2

D 1

D 0

SCK A7 = 0 SDI

A 7

A 6

High Z

SDO

high Z

Figure 10.15b Single data byte read operation CE Write operation SCK Read operation Address byte = 0x02 SDI SDO

A 7

A 0 D 7

D 0

D 7

D 0

D 7

D 0

Figure 10.15c SPI multiple data byte transfer

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Control Register • • • • • •

The control register is used to select the shutdown, continuous, or one-shot conversion operating mode. The temperature conversion mode selection logic is shown in Table 10.5. At power up, the SHDN bit is 1. Thus the TC72 is in the shutdown mode. If the SHDN bit is 0, the TC72 will perform a temperature conversion approximately every 150 ms. A temperature conversion will be initiated by a write operation into the control register to select the continuous mode or one-shot mode. A typical circuit connection between the TC72 and the HCS12 is shown in Figure 10.16. Table 10.5Control register temperatureconversionmodeselection Operationmode

One-Shotbit

Shutdown bit

Continuoustemperatureconversion Shutdown Continuoustemperatureconversion One-shot

0 0 1 1

0 1 0 1

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Example 10.6: Reading Temp. • Write a C program to read the temperature every 200 ms. Convert the temperature to a string so that it can be displayed in an appropriate output device. A pointer to hold the string will be passed to this function. The bus clock is 24 MHz. TC72 VDD

HCS12 MCU

VDD CE

0.1F

PK7

SCK

SCK0

SDO

MISO0

SDI

MOSI0

GND

Figure 10.16 Circuit connection between the TC72 and the HCS12

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C Code (1 of 4)

ECE 4510

#include “c:\egnu091\include\hcs12.h” #include “c:\egnu091\include\spi0util.c” #include “c:\egnu091\include\delay.c” #include “c:\egnu091\include\convert.c” void read_temp (char *ptr); void openspi0(void); char buf[10]; void main (void) { DDRM |= BIT1; /* configure the PM1 pin for output */ openspi0(); /* configure SPI0 module */ read_temp(&buf[0]); } void openspi0(void) { SPI0BR = 0x10; /* set baud rate to 6 MHz */ SPI0CR1 = 0x50; /* enable SPI0 to master mode, select rising edge to shift data in and out */ SPI0CR2 = 0x02; /* select normal mode and stop SPI in wait mode */ WOMS = 0x00; /* enable Port S pull-up */ 44 } Material from or based on: The HCS12/9S12: An Introduction to Software & Hardware Interfacing, Thomson Delmar Learning, 2006.

C Code (2 of 4) void read_temp (char *ptr) { char hi_byte, lo_byte, temp, *bptr; unsigned int result; bptr = ptr; PTM |= BIT1; /* enable TC72 data transfer */ putcspi0(0x80); /* send out TC72 control register write address */ putcspi0(0x11); /* perform one shot conversion */ PTM &= ~BIT1; /* disable TC72 data transfer */ delayby100ms(2); /* wait until temperature conversion is complete */ PTM |= BIT1; /* enable TC72 data transfer */ putcspi0(0x02); /* send MSB temperature read address */ hi_byte = getcspi0(); /* read the temperature high byte */ lo_byte = getcspi0(); /* save temperature low byte and clear SPIF */ PTM &= ~BIT1; /* disable TC72 data transfer */

ECE 4510

lo_byte &= 0xC0; /* make sure the lower 6 bits are 0s */ result = (int) hi_byte * 256 + (int) lo_byte; if (hi_byte & 0x80) { /* temperature is negative */ result = ~result + 1; /* take the two' complement of result */ result >>= 6; Material from or based on: The HCS12/9S12: An Introduction to Software & Hardware Interfacing, Thomson Delmar Learning, 2006.

45

C Code (3 of 4) temp = result & 0x0003; /* place the lowest two bits in temp */ result >>= 2; /* get rid of fractional part */ *ptr++ = 0x2D; /* store the minus sign */ int2alpha(result, ptr);

ECE 4510

} else { /* temperature is positive */ result >>= 6; temp = result & 0x0003; /* save fractional part */ result >>= 2; /* get rid of fractional part */ int2alpha(result, ptr); /* convert to ASCII string */ } while(*bptr){ /* search the end of the string */ bptr++; }; switch (temp){ /* add fractional digits to the temperature */ case 0: break; case 1: /* fractional part is .25 */ *bptr++ = 0x2E; /* add decimal point */ *bptr++ = 0x32; *bptr++ = 0x35; *bptr = '\0'; Material from or based on: The HCS12/9S12: An Introduction to Software & Hardware break; Interfacing, Thomson Delmar Learning, 2006.

46

C Code (4 of 4) case 2: /* fractional part is .5 */ *bptr++ = 0x2E; /* add decimal point */ *bptr++ = 0x35; *bptr = '\0'; break; case 3: /* fractional part is .75 */ *bptr++ = 0x2E; /* add decimal point */ *bptr++ = 0x37; *bptr++ = 0x35; *bptr = '\0'; break; default: break; } }

ECE 4510


ECE 4510 Introduction to Microprocessors Chapter 10

ECE 4510 Introduction to Microprocessors Chapter 10

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