in… I want to specialize primarily in… VLSI. Digital Systems Design. ASICs &
FPGAs. VHDL/Verilog. CAD Tools. Reconfigurable. Computing. Microelectronics.
Kris Gaj
ECE 545
Research and teaching interests: • reconfigurable computing • computer arithmetic • cryptography • network security
Digital System Design with VHDL Course web page:
Contact:
ECE web page → Courses → Course web pages → ECE 545
The Engineering Building, room 3225
[email protected]
http://ece.gmu.edu/coursewebpages/ECE/ECE545/F11/
Office hours: Thursday, 7:30-8:30 PM, Tuesday, 6:00-7:00 PM, and by appointment
ECE 545
ECE 545
Part of:
Part of:
MS in Computer Engineering
PhD in Electrical and Computer Engineering
One of five core courses (must be passed with B or better) Strongly suggested for two specialization areas:
Knowledge tested at the Technical Qualifying Exam (TQE) Topic 2: Digital Design and Computer Organization
Digital Systems Design Microprocessor and Embedded Systems Elective course in the remaining specialization areas
MS in Electrical Engineering Elective
ECE 545 Class of Fall 2011 MS SE NDG 1 2 PhD ECE MS CpE 1 6 MS EE 8 • 18 students total • 7 admitted in Fall 2011 • 5 admitted in Spring 2011
I am interested in…
I want to specialize primarily in… CAD tools & Design Automation
VLSI
Hardware Description Languages
Recommended program & specialization MS CpE Digital Systems Design
Digital Systems Design FPGAs & Reconfigurable computing ASICs & FPGAs
Computer Arithmetic
VHDL/Verilog
Front-end ASIC Design (algorithmic downto gate level)
CAD Tools Reconfigurable Computing
Back-end ASIC Design (circuit and mask layout levels) Analog & Digital Circuit Design
Microelectronics
VLSI Fabrication
VLSI Fabrication
Microelectronics
Nanoelectronics
Nanoelectronics Semiconductor Devices
MS EE Microelectronics/ Nanoelectronics
1
Courses
Design level Digital System Computer Design with VHDL Arithmetic
CpE
VLSI Design VLSI Test for ASICs Concepts
Digital Systems Design
algorithmic ECE 645
ECE 545
register-transfer gate
ECE 586
transistor layout devices
ECE 680
Digital Integrated Circuits
Physical VLSI Design Semiconductor ECE 584 ECE684 Device Fundamentals
PreApproved Electives
ECE 545 Digital System Design with VHDL ECE 645 Computer Arithmetic ECE 681 VLSI Design for ASICs ECE 682 VLSI Test Concepts ECE 586 Digital Integrated Circuits
Suggested Electives
CS 540, 583 (languages, algorithms) CS 635 (parallel machines) ECE 584, 684, … (technology) ECE 511, 611, … (microprocessors) ECE 542, 642, 742 (networks) ECE 645, 681 (digital design) ECE 646, 746, … (applications) ECE 548 (sequential mach. theory)
Professors
K. Gaj, J. Kaps, T. Storey, T.K. Ramesh
ECE 682
ECE 681
MOS Device Electronics
CpE Microprocessors and Embedded Systems
DIGITAL SYSTEMS DESIGN
ECE 511 Microprocessors ECE 545 Digital System Design with VHDL ECE 611 Advanced Microprocessors ECE 612 Real-Time Embedded Systems
J. Kaps, K. Gaj, D. Tabak, C. Sabzevari
Grading Scheme
Concentration advisors: Kris Gaj, Jens-Peter Kaps, Ken Hintz 1. ECE 545 Digital System Design with VHDL – K. Gaj, project, FPGA design with VHDL, Aldec/Mentor Graphics, Xilinx/Altera 2. ECE 645 Computer Arithmetic – K. Gaj, project, FPGA design with VHDL Aldec/Mentor Graphics, Xilinx/Altera 3. ECE 681 VLSI Design for ASICs – T.K. Ramesh, project/lab, front-end and back-end ASIC design with Synopsys tools
• Homework
-
10%
• Project
-
40%
• Midterm Exam
-
20%
• Final Exam
-
30%
4. ECE 586 Digital Integrated Circuits – D. Ioannou, R. Mulpuri, 5. ECE 682 VLSI Test Concepts – T. Storey
Midterm exam 1
Final exam
2 hours 30 minutes
2 hours 45 minutes
in class
in class
design-oriented
design-oriented
open-books, open-notes
open-books, open-notes
practice exams available on the web
practice exams available on the web
Tentative date: Thursday, October 27th
Date: Monday, December 15, 4:30-7:15pm
2
Required Textbook Pong P. Chu, RTL Hardware Design Using VHDL, Wiley-Interscience, 2006.
Textbooks
13
Supplementary Textbook – Basics Refresher
Supplementary Textbook – Advanced Hubert Kaeslin, Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication, Cambridge University Press; 1st Edition, 2008.
Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, McGraw-Hill, 3rd or 2nd Edition
Used in ECE 681 “VLSI Design for ASICs”
What is an FPGA? Configurable Logic Blocks Block RAMs
Block RAMs
Technology & Tools
I/O Blocks Block RAMs
17
3
Two competing implementation approaches ASIC Application Specific Integrated Circuit
FPGA Field Programmable Gate Array
• designed all the way from behavioral description to physical layout
• no physical layout design; design ends with a bitstream used to configure a device
• designs must be sent for expensive and time consuming fabrication in semiconductor foundry
• bought off the shelf and reconfigured by designers themselves
FPGA Design process (1) Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds…..
Specification / Pseudocode
FPGAs vs. ASICs ASICs High performance
FPGAs Off-the-shelf Low development costs
Low power Short time to the market Low cost (but only in high volumes)
Reconfigurability
FPGA Design process (2) Implementation Timing simulation
On-paper hardware design (Block diagram & ASM chart) VHDL description (Your Source Files) Library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
Functional simulation
Configuration On chip testing
entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; ); end AES_core;
Synthesis
Post-synthesis simulation
Simulation Tools
4
FPGA Synthesis Tools
Logic Synthesis VHDL description architecture MLU_DATAFLOW of MLU is signal A1:STD_LOGIC; signal B1:STD_LOGIC; signal Y1:STD_LOGIC; signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;
Circuit netlist
FPGA Implementation • After synthesis the entire implementation process is performed by FPGA vendor tools
begin A1
