Editorial Dynamically Reconfigurable Architectures

Hindawi Publishing Corporation EURASIP Journal on Embedded Systems Volume 2007, Article ID 28405, 2 pages doi:10.1155/2007/28405

Editorial Dynamically Reconfigurable Architectures ¨ Neil Bergmann,1 Marco Platzner,2 and Jurgen Teich3 1 School

of Information Technology & Electrical Engineering, The University of Queensland, Brisbane, QLD 4072, Australia of Computer Science, University of Paderborn, 33095 Paderborn, Germany 3 Department of Computer Science, University of Erlangen-Nuremberg, 91058 Erlangen, Germany 2 Department

Received 8 January 2007; Accepted 8 January 2007 Copyright © 2007 Neil Bergmann et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

As integrated circuit line widths continue to shrink, there is a corresponding increase in the capital costs of microelectronic fabrication plants and in the mask making costs of individual chips. As a result, it is increasingly uneconomical to produce small and medium volume chips in the latest submicron technologies. Reconfigurable logic circuits, such as FPGAs (field programmable gate arrays) and coarse-grained processor arrays, allow a single mask-level design to be configured for many different applications, so improving the production volumes and economic viability of the mask-level design. However, configurability comes at a cost—the area of a configurable circuit is often larger, the power consumption is greater, and the speed is slower than a full-custom circuit. Such configurable circuits become much more attractive if the same logic substrate can be reconfigured and reused for different functions during different phases of an application. Such systems, where the configurable circuit structures are changed during circuit operation, are called dynamically reconfigurable architectures. In April 2006, the fourth workshop in a series of workshops on the topic of dynamically reconfigurable architectures (DRAs) was held at the Internationales Begegnungsund Forschungszentrum f¨ur Informatik (International Conference and Research Center for Computer Science) at Schloss Dagstuhl in Germany. The workshop attendees were invited to submit extended versions of their workshop presentations for consideration for this special issue, and after a peer review process, seven papers were accepted for publication. The workshop provided participants with an opportunity to review the history of DRAs, to present a summary of their current work, and to explore the challenges and opportunities that these architectures will present in the future. These seven papers in the special issue reflect this diversity. Some papers present a consolidated summary of a large body

of work, others look at technologies that will support future generations of reconfigurable circuits. One of the key problems in DRAs is how to design circuit components that can be swapped in and out of a system. In the first paper, “Prerouted FPGA cores for rapid system construction in a dynamic reconfigurable system,” T. Oliver and D. Maskell look at how to build FPGA-based processing cores suitable for use in DRAs. In the second paper, “Efficient integration of pipelined IP blocks into automatically compiled datapaths,” Andreas Koch looks at how to combine manually optimised IP blocks with automatically compiled modules. Another area of active interest in DRAs is identification of suitable application domains in which dynamic reconfiguration can be used to advantage. In the third paper, “Using simulated partial dynamic run time reconfiguration to share embedded FPGA compute and power resources across a swarm of unpiloted airborne vehicles,” D. Kearney and M. Jasiunas investigate how dynamic reconfiguration can be used to move computations within a cooperating cluster of autonomous vehicles so as to make best use of available electrical energy and available computing power. In the fourth paper, “Efficient architectures for streaming DSP applications,” Gerard Smit et al. present their work on DRAs which are especially suited to streaming digital signal processing applications. In the fifth paper, “A high-end real-time digital film processing reconfigurable platform,” Sven Heithecker et al. present a specialised DRA platform for high-performance digital image processing. Future widespread adoption of DRA technology is likely to depend on both computational and communications capabilities of DRA systems. In the sixth paper, “Examining the viability of FPGA supercomputing,” S. Craven and P. Athanas analyse how FPGAs’ computational ability compares with traditional processors, particularly in the domain of supercomputing applications. In the final paper, “Characterization

2

EURASIP Journal on Embedded Systems

of a reconfigurable free-space optical channel for embedded computer applications with experimental validation using rapid prototyping technology,” Rafael Gil-Otero et al. investigate optical technologies which will provide future DRAs with high-speed communication abilities to match their enormous computational abilities. Together, these papers provide an excellent snapshot of the latest research directions in dynamically reconfigurable architectures—we hope you find them useful and informative. Neil Bergmann Marco Platzner J¨urgen Teich

Photographȱ©ȱTurismeȱdeȱBarcelonaȱ/ȱJ.ȱTrullàs

Preliminaryȱcallȱforȱpapers

OrganizingȱCommittee

The 2011 European Signal Processing Conference (EUSIPCOȬ2011) is the nineteenth in a series of conferences promoted by the European Association for Signal Processing (EURASIP, www.eurasip.org). This year edition will take place in Barcelona, capital city of Catalonia (Spain), and will be jointly organized by the Centre Tecnològic de Telecomunicacions de Catalunya (CTTC) and the Universitat Politècnica de Catalunya (UPC). EUSIPCOȬ2011 will focus on key aspects of signal processing theory and applications li ti as listed li t d below. b l A Acceptance t off submissions b i i will ill be b based b d on quality, lit relevance and originality. Accepted papers will be published in the EUSIPCO proceedings and presented during the conference. Paper submissions, proposals for tutorials and proposals for special sessions are invited in, but not limited to, the following areas of interest.

Areas of Interest • Audio and electroȬacoustics. • Design, implementation, and applications of signal processing systems. • Multimedia l d signall processing and d coding. d • Image and multidimensional signal processing. • Signal detection and estimation. • Sensor array and multiȬchannel signal processing. • Sensor fusion in networked systems. • Signal processing for communications. • Medical imaging and image analysis. • NonȬstationary, nonȬlinear and nonȬGaussian signal processing.

Submissions Procedures to submit a paper and proposals for special sessions and tutorials will be detailed at www.eusipco2011.org. Submitted papers must be cameraȬready, no more than 5 pages long, and conforming to the standard specified on the EUSIPCO 2011 web site. First authors who are registered students can participate in the best student paper competition.

ImportantȱDeadlines: P Proposalsȱforȱspecialȱsessionsȱ l f i l i

15 D 2010 15ȱDecȱ2010

Proposalsȱforȱtutorials

18ȱFeb 2011

Electronicȱsubmissionȱofȱfullȱpapers

21ȱFeb 2011

Notificationȱofȱacceptance SubmissionȱofȱcameraȬreadyȱpapers Webpage:ȱwww.eusipco2011.org

23ȱMay 2011 6ȱJun 2011

HonoraryȱChair MiguelȱA.ȱLagunasȱ(CTTC) GeneralȱChair AnaȱI.ȱPérezȬNeiraȱ(UPC) GeneralȱViceȬChair CarlesȱAntónȬHaroȱ(CTTC) TechnicalȱProgramȱChair XavierȱMestreȱ(CTTC) TechnicalȱProgramȱCo Technical Program CoȬChairs Chairs JavierȱHernandoȱ(UPC) MontserratȱPardàsȱ(UPC) PlenaryȱTalks FerranȱMarquésȱ(UPC) YoninaȱEldarȱ(Technion) SpecialȱSessions IgnacioȱSantamaríaȱ(Unversidadȱ deȱCantabria) MatsȱBengtssonȱ(KTH) Finances MontserratȱNájarȱ(UPC) Montserrat Nájar (UPC) Tutorials DanielȱP.ȱPalomarȱ (HongȱKongȱUST) BeatriceȱPesquetȬPopescuȱ(ENST) Publicityȱ StephanȱPfletschingerȱ(CTTC) MònicaȱNavarroȱ(CTTC) Publications AntonioȱPascualȱ(UPC) CarlesȱFernándezȱ(CTTC) IIndustrialȱLiaisonȱ&ȱExhibits d i l Li i & E hibi AngelikiȱAlexiouȱȱ (UniversityȱofȱPiraeus) AlbertȱSitjàȱ(CTTC) InternationalȱLiaison JuȱLiuȱ(ShandongȱUniversityȬChina) JinhongȱYuanȱ(UNSWȬAustralia) TamasȱSziranyiȱ(SZTAKIȱȬHungary) RichȱSternȱ(CMUȬUSA) RicardoȱL.ȱdeȱQueirozȱȱ(UNBȬBrazil)