Editorial Introduction To The Special Section On Petri ... - IEEE Xplore

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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 11, NO. 3, AUGUST 1998

Editorial Introduction to the Special Section on Petri Nets in Semiconductor Manufacturing

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OR THE PAST three decades, the theory of Petri nets (PN’s) has been developed into a powerful tool for the modeling, design, analysis, planning, scheduling, control, and implementation of manufacturing systems. These systems can be characterized as discrete event systems (DES) that may exhibit such features as concurrency, asynchrony, nondeterminism, mutual exclusion, resource sharing, deadlocks, routing flexibility and lot sizes. Semiconductor manufacturing systems are complex DES. Their complexity owes to the complicated semiconductor production and test procedures, and the large number of resources shared in the systems. PN’s have gained more and more attentions in semiconductor manufacturing due to their graphical and mathematical advantages over traditional tools to deal with discrete-event dynamics and characteristics of complex systems. This special section aims to present some of significant current results in the use of PN’s in semiconductor manufacturing system design and automation. Four papers and three briefs are selected in the section. For readers not familiar with PN’s, the first paper “Modeling, Analysis, Simulation, Scheduling, and Control of Semiconductor Manufacturing Systems: A Petri Net Approach” by ourselves serves as a tutorial paper. It reviews applications of PN’s in semiconductor manufacturing automation. Fundamental definitions and concepts of PN’s are introduced. It proceeds to discuss the use of modules and a general method for constructing a system model. The method is demonstrated through an AT&T FWS-200 flexible workstation for producing printed circuit boards. Next, important PN properties and their implications in semiconductor manufacturing, and analysis methods are presented. Timed PN’s are introduced for simulation, performance evaluation, and scheduling purposes. An application-oriented case study of the photolithography area in a real-world IC wafer fabrication system is presented to demonstrate the effectiveness of PN’s for significant applications. The tutorial paper concludes with the active research areas and future research directions in applying PN’s to design of semiconductor manufacturing systems. The second paper, “Modeling, Qualitative Analysis, and Performance Evaluation of the Etching Area in an IC Wafer Fabrication System Using Petri Nets” by Jeng, Xie, and Chou presents a project of applying PN’s to modeling and analysis of a real-world system. Several generic modules are proposed Publisher Item Identifier S 0894-6507(98)05875-8.

to capture important characteristics of wafer manufacturing and serves as a basis to construct a complex system model in a systematic fashion. Based on them, a modular approach is presented and illustrated through PN modeling of the etching area of an industrial IC wafer fabrication system. A theory on analyzing its qualitative properties is presented. Performance of the target area is evaluated by simulation. The system model is validated quantitatively by comparing simulated and real machine utilization. The model is used to answer “whatif” questions, e.g., the maximal throughput and bottleneck machines are predicted when the modeled resources change in their quantity and operational speeds. Allam and Alla in “Modeling and Simulation of an Electronic Component Manufacturing System Using Hybrid Petri Nets” propose hybrid PN’s as an approximation of “discrete” PN’s to tackle the state explosion problem in analyzing largescale semiconductor manufacturing systems. First, hybrid PN’s are presented intuitively with a simple production system with batches. By comparing discrete and hybrid PN’s for modeling this system, the paper shows that the latter approximates the former well and can save significant simulation time. Next, a generalized timed marked hybrid PN is formally defined. It is applied to an assembly-test workshop of electronic components that is characterized by a high throughput and a unique routing of different components. Simulation results of average buffer levels and production rates are presented. The fourth paper, “Scheduling of Semiconductor Test Facility via Petri Nets and Hhybrid Heuristic Search” by Xiong and Zhou presents two PN-based heuristic search strategies, called hybrid BF-BT and hybrid BT-BF, for scheduling semiconductor test facility. The strategies are proposed to cope with the complexity of multiple lots scheduling by combining best first search and backtracking search. Hybrid BF-BT begins with best-first search until a depth bound is reached. Then backtracking search is adopted using the best present marking as a starting node. If failing to find a solution, it returns to obtain the second best marking and continues. As an opposite approach, hybrid BT-BF starts backtracking search followed best first search. From simulation results, the paper concludes that the latter performs much better than the former. Application of hybrid BT-BF to a complex facility of wafer sort and final test is shown. The first brief, “Modeling and Performance Analysis of Cluster Tools Using Petri Nets,” by Srinivasan proposes a

0894–6507/98$10.00  1998 IEEE

JENG AND ZHOU: EDITORIAL

method, called state cycle analysis, to analyze throughput performance of cluster tools. These tools are gaining everincreasing importance as the semiconductor industry migrates to larger wafer sizes and small device geometry. Janneck and Naedele in “Modeling a Die Bonder with Petri Nets: a case study” present a tool called CodeSign that allows object oriented design and simulation of high-level timed PN models. It is used to model and analyze a die bonder in the IC packaging process. The developed model is compared with a previous spreadsheet model in four configurations with actual measurements on the machine. The results show that a prediction error obtained from CodeSign is smaller than that from the spreadsheet model. The final brief “Modeling and Emulation of a Furnace in IC Fab Based on Coloredtimed Petri Net” by Lin and Huang proposes the use of hierarchical colored-timed Petri nets (CTPN) to model furnaces. It presents the CTPN model of a furnace and an emulation environment. The performance of a furnace can be easily tested via emulation without its actual installation.

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We would like to thank all the anonymous reviewers who helped improve the special section papers and briefs in both their technical and presentation aspects. We would also thank all the authors (including those whose papers cannot be included) who contributed to this section and had to work on their revisions under a very tight publication schedule. Finally, we would like to thank the Editor, Dr. Gary S. May, and the editorial board for their approval of and great support to this special section.

MU DER JENG, Guest Editor Department of Electrical Engineering National Taiwan Ocean University Keelung 202, Taiwan, R.O.C. MENGCHU ZHOU, Guest Editor Department of Electrical and Computer Engineering New Jersey Institute of Technology Newark, NJ 07102-1982 USA

Mu Der Jeng (S’89–M’92–SM’96) received the B.S. and M.S. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1983 and 1985, respectively, and the Ph.D. degree in computer and systems engineering from Rensselaer Polytechnic Institute, Troy, NY, in 1992. From 1985 to 1987, he served as a second lieutenant in the Military Intelligence Bureau of Defense Ministry, where he was involved in developing office automation and database software. From 1987 to 1988, he worked for the Institute for Information Industry as an Associate Engineer in the design of data communication products. Since August 1992, he has been an Associate Professor in the Electrical Engineering Department at National Taiwan Ocean University, Keelung. His current research interests include Petri nets, neural networks, artificial intelligent search techniques, manufacturing modeling and scheduling, planning of underwater robots, performance analysis of IC wafer fabrication systems, and multimedia systems. In the above areas, he has actively been involved in many government- and industry-funded projects. Dr. Jeng received the Franklin V. Taylor Award from the IEEE Systems, Man and Cybernetics (SMC) Society in 1993 for an outstanding paper presented at 1992 IEEE SMC International Conference. Since 1994, he has annually received Research Awards from National Science Council. He has served on the program committees of 1994, 1998 IEEE SMC International Conferences, 1997 IEEE International Conference on Emerging Technologies and Factory Automation, and the 1998 IEEE International Symposium on Industrial Electronics. He has frequently been invited to participate as session chairs and organizers for many international conferences. He is a member of Phi Tau Phi and is listed in Who’s Who in the World.

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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 11, NO. 3, AUGUST 1998

MengChu Zhou (S’88–M’90–SM’93) received the B.S. degree in computer and control engineering from East China Institute of Technology, Nanjing, in 1983, the M.S. degree in automatic control from Beijing Institute of Technology, Beijing, China in 1986, and the Ph.D. degree in computer and systems engineering from Rensselaer Polytechnic Institute, Troy, NY, in 1990. He joined the Department of Electrical and Computer Engineering at the New Jersey Institute of Technology, Newark, in 1990, and is currently Associate Professor and Director of Discrete Event Systems Laboratory. He was Assistant Engineer in the Institute for Computer Applications, Beijing, from 1986 to 1987. His research interests include computer-integrated manufacturing and networking, embedded control, discrete event systems, Petri nets and applications, and intelligent automation. He co-authored, with F. DiCesare, Petri Net Synthesis for Discrete Event Control of Manufacturing Systems (Norwell, MA: Kluwer, 1993) and edited Petri Nets in Flexible and Agile Automation (Norwell, MA: Kluwer, 1995). In addition, he has published over 110 international journal articles, book chapters, and conference proceeding papers in the above areas. Dr. Zhou has organized and chaired over 40 technical and tutorial sessions and served on program committees for many international and regional conferences. He served as the Program Chair of the 9th International Conference on CAD/CAM, Robotics, and Factories of the Future, Newark, NJ, August 1993, Vice-Chair of International Program Committee of the 1996 IEEE International Conference on Systems, Man and Cybernetics, Beijing, China, October 1996, Program Chair of the 1997 IEEE International Conference on Emerging Technologies and Factory Automation, Los Angeles, CA, September 1997, and the 1998 IEEE International Conference on Systems, Man and Cybernetics, San Diego, CA, October 1998. He served as the Co-Editor for IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS Special Section on Petri Nets in Manufacturing, serving the Guest Editor for the Journal of Intelligent Manufacturing Special Issue on Computer Integrated Manufacturing Systems: Recent Developments and Applications. He is on the Editorial Board of IEEE TRANSACTIONS ON ROBOTICS AND AUTOMATION and the International Journal of Intelligent Control and Systems. He was the recipient of NSF’s Research Initiation Award, and was listed in 1994 Computer Integrated Manufacturing LEAD Award by Society of Manufacturing Engineers. He was granted the H. J. Perlis Research Award by New Jersey Institute of Technology in 1996. He is serving as Vice President, Finance and Fund Raising, Chinese Association for Science and Technology-USA.