EE559: MOS VLSI Design

EE559 MOS VLSI Design

EE559: MOS VLSI Design I t t Instructors: K. K Roy R Email: [email protected] URL1: www.ece.purdue.edu/~kaushik Office: MSEE 232 Telephone: 494-2361 Office Hours: Tuesday/Thursday 11am-12noon or by b appointments i t t

Grading Policy • Mid-terms + quizzes + hw will account for 75% of the grade – 3 mid-terms – Mandatory and has to be taken on the scheduled day of the exam.

• Project will account for 25% of the grade. Late projects will not be accepted. • You are guaranteed an A if your weighted average score over exams, quizzes, and projects is 90 or above. • Any form of cheating will be heavily penalized and reported to the Dean of students and mayy result in a failing gg grade. • Instructor reserves right to change project requirements.

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Text and References

• Text: – Digital Integrated Circuits: A Design Perspective, J. Rabaey, Prentice Hall, Second edition

• References: – Principles of CMOS VLSI Design: A Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian, Addison Wesley – Circuits, Interconnects, and Packaging for VLSI, H. Bakoglu, Addison Wesley

• Class Notes: – http://www.ece.purdue.edu/~vlsi/ee559/20001

Conferences & Journals • • • • • • • • • • •

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IEEE Transactions on VLSI Systems IEEE Transactions on CAD of IC’s IC s IEEE Journal of Solid State Circuits IEEE VLSI Circuits Symposium Journal of Electronic Testing ACM Design Automation Conference IEEE International Conference on CAD IEEE Solid State Circuits Conference International symposium on Low-Power Electronics & Design IEEE Conference on Computer Design IEEE International Test Conference

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Course Outline • • • • •

Introduction: Historical perspective and Future Trend Semiconductor Devices CMOS Logic Logic, Layout techniques MOS devices, SPICE models Inverters: transfer characteristics, static and dynamic behavior, power and energy consumption of static MOS inverters • Designing combinational logic gates in CMOS – Static CMOS design: Complementary CMOS, ratioed logic, pass-transistor logic – Dynamic CMOS logic

Course Outline (Cont’d) • Designing combinational logic gates (Cont’d) – Power consumption p in CMOS g gates – Low-power design

• • • • •

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Designing sequential circuits Interconnect and timing issues Designing memory and array structures Designing arithmetic building blocks VLSI S testing and verification f

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VLSI CAD Lab and TA • VLSI CAD Lab located in 360 Potter Engineering Center – SUN workstations running Mentor Graphics tools – Courtesy key for after-hour access can be obtained from front desk in Potter Engineering Library – Additional workstations in MSEE 186

• Lab TA: Kuntal Roy ([email protected]) – Facilitates the use of lab design tools. – Office hours: TBA – Lab Orientation will be held in the second week

• Lab URL – http://min.ecn.purdue.edu/~mgcdevel/ee559_lab.html

Course Project • Complete design of a functional logic block or system – Complexity of 1000+ transistors or novelty – Design using the CADENCE tools and HSPICE • Design your own library from scratch

– – – – – – –

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Functionality to be verified Critical path timing should be verified using HSPICE Project report due the last day of class Project presentation by each group in the last week of class Work in a group of 2 will be allowed in special cases Start early! Emphasis on new ideas, power dissipation, performance, reconfigurability, low voltage design

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Introduction: A Historical Perspective and Future Trends References: Adapted p from: Digital g Integrated g Circuits: A Design g Perspective p , J. Rabaey © UCB Principles of CMOS VLSI Design: A Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian

Digital Computation: Particle Location is an Indicator of State 1

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1

0

0

1 0

5


Physical Medium for Computation: Barrier Model GATE

V=0

SOURCE

DRAIN

Leff

V=Vmin=Ebmin

Tox

Vg

Eb

Vd

1. Can we operate with Vmin ~ KBTln2 ? 2. Can we operate with Qmin = q ?

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The First Computer

• The Babbage g Differential Engine (1834) • 25,000 mechanical parts • Cost £17,470

Digital Electronic Computing • Started with the introduction of vacuum tube • ENIAC for computing artillery firing tables in 1946 • Integration density – 80 feet long, 8.5 feet high, and several feet wide – 18,000 vacuum tubes

• Reliability issues and excessive power consumption • Did not go far until the invention of the transistor at Bell Lab in 1947

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HISTORY • MOS field-effect transistor: Lilienfeld (1925), Heil (1935) • Bipolar transistors: Bardeen (1947), Schockley (1949) • First Bipolar digital logic: Harris (1956) – IC Logic family: • Transistor-Transistor Logic (TTL) (1962) • Emitter-Coupled Logic (ECL) (1971) • Integrated Injection Logic (I2L) (1972)

• PMOS and NMOS transistors on the same substrate: Weimer ((1962), ), Wanlass (1965) ( ) • PMOS-only logic until 1971 when NMOS technology emerged • NMOS-only logic until late 1970s, when CMOS technology took over • Later developments: BiCMOS, GaAs, low-temperator CMOS, super-conducting technologies, Nano-electronic

Exponential Increase in Leakage 1970

1980

5 µm

2000

2020

100 nm

1 µm

10 nm

Silicon Nano- electronics

Non Silicon Non-Silicon Technology

I ON = 106 I OFF

I ON = 103 I OFF

I ON ~ 102~6 I OFF

S Source

Drain

n+

n+ Junction leakage Bulk

Leakage Power (% % of Total)

Silicon Micro- electronics

Subthreshold Gate Leakage Leakage Gate

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2010

50%

Must stop at 50%

40% 30% 20% 10% 0%

A. Grove, IEDM 2002

1.5

0.7

0.35 0.18 0.09 0.05

Technology (μ)

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Technology Trend

Nano devices

Fully-depleted body VG

Bulk-CMOS

Gate

Carbon nanotube III-V devices nano-wires Spintronics

DGMOS

Buried Oxide (BOX)

VD

Gate

VD Drain

Source

VG VS

VS

Substrate Source Floating Body

Drain

Vback

FD/SOI

Buried Oxide (BOX)

FinFET

Substrate

Trigate

PD/SOI

Single gate device

Multi-gate devices

Design methods to exploit the advantages of technology innovations

The Scale of Things – Nanometers and More Things Natural

Things Manmade 10-2 m

Ant ~ 5 mm

Dust mite

Red blood cells with white cell ~ 2-5 μm

The Challenge

1,000,000 nanometers = 1 millimeter (mm) MicroElectroMechanical (MEMS) devices 10 -100 μm wide

10-44 m

00.11 mm 100 μm

10-5 m

0.01 mm 10 μm Infrared

Fly ash ~ 10-20 μm

Microworld

200 μm

Human hair ~ 60-120 μm wide

Head of a pin 1-2 mm

Microwave

10-3 m

1 cm 10 mm

1,000 nanometers = 1 micrometer (μm)

Pollen grain Red blood cells

P

O O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

S

S

S

S

S

O

S

O

S

S

Zone plate x-ray “lens” Outer ring spacing ~35 nm

Visible

10-6 m

O

O

O

Smaller is different!

~10 nm diameter

10-8 m

Fabricate and combine nanoscale building blocks to make useful devices, e.g., a photosynthetic reaction center with integral semiconductor storage.

0.1 μm 100 nm

Ultraviolet

Nanoworld

10-7 m

0.01 μm 10 nm

Self-assembled, Nature-inspired structure Many 10s of nm Nanotube electrode

ATP synthase 10-9 m Soft x-ray

1 nanometer (nm)

More is different! DNA ~2-1/2 nm diameter

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Atoms of silicon spacing ~tenths of nm

10-10 m

0.1 nm

Quantum corral of 48 iron atoms on copper surface positioned one at a time with an STM tip Corral diameter 14 nm

Carbon nanotube ~1.3 nm diameter

Carbon buckyball ~1 nm diameter

Office of Basic Energy Sciences Office of Science, U.S. DOE Version 10-07-03, pmd

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Variation in Process Parameters Device 2

Norrmalized Frequency

1 .4

Device 1

1 .3

30%

1 .2

130nm 1 .1

Source: Intel

1 .0

5X

0 .9 1

Channel length

2 3 4 N o rm a liz e d L e a k a g e ( Is b )

5

# dopant atoms

Delay and Leakage Spread

Inter and Intra-die Variations

10000

Source: Intel 1000 100 10

1000 500 250 130

65

32

Technology Node (nm)

Random dopant fluctuation

Device parameters are no longer deterministic

Reliability

Failure probabilityy

Temporal degradation of performance -- NBTI

Tech. generation

Time Defects Interface trap generation over time

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Life ti Lif time degradation

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Scaling & Ion/Ioff 100 nm

1 um

Silicon micro electronics

10 nm

Silicon nano electronics

Non-Silicon technology I

• Increasing leakage • Increasing process variations p

• Carbon Nanotubes • Molecular transistors

• Short Channel Effects

• Molecular RTDs

I ON = 103 I OFF

I ON = 106 I OFF

V

I ON = 10 4 I OFF

2. Power & Power Density 100

Power (Wa atts)

10 8086

486

286 386

8085 1 8080 8008 4004

Power Density (W/cm2)

P6 Pentium ® proc

0.1 1971

1974

1978

1985

1992

2000

Year

Year

Increased Average Power • Battery Life • Cooling Cost

Increased Power Density • Reliability Source: Intel

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Nano-Scaled Si Devices Si Fin

DGMOS

FinFET or Tri-Gate

Planar double-gate structure

Quasi-planar DG structure

Ground PlaneSOI MOS

Independent gate FinFET

Bulk Si MOSFETs

Shared back gate DG devices

Freque ency (norm) q y

Variation in Process Parameters 1 .4 1 .3

30%

1 .2

130nm 1 .1

S Source: Intel I t l

1 .0

5X

0 .9 1

3

2

4

5

Leakage (normalized)

Inter and Intra-die Variations

# dopant ato oms

10000

Source: Intel 1000 100 10

1000 500

250 130

65

32

Technology Node (nm)

Random dopant fluctuation

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Evolution in Complexity

Processor Trends 800 700

PP 66 PP-66

HP PA8000 UltraSparc-167 PPro-150 PPro 150 MIPS R10000 SuperSparc2-90 A21164-300

600

HP PA7200

Die Size (mil2)

PPro200 PPC 604-120 A21064A MIPS R4400 PP-100

500

PPC 601-80 400

486-66 i486C-33 DX4 100

PP-133

300 i386 200

i386C-33

100 0

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'91

'93

'94

'95

'96

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Processor Trends (cont’d) 300

A21164-300 A21064A

250

Freq(MHz)

200

MIPS R5000 PPro200

MIPS R4400

HP PA8000

MIPS R10000

UltraSparc-167 150

HP PA7200 PP-133

PP166 PPro-150

PPC 604-120 100

DX4 100

50

486-66 PPC 601-80 PP-66 i386C-33 i486C-33 i386

0

'91

PP-100

'93

PPC603e-100

SuperSparc2-90

'94

'95

'96

Higher Performance: •Higher Frequencies (2x/Generation) •Higher Device counts (2x /Generation)

Power Trends 40

A21164-300

HP PA8000

35 30

A21064A

Power(W)

PPro200

UltraSparc-167 PPro-150 HP PA7200

25

MIPS R10000

20 15 10 5 0

SuperSparc2-90 PPC 604-120

PP-66 PPC 601-80 i486C-33

MIPS R5000 PP166

MIPS R4400 PP-100 PP-133

486-66 DX4 100

PPC603e-100

i386 i386C-33 '91

'93

'94

'94

'95

'96 [Source: Microprocessor Report]

2x Performance Increase ==> 2x power increase

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Heat Dissipation • Chips fail when they get hot • Need compact p and cost-effective cooling g solns CPU

Thermal Soln Cost

486/33mhz

HeatSink $0.50

486DX2 66mhz Pentium 66mhz

Heatsink $1.00 Larger Heatsink $2.00 System Fan $4.00

• Cooling Solns will become more exotic/expensive – Extruded Heatsinks, Heatpipes, Blowers, Noise....

• Every Watt impacts System Cost, esp. for HVM

Where is the Power Going? (Mobile PC) 30 25 20 15 10 5 0 89

91 CPU

92

93 Graphics

94

95 I/O Subsystem

96

97 Total

CPU Power: p predicted from average g device count/area growth g

• CPU Power increasing (Predicted in 1994 Low power workshop) • Graphics & Chipset Power increasing faster than predicted Power reduction is not only a CPU problem

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Intel 4004 Microprocessor

Intel Pentium (II) Microprocessor

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Dunnington is the first IA (Intel Architecture) processor with 6-cores, is based on the 45nm high-k process technology, and has large shared caches.

Tukwila, 4-cores, world's first 2 billion transistor microprocessor

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National Technology Roadmap for Semiconductor (NTRS)

Technology T h l (um) ( ) Year # transistors On-Chip Clock (MHz) Area (mm2) Wiring Levels

0 25 0.25 1998 28M 450 300 5

0 18 0.18 2001 64M 600 360 5-6

0 13 0.13 2004 150M 800 430 6

0 10 0.10 2007 350M 1000 520 6-7

0 07 0.07 2010 800M 1100 620 7-8

Interconnect Performance Trend

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Technology (um) 2cm line delay (ns)

0.25 0.18 0.15 2.589 2.480 2.650

0.13 2.620

0.10 3.730

0.07 4.670

1mm line delay (ns)

0.059 0.049 0.051

0.044

0.052

0.042

Intrinsic gate delay (ns) 0.071 0.051 0.049

0.045

0.039

0.022

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Interconnect Complexity Technology (um) Length (m) Wiring Levels Opt. # buffers per net Opt. # wiresizes per net Opt. # buffers per chip

0.25 0.18 820 1,480 6 6 6-7 few few 5K 25K

0.13 2,840 7

54K

0.10 5,140 7-8 8

0.07 10,000 89 8-9 many many 230K 797K

• Performance • Signal reliability • Electromigration

Distributions of Wire lengths

Nu umber of Interconnectts

1E+07 Rent's exponent = 0.6 Rent's Rent s coefficient = 4.0 Avg. fanout = 3

1E+06 1E+05 1E+04 1E+03 1E+02

0.07 um tech.

1E+01 0.25 um tech.

1E+00

0

10

20

30

Length (mm)

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Technology Scaling Technology scaling improves: Transistor & interconnect performance Transistor density Energy consumed per switching transition 0.7X scaling factor (30% scaling) results in: 30% gate t d delay l reduction d ti (43% ffreq. ↑ ) 2X transistor density increase (49% area ↓ ) Energy per transition reduction

Technology Scaling • Speed & Performance – High drive current and low parasitics – Low gate delay and high frequency

• Density & Area – Small feature size

• Power & Reliability – Low power supply voltage – Low L off-state ff t t leakage l k

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Technology Generation Scaling Dimensions ⎯scale ⎯ ⎯→ 0.7, Vdd ⎯scales ⎯⎯→ β , Vt ⎯scales ⎯⎯→ β I=

kW 0.7 (Vdd − Vt ) ⎯scales ⎯⎯→ ×β = β Tox 0.7

D=

CVdd I

E = CVdd

⎯scales ⎯⎯→

0.7 × β

β

⎯scales ⎯⎯→ 0.7 β

2

= 0.7

(30% delay reduction)

2

IC Frequency & Power Trends

•

Gate delay improves ~30% Power increases 50% Power = CL V2 f

• •

1000 1000 100 100

1000 1000

Pentium R II Processor

Power

800 800

Pentium R Processor

10 10

600 600 486DX CPU

11

400

386

0.1 0.1

0.01 0.01

200

Frequency 1

2

3

1.0 0.8

4

5

6

7

00

Frrequency (M Hz)) Frequency (MH Hz)

Clock frequency improves 50%

Chip Power (W) Chip Power (W W)

•

0.6 .35 .25 .18

Technology Generation (μm) Active switched capacitance “CL” is increasing.

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Constant Voltage vs Field Scaling

• VCC & modest VT scaling • Loss in gate overdrive (VCC-VT)

V CC or V T (V)

• VCC ⌫ 1V

5 VCC or VT (V)

• Recently: constant efield scaling, aka voltage scaling

4 3

5

VCC

4 3

(VCC- VT ) Gate over drive

22

VT

11 00

0

VCC=1.8V

VT =.45V

1

2

3

4

5

6

7

1.4 1.0 0.8 0.6 .35 .25 .18 Technology Generation (μm) Voltage scaling is good for controlling IC’s active power, but it requires aggressive VT scaling for high performance

59

Barriers to Voltage Scaling Voltage Scaling = Constant Electric Field Scaling Voltage scaling is good for IC’s active power, but degrades gate over drive. Requires VT scaling.

Leakage power Short-channel effects Special circuit functionality, noise Soft error Parameter variation 60

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Subthreshold Leak kage

Barriers to Voltage Scaling 1000

Leakage power Short-channel effects Soft error Special circuit functionality

constrained Ioff maintain Vcc/Vt

100

10

1 0.25um 0.18um 0.13um 0.09um

Technology Generation

61

Delay CV τ d = L DD ID

τd =

CL V W ( ) μC oxV DD (1 − T ) 2 2L V DD

τd =

CL WC oxυ SAT (1 −

VT ) VDD

Long Channel MOSFET

Short Channel MOSFET

. CL0.5T 05 1 2.2 ox ( ) τ= + V W W . 13 . 0 3 T n p V (0.9 − V ) DD DD

[1]

[1] C. Hu, “Low Power Design Methodologies,” Kluwer Academic Publishers, p. 25.

Performance significantly degrades when VDD approaches 3VT. 62

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VT Scaling: VT and IOFF Trade-off Performance vs Leakage:

ID(SAT)

VT ↓ IOFF ↑ ID(SAT) ↑

I OFF ∝ I subth ∝ I D ( SAT ) ∝

Weff Leff

Leff

IDS

Weff

Low VT K1e

High VT

(VGS −VT )

VD = VDD fixed Tox

IOFFL

K 2 (VGS − VT ) 2

IOFFH

I D ( SAT ) ∝ K 3Weff Coxυ SAT (VGS − VT )

VTL VTH

VG

As VT decreases, sub-threshold leakage increases Leakage is a barrier to voltage scaling 63

IOFF vs VT 1E-04

IOFF (A)

1E-05

1E-06

Log IOFF

1E-07

I OFF ∝ e (VGS −VT )

1E-08

1E-09

1E-10 -0.5

-0.45

-0.4

-0.35

-0.3

-0.25

-0.2

VT (V) - Normalized

VTP (V)

IOFF is an exponential function of VT.

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Future: Projected Leakage Trends 10,000 0.10 um 0.13 um 0.18 um

1,000 IOFF (nA/ μ m)

0 25 um 0.25

100

10

1

30

40

50

60

70

80

90

100 110

Temperature (C)

St (30C) = 80 mV/dec St (100C) = 100 d VT/dT = 0.7 mV/C

IOFF (0.25um) = 1 nA/um (scales 5X) VT (0.25um) = 450 mV (scales by 15%)

Why Excessive leakage an Issue?

• Approaching ~10% in 0.18 μm technology • Acceptable limit less than ~10%, implies serious challenge in VT scaling!

1.E+02

1 10100

Power (W))

• Leakage component to active power becomes significant % of total power

1 1010

1.E+01

1010

1.E+00

Active Power

386

-1 -1 10

1.E-01

10

Pentium R Pro Processor

R

P ti Pentium 486DX Processor CPU

-2

-2 1010

1.E-02

Standby power (component Transistor Leakage T=110C)

-3

-3 1010

1.E-03

10-4

10-4

1.E-04

10-5

10-5

1.E-05

-6 10 -6 6

10

1.E-06 0

1

2

3

4

5

6

7

1.0 0.8 0.6 .35 .25 .18 Technology Generation (μm)

Barrier

high static leakage (standby) power 67

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Power Trends • Enable development of ultra low voltage circuits Vt Variation for optimum energy • At lower Vt, 2.5 Normalized Energy

– leakage g becomes a p problem 2 – Signal integrity and Noise margin

Vdd =1.7V Decreasing Switching Power Decreasing Leakage Power

1.5

1

f=20MHz

Vdd = 0..5V

Vdd = 0..9V 0.5 • Multiple on-chip Vt Vt, 0 0.2 dynamic Vt • Other challenges for low voltages ?

0.4 0.6 Threshold Voltage (Vt)

0.8

1

[Source: A.Chandrakasan et.al. Proc of IEEE April’95]

Trends in Microelectronics • Improvement in device technology – Smaller circuits – Faster circuits – More circuits on a chip

• Higher Integration – More complex systems – Lower cost of computation – Higher reliability

• Limitations – – – –

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Intrinsic device scaling limits Cost of fabrication Interconnect limitation Large scale design management

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Problems of Microelectronics • Design Cost: – – – –

design time fabrication time i impossibility ibilit tto repair i reduce design cost to be competitive in price

• Marketing Issues: – use most recent technologies to stay competitive in performance – volume production is inexpensive – time-to-market is critical – evolving market

• Solution: – Hierarchical and abstraction – Different design styles – Computer-Aided-Design

Circuit and System Representations Complex digital system

Component gates + Memory systems

• 3 design domains – Behavioral • specifies what a particular system does

– Structural • how entities are connected together to effect the prescribed manner

– Physical • how to actually build a structure that has the required connectivity to implement the prescribed behavior

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Design Abstraction Levels SYSTEM

MODULE + GATE

CIRCUIT

DEVICE G S n+

D n+

For a Digital Design

• • • • • • •

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Architecture Algorithm Module or Functional Block logical Switch Circuit Layout

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Behavioral Representation Domain • Hardware description language – VHDL, VHDL Verilog V il

• Boolean equation • Within this domain, there are various level of abstraction – Algorithm – Register transfer level (communication between registers)

Acc

Acc + R1

– Boolean equations

CO = A.B + A.C + B.C carry

Behavioral Representation Domain - cont. • Algorithm level (Verilog)

can include speed info

MODULE carry (co, a,b,c) output co input a, b, c assign co = (a&b)|(a&c)|(b&c); ENDMODULE

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Structural Domain • The levels of abstraction include – – – –

module gate switch circuit

MODULE carry (co, a, b, c) input a, b, c; output co; wire x,, y, z AND g1 (x, a, b) AND g2 (y, a, c) AND g3 (z, b, c) OR g4 (co, x, y, z); ENDMODULE

Structural Domain- cont.

x

a b g1

g2

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g3

y

a c

z

b c

x y z

co g4

30


Transistor Level MODULE carry (co, a, b, c) input a, b, c; output co; wire i1, i2, i3, i4, cn; NMOS n1(i1, vss, a) NMOS n2(i1, vss, b)

. . .

( , vdd,, b); ); PMOS pp1(i3, PMOS p2(cn, i3, a);

. . .

ENDMODULE

Physical Representation MODULE carry ; Input p a,, b,, c;; output co; boundary [0, 0, 100, 400] port a aluminum width = 1 origin = [0,2] port b aluminum width = 1 origin = [0,7] port

. . .

Port ci polysilicon ……. ENDMODULE

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CMOS Logic a

a

s

s b

b

NMOS transistor

PMOS transistor

Consider them as switches

a

a s=0

s=0

a

b

a

s=0

b

b

b a

a s=1 s=1

a

b

a

s=1

b

b

b

Inverter (A) VDD

A

B

- Low power dissipation

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NAND (AB)

A

A

A+ B B

A

0 Out

1

0

1

1

1

0

B

A 1 B

A.B

NOR (A+B)

A

A

A. B

0

1

B 0

1

0

0

0

B A

B

1

A+B

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Complex Gates F = (( A + B + C ).D ) = D + ABC F = ( A + B + C ).D

A D

B C

D

A

B

C

VLSI Design is Inter-Disciplinary

• Breadth of field – – – – –

Semiconductor physics and technology Integrated electronics Systems design Testing Computer-Aided Design

• Depth p of field – Complexity of fabrication technology – Difficulty of design problems

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