Effect of deposition parameters on surface roughness ...

Journal of Micromechanics and Microengineering

TOPICAL REVIEW

Effect of deposition parameters on surface roughness and consequent electromagnetic performance of capacitive RF MEMS switches: a review To cite this article: Zhiqiang Chen et al 2017 J. Micromech. Microeng. 27 113003

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Journal of Micromechanics and Microengineering J. Micromech. Microeng. 27 (2017) 113003 (26pp)

https://doi.org/10.1088/1361-6439/aa8917

Topical Review

Effect of deposition parameters on surface roughness and consequent electromagnetic performance of capacitive RF MEMS switches: a review Zhiqiang Chen , Wenchao Tian, Xiaotong Zhang and Yongkun Wang School of Mechano-Electronic Engineering, Xidian University, Xi’an 710071, People’s Republic of China E-mail: [email protected] or [email protected] Received 17 May 2017, revised 24 August 2017 Accepted for publication 30 August 2017 Published 16 October 2017 Abstract

Surface roughness seriously affects the electromagnetic performance of capacitive radio frequency (RF) micro-electromechanical system (MEMS) switches. This review presents the effects of different film thickness values, substrate topologies, sputtering powers, gas pressures, gas ratios, substrate temperatures and annealing temperatures on the surface roughness of deposited thin films. At the same time, the mechanisms of the deposition parameters on the surface roughness are also analyzed. The effects of surface roughness on the electromagnetic performance of capacitive RF MEMS switches are then discussed in detail. Finally, two different methods for improving the surface roughness of deposited thin films are given. Keywords: RF MEMS, surface roughness, electromagnetic performance, deposition, sputtering (Some figures may appear in colour only in the online journal)

1. Introduction

Greenwood and Williamson [19] developed the first contact model of rough surfaces, a lot of work has been done to analyze surface roughness related problems [6, 20–24]. The contact percentages between rough-surface structures and smoothplane structures under external loads may be just 1–10% of the theoretical values, and decrease rapidly with increasing separation between them [8]. In addition, the contact ratios of the area increase with increase in operation time [7]. The variation in surface roughness affects the electromagnetic performance of RF MEMS switches in turn. To enhance the electromagnetic performance of RF MEMS switches, the basic problems with them should be addressed in addition to the design of novel RF MEMS switch structures [25–27]. The objective of this review is focused on the effect of deposition parameters on surface roughness and the influence

As a key device in the radio frequency (RF) communications area, RF micro-electromechanical system (MEMS) switches have been widely applied in telecommunications, remote sensing, radar, amplifiers, phase shifters, impedance tuners, filters, etc [1, 2] for the advantages of high throughput, small size, very low insertion loss, very high isolation, very high linearity and high power handling capacity [3–5] at high frequency compared with field-effect transistors and positive intrinsic negative diode switches. However, their wide application is hampered by reliability problems, in particular surface roughness related problems, such as electromagnetic characters [6–9], thermal behaviors [10–12], electromechanical characteristics [13–15], adhesion and friction [2, 16–18] etc. After 1361-6439/17/113003+26$33.00

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© 2017 IOP Publishing Ltd Printed in the UK

Topical Review

J. Micromech. Microeng. 27 (2017) 113003

of surface roughness on the electromagnetic performance of capacitive RF MEMS switches. Section 2 presents a brief introduction to RF MEMS switches. Section 3 compares and analyzes the effects of some deposition parameters on the surface roughness of the deposited thin films. Section 4 demonstrates the influence of surface roughness on the electro magnetic performance of capacitive RF MEMS switches. Section 5 gives two methods for improving the surface roughness, and section 6 offers some conclusions.

Figure 1. A standard capacitive shunt RF MEMS switch.

When the electrostatic force is removed, the metal bridge is exposed to an elastic restoring force and the switch pulls up. Under this circumstance, the RF signal passes through the signal line because the capacitance between the metal bridge and the CPW signal line is much smaller in this state. The design considerations of RF MEMS switches are mainly focused on improving the RF performance and reducing the actuation voltage through mechanical design or new materials, rather than consideration of the micro-contact interfaces [5]. However, the contact interface, in particular the surface roughness, affects the RF performance of RF MEMS switches. This review first presents the effects of deposition parameters on the surface roughness, and then summarizes the effects of surface roughness on the electromagnetic performance of capacitive RF MEMS switches.

2. Brief introduction to RF MEMS switches RF MEMS switches can be classified into direct current (DC) series contact switches [28], DC shunt switches [29], capacitive series switches [30] and capacitive shunt switches [31], according to the method of contact. The DC contact switches (series and shunt) can operate at a wide frequency from DC to gigahertz (GHz), and they show better insertion loss and isolation in the frequency range. However, the insertion loss is determined by the contact resistance and the isolation is related to the parasitic capacitance. In addition, the contact materials of DC contact switches are typically gold or other metals, which are much softer than dielectric materials, and adhesion and friction occur frequently in these types of switches. The capacitive series switches have better insertion loss and isolation when the frequency is in the range of several GHz (typically 1–10 GHz). The capacitive shunt switches have better insertion loss and isolation at higher frequency ranges (typically tens of GHz) and their performance is determined by the capacitance ratios. On the other hand, the current RF MEMS switches can be classified into electrostatic [25], electro-thermal [32], magn etic [33] and piezoelectric [34] driving based on actuation mechanisms. Electro-thermal and magnetic actuations offer the advantages of low actuation voltage and high contact force, but the switch time is a little longer and draws high cur rent, and then they dissipate more power [5, 35]. Piezoelectric actuation can provide low actuation voltage and fast switch time, but there is parasitic actuation because of the mismatch in the coefficients of thermal expansion (CTEs) of different layers [5]. Electrostatic actuation RF MEMS switches are the most commonly used ones for the advantages of low power loss, low insertion loss and high isolation [5]. Shunt capacitive RF MEMS switches are the most researched of all the electrostatic actuation types for their good electromagnetic performance at high frequency range. Figure 1 shows the commonly used schematic structure of a standard shunt capacitive RF MEMS switch [36, 37]. As shown in figure 1, it contains a metal bridge, a silicon nitride insulator, a coplanar waveguide (CPW) signal line, two CPW ground lines on the two sides and a silicon substrate. The movable metal bridge moves toward the fixed dielectric layer and the CPW signal line (down electrode) in response to the applied hold-down voltage. Then the RF signal in the CPW signal line is isolated by the metal bridge due to the large capacitance between the metal bridge and the CPW signal line after the contact between the metal bridge and dielectric layer.

3. Effects of different deposition parameters on the surface roughness of thin films Deposition is the most commonly applied process during the fabrication of thin films. According to the thin-film forming mechanism, deposition can be classified into chemical vapor deposition (CVD), such as low pressure CVD [38] and plasma enhanced CVD (PECVD) [39], and physical vapor deposition such as sputtering deposition [40–42], ion beam sputtering [43, 44], thermal evaporation [45, 46], pulsed laser deposition (PLD) [47, 48], etc. This review mainly focuses on sputtering deposition and some other deposition processes are also proposed. It is always true that different deposition processes and deposition materials have different surface roughness. Furthermore, even though the thin films are fabricated with the same process, the fabrication conditions, such as deposition temperature [49], film thickness [50], sputtering power [51], etc also have an influence on the surface roughness of thin films. The aim of this section focuses on the effects of different film thicknesses, substrate topologies, sputtering powers, sputtering pressures, sputtering gas ratios, substrate temper atures and annealing temperatures on the surface roughness of the deposited films. 3.1. Effects of different film thicknesses on the surface roughness of the thin films

The thickness of the thin film is determined by the deposition rate and deposition time. It has been reported that films with different thickness have different surface roughness. Table 1 elaborates the detailed deposition parameters and lists the 2

Topical Review


Table 1. Comparison of the surface roughness of thin films at different film thicknesses.

Film

Deposition process

Substrate/Tsub (°C)

Pwork (Pa)

Gas/rgas (sccm)

rdep (nm s−1)

Pdep (W)

Ascan (µm2)

Au

Evaporation

Si

10−4

—

0.6

—

0.5 × 0.5

Ti

DC magnetron sputtering

Glass/RT

0.665 Ar/20

0.783

100

2 × 2

W


Si

0.7

Ar/150

0.05

200

0.5 × 0.5

MgO

IBAD

Electron beam — evaporation

—

—

AlN

RF magnetron sputtering

Si(0 0 1)/450

0.8

Ar and N2 0.11

TiN


Si (ρ > 100 Ω cm)/450

0.1

Ar/100

—

SRG


Si/500

2.66

Ar

0.267

—

2 × 2

1000

2 × 2

1.23 W cm−2

1 × 1

100

3 × 3

tfilm (nm)

σRMS (nm)

100 200 400 800 1600 100 250 500 900 7 18 35 55.8 160 2.2 5.0 6.0 9.2 12 240 490 750 960 35 110 140 305 500 1500 3000

1.68 2.49 4.75 7.05 9.92 2.45 3.69 5.88 11.84 0.70 1.25 1.65 1.72 2.20 0.682 1.181 1.388 2.015 2.502 1.01 1.43 1.88 2.25 0.5 1.3 1.7 3.1 2.520 2.033 1.202

Reference [50]

[52]

[53]

[56]

[57]

[58]

[61]

deposited films increases with film thickness [54, 55]. Zhu et al [53] also reported that this phenomenon was related to the variation in the grain size because RMS roughness was determined by the height fluctuations in the surface profiles. The surface roughness of compounds was also analyzed by other researchers [56–58]. For example, Xue et al [56] found that σRMS of the deposited magnesium oxide (MgO) films via ion beam assisted deposition (IBAD) increased from 0.682 to 2.502 nm as tfilm increased from 2.2 to 12 nm. Reusch et al [57] and Freixas et al [58] researched the surface roughness of aluminum nitride (AlN) and titanium nitride (TiN) [58] thin films, respectively. Table 1 lists the deposition conditions and test results in detail. As shown in table 1, the surface roughness of the compounds (MgO, AlN and TiN included) also increased with the film thickness. Chang et al [59] also found that the RMS roughness of RF magnetron sputtered Ti-doped zinc oxide (ZnO) films increased from 0.50 to 1.78 nm when the film thickness increased from 30 to 950 nm. This was mainly due to the fact that thin films have smaller grain size than the thick ones [57, 59, 60]. However, not all materials have the same trends between σRMS and tfilm as metals and compounds. Tiwari et al [61] found that σRMS of sodium-rich glass (SRG) thin films decreased from 2.25 to 1.20 nm as tfilm increased from 500

comparison results of the surface roughness of thin films with different thickness values. In table 1, Tsub means the substrate temperature in centigrade (°C), Pwork indicates the working pressure in Pascal (Pa), rgas is the rate of gas used during deposition in standard-state cubic centimeter per minute (sccm), rdep represents the deposition rate, Pdep is the deposition power in Watt (W) or power density, sometimes, Ascan shows the scan area in square micro-meter (µm2), tfilm expresses the film thickness in nano-meter (nm), and σRMS gives the RMS roughness of the thin films in nm. Metals are the mostly applied materials during the deposition process in MEMS device fabrication. Among them, gold (Au) is the commonly used material for its excellent electrical conductivity and ductility. Van Zwol et al [50] found that σRMS of Au films increased from 1.68 to 9.92 nm when tfilm increased from 100 to 1600 nm. As well as Au, the surface roughness of titanium (Ti) [52] and tungsten (W) [53] has also been investigated by other researchers. Table 1 lists the deposition conditions and test results in detail. It was found that the surface roughness of metal thin films increases with film thickness. Jaiswal et al [52] attributed this to the increase in grain size and voids on the surface due to the increase in film thickness, as shown in figure 2. This is consistent with the results in some papers that the surface roughness of the 3

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Figure 2. 2D atomic force microscopy (AFM) images of Ti films deposited with different thickness on a glass substrate: (a) T1 ~ 100 nm,

(b) T2 ~ 250 nm, (c) T3 ~ 500 nm, and (d) T4 ~ 900 nm. T1, T2, T3 and T4 are the thicknesses of the deposited films. Reproduced with permission from [52].

to 3000 nm. Bhatt et al [62] also found that the mean roughness (Ra) of RF magnetron sputtered α-SiO2 thin films at 300 W power and 0.665 Pa pressure decreased from 0.72 to 0.25 nm as the film thickness increased from 0.5 to 3.0 µm. This was attributed to the prolonged deposition time for preparing thicker films, which allowed the atoms to rearrange into low energy states by surface diffusion and thus reduced σRMS [61, 62]. In this section, the surface roughness of various thin films with different thicknesses was compared and presented. The results showed that the surface roughness of metal (Au, Ti, W) and compounds (MgO, AlN, TiN) increased with the film thickness. This was due to the fact that the deposited metal and compound particles had enough surface mobility at the substrates under the deposition temperature. Therefore, the surface roughness increased because there was an increase in grain size and the grains protruded out of the relatively flat surface as the film thickness increased. However, the surface roughness of SRG films decreased as the film thickness increased. This was explained by the fact that the prolonged deposition time to prepare thicker films allowed the atoms to rearrange into low energy states and so reduced surface roughness. It should be noted that metals and the aforementioned compounds are crystal, while SRG and α-SiO2 are non-crystal or of amorphous structure. Therefore, it can be deduced that the surface roughness of crystals increases while that of noncrystal material decreases with the film thickness due to the different material characteristics between them.

3.2. Effects of substrate topologies on the surface roughness of deposited thin films

The surface topologies of different substrates may be different, which in turn affects the surface roughness of the thin films grown on them. Table 2 lists the surface roughness of thin films grown on different substrates via PECVD, RF magnetron sputtering and PLD. The parameter implications were the same as the previous section except that δRMS meant the original surface roughness of the substrates was in nm before the film deposition process. Yu et al [8] found that σRMS of deposited SiN films grown on Ti, Cr, Al and Cu substrates were 2.192, 4.471, 12.29 and 14.81 nm, respectively. At the same time, δRMS of Ti, Cr, Al and Cu substrates were 2.162, 3.067, 4.196 and 4.314 nm, respectively. It was presented that the smoother the substrate surface, the lower the σRMS of the deposited films on them. However, there was a larger increase in σRMS of thin films deposited on Al and Cu substrates compared to those grown on Ti and Cr substrates. This was explained by the fact that the increase in σRMS of thin films on an Al substrate was mainly caused by the ‘hillock’ formation in the substrate [8, 63, 64], while for Cu it was mainly due to the agglomeration and coalescence of the grains [8, 65]. References [66, 67] analyzed the surface roughness of the compound films that were deposited via RF magnetron sputtering on different substrates. For example, Jiao et al [66] found that σRMS of the deposited films on SiO2, Si(1 1 1), Si(1 0 0) and α-Si substrates was 4.22, 6.60, 6.62 and 6.99 nm, 4

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Table 2. Comparison of the surface roughness of thin films grown on different substrates.

Film

Deposition process

Pwork (Pa)

Gas/rgas (sccm)

rdep (nm s−1)

Pdep (W)

SiN

PECVD

—

—

—

AlN


0.65

N2 and Ar/60

AlN


1.33

TiN

PZT

tfilm (nm)

Tsub (°C)

Ascan (µm2)

—

150

250–300

10 × 10

—

200

1200

Water cooled

2 × 2

N2 and Ar

—

550

1200

RT

0.7 × 0.7

Pulsed laser — deposition

N2 and Ar

—

—

100

20

2 × 2

Pulsed laser 10 deposition

O2

0.16

3.5 J cm−2

300

600

2 × 2

δRMS Substrate (nm)

σRMS (nm)

Ti Cr Al Cu SiO2 Si(1 1 1) Si(1 0 0) α-Si SiO2/Si Si(1 0 0) Si3N4/Si Pt/Ti/ SiO2/Si Si PC PU GaN/Si R-TiO2 buffered GaN/Si

2.162 3.067 4.196 4.134 σ3 due to electrostatic repulsion.

d = 0.2 µm 0.4 0.6 0.8 1.0

2.1

1.9

1.7

1.5 1E-9 10-3

1E-8 10-2

1E-7 10-1

Hemisphere radius, R (µm)

Figure 22. Normalized capacitance C∗ versus hemisphere radius R for various gap values g0. Reproduced from [14]. © IOP Publishing Ltd. All rights reserved.

The films grown at 200 °C had the smoothest surface. This was attributed to grain coalescence and larger grain growth at higher substrate temperatures [121, 122]. Singh et al [123] also found that the surface roughness of pulsed DC magnetron sputtering Zr films decreased as the substrate temperature increased due to the densification of the films with increasing temperature, while it increased after some certain temperature (500 °C in their research) due to crystallite growth. The effect of substrate temperature on the surface roughness of the grown films was discussed in this section. It was presented that the effects of substrate temperatures on the surface roughness of the deposited films strongly depended on the type of material. Typically, there were optimal substrate temperatures to grow the smoothest films, which depended upon the material characteristic, such as crystallization temperature and melting point.

Figure 20. The simplified structure of an RF MEMS switch at (a) down-state (b) up-state. εr is the relative dielectric permittivity of the insulator, td is the thickness of the dielectric film, and d0 is the distance between the metal bridge and insulator when the switch is on up-state.

was RT, 300 and 600 °C. This was mainly attributed to the grain growth taking place for the increase in rate of surface atom migration at higher substrate temperatures because the atoms obtained extra energy other than kinetic energy when they arrived the substrates [116]. However, Jin et al [120] and Nam et al [121] found that there was an optimal substrate temperature to deposit the smoothest films. For example, Nam et al [121] found that σRMS of the deposited Ga-doped zinc oxide (GZO) thin films decreased from 7.02 to 0.38 nm as Tsub increased from RT to 200 °C, and then increased to 0.74 and 4.18 nm as Tsub increased to 300 and 400 °C, respectively.

3.7. Effects of different annealing temperatures on the surface roughness of thin films

Thermal annealing at certain temperatures can drastically reduce the residual stress close to zero [45]. Therefore, it was applied to fabricate thin films during the MEMS process post-treatment. This section mainly discusses the effects of 16

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Metal bridge at up-state

x

0

Asperity-meanheight plane

g

gma

g0

z td

Dielectric layer Lower DC pad

z

(a) Asperity-meanheight plane

Metal bridge at down-state

x

0

Cd21

g′

td

Dielectric layer

Cd22

Lower DC pad

z

Cd1

Figure 25. Capacitance as a function of fractal dimension for

(b)

various values of dielectric thickness. d is the thickness of the dielectric layer and D is the fractal dimension, which could quantitatively describe surface microscopic roughness. Reprinted from [164], Copyright (2002), with permission from Elsevier.

Figure 23. Schematic view of the contact between the flat metal bridge and the rough dielectric layer. (a) Up-state, (b) down-state. gma is the gap between the metal bridge and the asperity mean-height plane at up-state, g is the distance from the metal bridge to the asperity peak, z is the height of the asperity tips, td is the thickness of the dielectric layer, g0 is the distance from the metal bridge to the lower DC pad, g′ is the separation between the metal bridge and the asperity mean-height plane at down-state, Cd1 is the capacitance result from the area where the metal bridge contacts with the Si3N4 surface, Cd21 and Cd22 are the capacitances that came from the air gap between the metal bridge and SiN and SiN itself, respectively. Reproduced from [8]. © IOP Publishing Ltd. All rights reserved.

Sobri et al [127] also reported that the grain size of nickel indium tin oxide (ITO) films grown by RF magnetron sputtering increased with the annealing temperature, as shown in figures 17 and 18. This was consistent with the results of some other researchers [128–130]. However, many researchers have found that the surface roughness of the deposited films does not always increase with the annealing temperature [131–134], as shown in table 7. For example, Pandey et al [131] found that σRMS of the deposited films was 19.70, 8.46, 14.80 and 13.2 nm when Tan was 400, 600, 800 and 1000 °C, respectively. It could be seen that the smoothest surface appeared when the annealing temperature was 600 °C. Similar results were found by Kuru et al [132]. Their results showed that there were optimal annealing temperatures for different film materials. Interestingly, the results in [133, 134] showed that the surface roughness of the thin films increased after annealing as compared to the as-deposited ones, though it might decrease with the annealing temperature. For example, Husna et al [134] found that σRMS of the deposited thin films was 6.83, 7.26, 7.20, 14.90 and 8.67 nm annealed at 250, 350, 450 and 500 °C, respectively. Some researchers thought that the decrease in the surface roughness was mainly due to the increase of the surface mobility with the annealing temperature [42]. The total energy of the films decreased with the growth of grains and decrease in the grain boundary area, resulting in an increase in the grain size and variance of surface roughness. Others reported that the activation of atom diffusion after obtaining more thermal energy at higher temperature facilitated the repairing of the dislocated atomic occupancies and even promoted the coalescence of adjacent grains [42, 135–137]. In fact, a small amount of annealing could result in stress-free film, but excess annealing could cause distortion of the thin films [115]. In this section, the effects of annealing temperatures on the surface roughness of deposited thin films were summarized in detail. The results showed that the surface roughness of the deposited thin films typically increased after annealing. However, it might decrease for some films, which depends on the crystallization temperature of the film material. Section 3 listed some parameters affecting the surface roughness of the deposited thin films and explained the reasons. Apart

Normalized up-state capacitance

1.0885 1.0884 1.0884 1.0883

3.0 µm 2.4 µm 2.0 µm 1.4 µm 1.0 µm

1.0883 1.0882 1.0882 1.0881 1.0881 1.0881 1.088 0

10

20

RMS Roughness (nm) Figure 24. Influence of surface roughness on the normalized up-

state capacitance with different initial gaps. Reproduced from [8]. © IOP Publishing Ltd. All rights reserved.

different annealing temperatures on the surface roughness of thin films deposited by RF magnetron sputtering. Some researchers have found that there is a slightly increase in the surface roughness of the deposited films with the annealing temperature [124–126], as shown in table 7. For example, Deng et al [124] found that σRMS of the deposited films was 2.10, 2.26, 2.47 and 2.85 nm after deposition, and annealing at 400, 600 and 800 °C, respectively, as shown in figure 16 and table 7. It was thought that the films deposited at low substrate temperature below the crystallization temper ature had smaller grain size and low surface atomic diffusion, while high annealing temperature led to large crystallizationinduced grain size, resulting in a rougher surface [124, 125]. 17

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Table 8. The statistic results of the down-state capacitance.

Author

A (m2)

td (µm)

εr

Cda (pF)

Cdr (pF)

Cda /Cdr

Yu et al [8] Mahameed et al [25] Schauwecker et al [31] Jabir et al [166] Li et al [167] Badía et al [168] Peroulis et al [169] Wang et al [170] Mahameed et al [171] Muldavin et al [172]

1.5 × 10−8 1.125 × 10−8 0.9 × 10−8 1.006 × 10−8 4.0 × 10−8 1.55 × 10−8 1.5 × 10−8 0.48 × 10−8 0.075 × 10−8 0.8 × 10−8

0.15 0.15 0.1 0.1 0.3 0.35 0.2 0.2 0.15 0.15

7.6 7.0 7.5 7.6 7.5 7.5 7.5 7.6 7.0 7.6

6.73 4.65 5.98 6.68 8.85 2.97 4.98 1.62 0.31 3.59

1.48 2.69 3.20 0.75 7.5 0.9 0.8 0.52 0.26 2.7

0.22 0.58 0.54 0.11 0.85 0.30 0.16 0.32 0.84 0.75

1.186

3.0 µm 2.4 µm 2.0 µm 1.4 µm 1.0 µm

Normanized insertion loss

1.185 1.184 1.183 1.182 1.181 1.18 1.179 0

10

20

30

40

50

RMS Roughness (nm)

Figure 26. Influence of RMS roughness on the normalized up-state

insertion loss for different initial gaps at 10 GHz. Reproduced from [8]. © IOP Publishing Ltd. All rights reserved.

Figure 28. Surface roughness as a function of film thickness

for both as-deposited film and after CMP. The SRG films were deposited at 100 W RF power and 20 mTorr pressure in Ar ambient via RF magnetron sputtering. [61] (2013) (© TMS 2013). With permission of Springer.

1.0

Normalized isolation

0.9

20 nm 10 nm 2 nm

0.8

of the final thin films is very system and process dependent, which may also cause a difference in the final results.

0.7

4. Research on surface roughness effect on the electromagnetic performance of capacitive RF MEMS switches

0.6 0.5 0.4 0.3

20

40

60

80

When there is surface roughness, the charge distributions on the rough surface are no longer uniform. According to electrostatic theory [151–154] and point effect [155–157], the electrical charge is mainly centered on the asperities of the rough surface leading to a higher electrical charge density on the tip position, as shown in figure 19. The electromagnetic performance is typically related to the surface topology of the contact area, in particular the capacitance between two electrodes because it is determined by the contact area and distance between the electrodes. However, the real contact area is only a small portion of the whole electrode area [7, 158, 159], which in turn affects the electromagnetic performance of capacitive RF MEMS switches. In this section, the effects of surface roughness on the capacitance and transmission performance of capacitive RF MEMS switches are discussed.

100

Applied hold-down voltage (V ) Figure 27. Variation of the normalized isolation with the applied

hold-down voltage for different RMS roughness. Reproduced from [8]. © IOP Publishing Ltd. All rights reserved.

from the aforementioned parameters, some other parameters, such as deposition angle [138], deposition pressure [62, 139, 140], deposition rate [45, 61, 141, 142], deposition time [143], gas flow rate [90, 144], annealing time [145], pulse frequency in pulsed magnetron sputtering [146] and deposition voltage [147–150] also have an influence on the surface roughness of grown thin films. It should be noted that the surface roughness 18

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Figure 29. Corresponding AFM micrographs for as-grown and polished nanocrystalline diamond films. (A) As-grown CMP polishing after

(B) 1 h, (C) 2 h, and (D) 4 h. The thin films were deposited on 500 µm thickness silicon (1 0 0) p-type wafer by CVD at 40 Torr pressure and 3.5 kW microwave power, and the polishing rates were kept at 60 rpm both for the pad and carrier in opposite directions. Reproduced from [174]. CC BY 3.0.

perfectly smooth, that is to say they are all theoretical values. In the following content, this review presents the differences between the theoretical values and the real ones. Kogut et al [14] assumed a rough surface where all the summits were hemispheres and had the same height distribution, as shown in figure 21. Based on this model, they found that the normalized capacitance C*, defined as the ratio between the actual capacitance with roughness surface and the apparent capacitance from smooth electrodes, increased from nearly 1.6 to 2.2 as the hemisphere radius increased from 1 nm to 100 nm when g0 equaled 200 nm, as shown in figure 22. However, the aforementioned rough contact model was too simple for studying the surface roughness problem. Yu et al [8] improved the previous model and proposed another relatively exact contact model, as shown in figures 23(a) and (b). In this model, the asperity heights followed a Gaussian distribution. On the basis of this model, Yu et al [8] found that the nor malized up-state capacitance changed from 1.088 to 1.0884 when σ varied from 0 to 20 nm with different initial gaps gma (from 1.0 to 3.0 µm), as shown in figure 24. It was noted that the normalized up-state capacitances were larger than one, though they varied slowly with surface roughness and air gap. This indicated that the real up-state capacitance was larger than the theoretical values. This was mainly due to the fact that the surface roughness increased the area of the metal bridge, which resulted in an increase in the up-state capacitance, as expressed by equation (2). At the same time, there was a slight increase in the normalized up-state capacitance

4.1. The effects of surface roughness on capacitance

The capacitance ratio of down-state to up-state capacitance is an important parameter for evaluating the electrical performance of capacitive RF MEMS switches. For the capacitive RF MEMS switches, it can be simplified as a metal insulator metal (MIM) structure, as shown in figure 20. In the general analysis, the down-state capacitance Cd is usually calculated by the macroscopically MIM capacitor equation, which can be expressed as [5, 160, 161] A Cd = εr ε0 . (1) td

In equation (1), A is the contact area, εr is the relative dielectric permittivity, ε0 is the permittivity in free space and approximates to 8. 854 × 10 F m−1, and td is the thickness of the dielectric layer. On the other hand, the up-state capacitance Cu is typically calculated as [1] td εr ε0 A ∼ ε0 A Cu = (d0 ) = (2) td + ε r d 0 d0 εr

where d0 is the distance between the micro-beam and the dielectric layer. Then the capacitance ratio is given by Cd ∼ εr d0 rC = . = (3) Cu td

Noting that equations (1)–(3) are accurate only if the contact surface between the metal bridge and the dielectric film is 19

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in the electrode area due to surface roughness. However, the real down-state capacitance was smaller than the theoretical value due to the imperfect contact between the electrode and dielectric layer, which introduced air between them.

with surface roughness. It was explained that a larger surface roughness led to a smaller equivalent gap between the metal bridge and gma since the asperity vertexes were nearer to the metal bridge [8]. On the other hand, Yu et al [8] found that the real down-state capacitance was only about 85% of the apparent value when the applied hold-down voltage was 30 V and RMS roughness was 2 nm. At the same time, the normalized down-state capacitance decreased with the surface roughness. For example, the normalized down-state capacitance decreased from about 0.85 to 0.265 when the applied holddown voltage was 30 V and RMS roughness increased from 2 to 20 nm. Chen et al [162] also found that the normalized down-state capacitance decreased with the surface roughness and the hemisphere radius. For example, they found that the normalized down-state capacitance decreased from nearly 0.6 to 0.35 when the RMS roughness increased from 0.1 to 20 nm. Bruce et al [163] analyzed the capacitance of a rough-surface capacitor via elementary functions. It was found that the normalized capacitance per unit length decreased sharply with the normalized period of the surface roughness, for example, the normalized capacitance per unit length decreased from about 2.0 to 1.3 as the normalized period of surface roughness increased from about 0 to 5. Patrikar et al [164] researched the capacitance of a rough-surface capacitor according to fractal theory. It was found that the normalized capacitance decreased as the dielectric layer increased, but the real capacitance values were typically larger than the theoretical values, as shown in figure 25. At the same time, the normalized capacitance increased with surface roughness, which increased as a fractal dimension. For example, the normalized capacitance increased from nearly 1.02 to 1.88 as the fractal dimension increased from about 1.15 to 1.65 when the dielectric layer thickness was set to 1.0 µm. Kumar et al [165] also investigated the capacitance of rough-surface capacitors by fractal analysis. It was observed that the capacitance considering the surface roughness could be 1.5 times, when the fractal dimension was 1.5, that without consideration of the surface roughness. At the same time, the real capacitance increased with the fractal dimension; that is to say, it increased with surface roughness. In addition, this review compared the measured down-state capacitance and theoretical values calculated by equation (1) based on the results that had been indicated in [162], and the statistic results are listed in table 8, where A is the apparent contact area, td is the thickness of the dielectric layer, εr is the relative dielectric constant, and Cda and Cdr are the apparent and real down-state capacitances of the capacitive RF MEMS switches, respectively. It can be seen that there is a pretty large dispersion between Cda and Cdr . Some of this dispersion can be attributed to the effect of surface roughness. In addition, some other parameters affect the final normalized down-state capacitance. For example, the additional air gaps due to dist ortion of the actuated beam by stress effect can also affect the down-state capacitance. In this section, the effects of surface roughness on the capacitances of a rough-surface capacitor, which could be treated as the simplified structures of the capacitive RF MEMS switches, were discussed. It could be seen that the real up-state capacitance was larger than the apparent one because of the increase

4.2. The effects of surface roughness on the transmission performance

Transmission performance, which is typically described by the S-parameter, is a key parameter in RF MEMS switches. In the common calculation, the insertion loss and isolation are expressed as [1, 8] 1 S = 20 log (4) 21 1 + jωCZ0 /2

where S21 is the insertion loss when C is the up-state capacitance, or isolation when C is the down-state capacitance in dB, ω is the angular frequency in rad per second and Z0 is the characteristic impedance in ohm (Ω). However, the insertion loss and isolation would be quite different if the surface roughness was taken into consideration. Figure 26 shows the effects of surface roughness on the normalized insertion loss of capacitive RF MEMS switches for different initial gaps [8]. It can be seen that the insertion loss of the rough-surface structure is higher than that without considering the surface roughness. The real insertion loss is as large as 1.185 times the theoretical one. However, the nor malized insertion loss increased with the surface roughness. Yu et al [8] thought that this was due to a larger surface roughness leading to a larger up-state capacitance. Figure 27 shows the normalized isolation versus applied hold-down voltage at different surface roughnesses. It is observed that the normalized isolation decreases as the surface roughness increases [8]. The reason for this is that the real down-state capacitance decreases with the RMS roughness [8]. Kumar et al [165] also found that the insertion loss became higher due to the surface roughness, for example, they found that the insertion loss of a rough surface structure was 1.5 times that without taking surface roughness into consideration when the frequency was 100 GHz and fractal dimension was 1.6. These results were consistent with the finite element simulation results of Sarath et al [173]. In this section, the effect of surface roughness on the S-parameters of capacitive RF MEMS switches was discussed. It was presented that the surface roughness caused the real up-state capacitance to be larger but the real down-state capacitance was smaller than the theoretical values, which resulted in the real insertion loss being larger while the real isolation was smaller than theoretical values. 5. Methods to improve the surface roughness of thin films Section 3 listed some methods for improving the surface roughness, such as changing the film thickness, varying the substrate or annealing temperatures, altering the deposition power or voltage, adjusting the gas pressure or ratio. In this section, other two methods are given to improve the surface roughness of thin films in RF MEMS devices. 20

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6. Conclusion

5.1. Chemical mechanical polishing (CMP)

CMP has been one of the most applied finishing processes during MEMS fabrication [174–178]. Material removal in CMP is a combination of the chemical reaction of an abrasive slurry with the film surface and repeated sliding, rolling or indentation of the abrasive particles against the film surface [179]. Tiwari et al [61] found that the average roughness of the deposited SRG films could be reduced from 0.6 to 0.2 nm after CMP when the film thickness was 3 µm, as indicated in figure 28. It also indicated that the thinner the film thickness, the higher the effect of CMP on the roughness. Thomas et al [174] found that the surface roughness of nanocrystalline diamond thin films decreased as the CMP duration increased, as shown in figure 29. The RMS roughness of the as-deposited CMP polishing after 1, 2 and 4 h was 18.3, 11.0, 4.5 and 1.7 nm, respectively. Deng et al [175] reported that the surface roughness of polyimide films was controlled within 10 nm of CMP. Pirayesh et al [176] also indicated that the RMS roughness of polycrystalline silicon films was decreased from 12 to 0.26 nm after polishing. Wang et al [180] also reported that the surface roughness of SiC substrates could be reduced after CMP, and seriously decreased as the polishing times increased. Hong et al [181] discovered that surface roughness decreased as the polishing temperature increased, in particular, the RMS roughness was 0.96, 0.535 and 0.316 nm when the polishing temperature was 23, 26 and 29 °C, respectively. Liu et al [182] presented that the polishing kinetics and mechanism of CMP was a complicated multiphase reaction process. Actually, the material removal of the solid–solid contact mode was abrasion [179].

This review provides insight into the effects of deposition parameters on surface roughness and the effect of surface roughness on the electromagnetic performance of capacitive RF MEMS switches. It was found that the deposition param eters affected the surface roughness of the deposited film from grain size and deposition rate aspects. Typically, the rougher the substrate surface, the coarser the thin film deposited on it. At the same time, the surface roughness of the deposited film increased with the film thickness for the crystal material, while it decreased for non-crystal material. However, the sputtering power, gas pressure, gas ratio and film thickness had relatively complex impacts on the deposition rate and grain size. In general, there are optimal values for sputtering power, gas pressure and gas ratio ranges to sputter the smoothest thin film. A small amount of heating and annealing can produce stress free film, while excess heating leads to distortion of the deposited film. In addition, the deposition results were also very system dependent, based on the exact configuration of specific tools, which also results in a difference in the surface roughness. When surface roughness existed, the interfaces of the electrode and dielectric layer were not perfectly smooth. Variation in contact area, contact distance and contact coincidence degree resulted in the up-state capacitance being larger than the apparent value, while the down-state capacitance was smaller than the theoretical one. As a result, the final insertion loss was larger while the isolation was smaller than the theor etical values. Therefore, the electromagnetic performance of capacitive RF MEMS switches was degraded due to surface roughness. Finally, two methods for improving the surface roughness were given.

5.2. Thermal treatment

Acknowledgments

Thermal annealing is an important post-fabrication process during MEMS device processing. Some results were shown in section 3 for the annealing temperature on the surface roughness. In addition to the annealing temperature, thermal reflow is another process that can be applied in the MEMS process [183–186]. Ahamed et al [183] indicated that the surface roughness improvement of MEMS vibratory sensors was tenfold at 700 °C for 30 min. These processing materials should be polymers or low glass transition temperature materials. Mafinejad et al [184] analyzed the effects of thermal reflow on the sacrificial layer to improve the surface roughness of the MEMS bridge of RF MEMS switches. The results found that the surface roughness of the metal bridge after thermal reflow at 200 °C for 5 min became uniform [184]. Villeneuve et al [185] analyzed the planarization optimization of gold membrane RF-MEMS switches after thermal reflow and CMP. The results showed that planarization of the gold membrane could be improved after thermal reflow and CMP. Yu et al [186] also proposed that the surface roughness of the capacitive RF MEMS switch membrane could be improved after thermal reflow of the sacrificial photoresist at 200 °C for 2 min.

This work was supported by the Natural Science Foundation of Ningbo city of China: 2016A610030, Shaanxi Province Natural Science Foundation of China: No. 2017JQ5002, China Postdoctoral Science Foundation: No. 2016M600765 and the extension of the National Natural Science Foundation of China: 61176130. The authors would like to thank the valuable advices of the reviewers for this review. ORCID iDs Zhiqiang Chen

https://orcid.org/0000-0001-5417-2818

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