IEEE ELECTRON DEVICE LETTERS, VOL. 28, NO. 1, JANUARY 2007
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Effect of F2 Postmetallization Annealing on the Electrical and Reliability Characteristics of HfSiO Gate Dielectric Man Chang, Minseok Jo, Hokyung Park, Hyunsang Hwang, Member, IEEE, Byoung Hun Lee, Member, IEEE, and Rino Choi
Abstract—The effects of fluorine (F2 ) annealing on the electrical and reliability characteristics of HfSiO MOSFETs were investigated. Compared with a control sample annealed in conventional forming gas (H2 /N2 = 4%/ 96%), additional annealing in a fluorine ambient (F2 /Ar = 0.3%/ 99.7%) at 400 ◦ C for 20 min improved the electrical characteristics such as lower interface trap density and higher transconductance. In addition, MOSFET samples annealed in a F2 ambient exhibited less degradation under hot-carrier stress and positive bias temperature stress. These improvements can be explained by fluorine incorporation at the high-k/Si interface, which was confirmed by an X-ray photoelectron spectroscopy analysis. Index Terms—Bias temperature instability, fluorine annealing, high-k, hot-carrier stress (HCS).
I. I NTRODUCTION
A
LTHOUGH hafnium-based high-k gate dielectrics have been intensively studied to replace SiO2 as the gate dielectric, the bias temperature instability, high interface state density, and hot-carrier-induced degradation are still major concerns. In particular, the bias temperature instability is related to the generation of interface traps and bulk traps [1]. It was known that fluorine incorporation in the SiO2 gate dielectrics improves the electrical and reliability characteristics by replacing Si–H bonds with Si–F bonds [2]–[7]; however, an excess amount of fluorine incorporation increases oxide thickness. It is known that excessive fluorine annealing replaces Si–O bonds with Si–F bonds, which generates reactive oxygen atoms. The oxygen atoms, which react with silicon substrate, form thick interfacial SiOx layer [2], [3]. To incorporate fluorine in the oxide, the conventional methods are fluorine implantation and plasma treatment in a fluorine-containing gas [4]–[6]. However, these processes can cause additional damage due to the high energetic plasma treatment and ion implantation. To minimize damage, thermal annealing in fluorine ambient is desirable.
Manuscript received September 18, 2006. This work was supported by Poong San Microtec, Korea. The review of this letter was arranged by Editor K. de Meyer. M. Chang, M. Jo, H. Park, and H. Hwang are with the Department of Materials Science and Engineering, Gwangju Institute of Science and Technology, Gwangju 500-712, Korea (e-mail:
[email protected]). B. H. Lee is an IBM assignee with SEMATECH, Austin, TX 78741 USA. R. Choi is with SEMATECH, Austin, TX 78741 USA. Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2006.887941
Fig. 1. XPS fluorine depth profile of the F2 -annealed sample. Fluorine was incorporated at the high-k/Si interface. Inset shows the F peak in fluorineannealed sample.
In this letter, the effect of thermal annealing in a F2 ambient on high-k MOSFETs samples is investigated.
II. E XPERIMENTS After a standard wafer cleaning and 1-nm-thick chemical oxide growth, an 4-nm HfSiO (20% SiO2 ) layer was deposited by atomic layer deposition (ALD) using precursors Hf[N(CH3 )C2 H5 ]4 and Si[N(CH3 )C2 H5 ]4 with O3 as the oxygen source. For a gate electrode, a ALD TiN layer and amorphous silicon layer were deposited. A source/drain (S/D) was formed by As implantation, followed by activation annealing in a N2 ambient. Conventional forming gas (H2 /N2 = 4%/96%) annealing was performed over 450 ◦ C for all samples. For some samples, additional fluorine annealing was performed at 400 ◦ C for 20 min in fluorine ambient (F2 /Ar = 0.3%/99.7%). The equivalent oxide thickness (EOT) value was extracted by the capacitance–voltage (C–V ) method, considering quantum effect. The interface trap density was calculated using the charge-pumping (CP) method in fixed amplitude mode. The entire measurement process was controlled by the Labview program, which provided constant measurement intervals and an automatic data analysis. X-ray photoelectron spectroscopy (XPS) analysis was performed to check fluorine profile in the high-k layer.
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IEEE ELECTRON DEVICE LETTERS, VOL. 28, NO. 1, JANUARY 2007
Fig. 2. (a) Nit of an nMOSFET measured by the CP technique. (b) C–V curves measured at a frequency of 100 kHz. (c) Linear drain–current Id and transconductance gm versus gate voltage Vg after the F2 annealing.
III. R ESULTS AND D ISCUSSION To confirm the fluorine incorporation after the F2 annealing, XPS depth profiling was performed, as shown in Fig. 1. For the XPS analysis, 10-nm hafnium oxide (HfO2 ) deposited on Si substrate was used. Fluorine annealing was performed at 400 ◦ C for 20 min with F content of 0.3%. Based on the XPS data, we confirmed fluorine incorporation at HfO2 /Si interface. F1s peak (Si–F) was also observed at the binding energy of 685.5 eV [9]. In the case of the F2 plasma-treated sample, fluorine atoms were uniformly distributed in the HfO2 bulk and interface [7], whereas F2 thermal-annealed sample showed fluorine atoms piled up at the high-k/substrate interface [8]. The interface state density (Nit ) was measured by the CP method at a frequency of 500 kHz, as shown in Fig. 2(a). The F2 -annealed sample exhibited a lower Nit value than that of the FG-annealed sample. These results indicate that conventional FG annealing was not sufficient to passivate the highk/silicon interface [10]. Thus, it clearly shows that additional fluorine annealing resulted in a lower interface state density by passivating silicon dangling bond at the interface. In addition, it can be concluded that strong Si–F bonds (5.73 eV) was formed by a replacement of the weak Si–H bonds (3.18 eV) during fluorine annealing [3]. As shown in Fig. 2(b), optimum fluorine annealing did not affect the EOT value, which indicates no oxide regrowth at the interface and sufficient passivation of interface traps. Fig. 2(c) shows the improved linear drain– current Id and transconductance gm after the F2 annealing, which can be explained by the lower interface state density.
Fig. 3. Threshold voltage shift as a function of stress time under an HCS condition (Vg = Vd = 1.5 and 2.0 V). The inset shows the degradation of gm after 1000-s HCS.
To investigate the reliability of HfSiO nMOSFET after the fluorine annealing, the threshold voltage shift ∆Vth and degradation of transconductance ∆gm were measured under hotcarrier stress (HCS) condition for 1000 s, as shown in Fig. 3. The worst degradation condition (Vg = Vd = 1.5 and 2.0 V) was chosen for the high-k MOSFETs [11]. Compared with a control sample, the sample annealed in a F2 ambient showed less ∆Vth and less degradation of ∆gm /gm,max under HCS. These improvements can be explained by the stronger Si–F bonds than the Si–H bonds under HCS conditions [5].
CHANG et al.: EFFECT OF F2 ANNEALING ON ELECTRICAL AND RELIABILITY CHARACTERISTICS OF MOSFETs
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sample showed improved reliability characteristics under the HCS and PBTI. The improvements can be explained by fluorine incorporation at high-k/substrate interface, leading to the formation of strong fluorine bonds. Fluorine annealing shows some promise for future high-k gate dielectric applications. ACKNOWLEDGMENT The authors would like to thank SEMATECH for providing samples. R EFERENCES
Fig. 4. PBTI characteristics under a gate bias of 1.5 V. PBTI were measured with varying stress temperatures (25 ◦ C, 85 ◦ C, and 150 ◦ C).
As shown in Fig. 4, positive bias temperature instability (PBTI) characteristics were measured under the stress gate bias of 1.5 V with varying stress temperatures from 25 ◦ C to 15 ◦ C. The F2 -annealed sample showed less ∆Vth than that of the FG-annealed sample. After PBTI stress for 1000 s, the differences in the ∆Vth value between the F2 -annealed sample and the control samples (∆Vth,FG − ∆Vth,fluorine ) were 8.6, 6.9, and 4.9 mV at 25 ◦ C, 85 ◦ C, and 150 ◦ C, respectively. However, under the PBTI stress conditions, CP measurement shows no significant difference for both control and F2 -annealed sample (not shown). This means that positive ∆Vth for PBTI measurement is mostly related with bulk-trapped charges rather than interface-trapped charge [7], [8], [12]. The origin of improved PBTI reliability is not clear. Although no significant fluorine incorporation at oxide bulk was observed by XPS analysis, fluorine annealing might passivate near interface trap, which might improve PBTI reliability. IV. C ONCLUSION The effect of fluorine annealing on electrical and reliability characteristics of high-k MOSFET was investigated. By optimizing fluorine concentration and annealing temperature, we can improve the electrical characteristics such as Nit , Id , and gm without increasing the EOT. In addition, the F2 -annealed
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