Effective Data Rate on Ethernet Interfaces For ...

J Control Autom Electr Syst (2013) 24:806–815 DOI 10.1007/s40313-013-0075-5

Effective Data Rate on Ethernet Interfaces For Embedded Systems: A Comparative Analysis Fabrício P. V. de Campos · Marcello L. R. de Campos · Carlos H. N. Martins · Moisés V. Ribeiro

Received: 20 December 2012 / Revised: 29 July 2013 / Accepted: 9 August 2013 / Published online: 6 September 2013 © Brazilian Society for Automatics–SBA 2013

Abstract This contribution proposes, discusses and analyzes different solutions for the implementation of Ethernet interfaces for embedded systems that show realistic compromise between performance and development cost. Two well-known approaches based on low cost microcontrollers are discussed. In the sequel, two novel approaches, which are based on field programmable gate array (FPGA), are introduced. The comparison analysis of the suitability of the proposed approaches against those based on microcontrollers is addressed on two case studies. The first case study, which makes use of a prototype of communication interface for a webserver application, points out that the proposed approaches based on FPGA devices can offer the best tradeoff between performance and development cost. Also, it reveals that the flexibility offered by FPGA devices is a powerful tool to allow fast update of the firmware and hardware of the embedded systems. The second case study, which analyzes the solutions in a prototype of an internet-based authentication solution for biometric access control system, indicates that the highest bit-rate can only be achieved if the commu-

F. P. V. de Campos (B) · M. L. R. de Campos Federal University of Rio de Janeiro/COPPE/Rio de Janeiro, Rio de Janeiro, RJ, Brazil e-mail: [email protected] M. L. R. de Campos e-mail: [email protected] F. P. V. de Campos · C. H. N. Martins · M. V. Ribeiro Federal University of Juiz de Fora/PPEE/Juiz de Fora, Juiz de Fora, MG, Brazil C. H. N. Martins e-mail: [email protected] M. V. Ribeiro e-mail: [email protected]

123

nication interface of an embedded system is prototyped with the proposed approach based on an FPGA device. Keywords

Ethernet · Embedded systems · FPGA

1 Introduction According to the Institute of Electrical and Electronics Engineers (IEEE) and the Cisco Systems Inc., in 2020 there will be 50 billion “smart” devices connected to the Internet (Pretz 2013; Evans 2011). The majority of them will be low cost and green devices for embedded systems, automation, vehicular communications, cell phones, smart phones, machine to machine (M2M) communications, internet of things (IoT), and smart grids. There are several technologies that allow these devices to be connected to the internet. Among them, Ethernet (Qian et al. 2009; Sommer et al. 2010) has emerged as a layer two (L2) standard that is widely deployed by industry. Microwebserver, serial/Ethernet converters RS232/SPI (SPI—serial peripheral interface), and industrial Ethernet converters RS485/CAN (CAN—controller area network) are the most common applications based on microcontrollers which make use of Ethernet interface. Applications involving web servers are described in Joshi et al. (2009), while the ones involving data communication are discussed in Xu and Zhu (2009), Wang et al. (2008), Richard and Kelly (2007). Applications for embedded systems, multimedia, and vehicles are addressed in Moyne and Tilbury (2007), Marin et al. (2009), Cucinotta et al. (2009), Maestro and Reviriego (2010), Sommer et al. (2010), Ferrari et al. (2010). Regarding embedded systems, current technology is based on low cost microcontrollers, which have limitations of resource and processing capacity for Ethernet-based interfaces.

J Control Autom Electr Syst (2013) 24:806–815

To guarantee quality of service (QoS) in high data rate applications, the costs of Ethernet technologies may become prohibitive for embedded systems. Hence, there is a pressing demand for the development of solutions which enable high effective data rates at low cost, for both Ethernet and real-time Ethernet. Nowadays, this necessity has been increased by the introduction of new technologies, and devices that are environmentally friendly and sustainable (Donnellan et al. 2011). Several discussions about Ethernet are presented in the literature (Bot 2004; Felser 2005; Sofia 2009; Sommer et al. 2010), but all of them are based on the specifications of systems and protocols and do not consider processing capacity, hardware resource limitation, and cost. Just a few works present the achieved effective data rate, however, none of then compare different solutions (Prabahar and Prabhu 2011; Ruimei and Mei 2010; Drumea and Svasta 2011; Nguyen et al. 2007). To deal with this gap, this contribution aims at providing a comparative analysis among different solutions for prototyping low cost and high effective data rate Ethernet interfaces. In this regard, two solutions for the implementation of Ethernet interfaces with field-programmable gate array (FPGA) softcore processors (Altera 2012; Zhen et al. 2007) are investigated. In addition, comparative analysis with prototypes of Ethernet-based solutions that make use of ARM (advanced reduced instruction set computing machines) microcontroller (Atack and Someren 1993) and serial/Ethernet converter (Tibbo 2012) are addressed. The comparison analysis of the suitability of the proposed approaches against those based on microcontrollers is addressed on two case studies. The first case study, which makes use of a prototype of communication interface for a webserver application, points out that the proposed approaches based on FPGA devices can offer the best tradeoff between performance and development cost. Also, it reveals that the flexibility offered by FPGA devices is a powerful tool to allow fast update of the firmware and hardware of embedded systems. The second case study, which analyzes the solutions in a prototype of an Internet-based authentication solution for fingerprint access control system, indicates that the highest bit-rate can only be achieved if the communication interface of an embedded system is prototyped with the proposed approaches based on an FPGA device. Overall, the analysis shows that it is possible to design low cost and high effective data rate Ethernet interfaces with FPGA-based solution for embedded systems. Also, it reveals directions for specifying, designing, and prototyping Ethernet interfaces in embedded systems in terms of development time, solution cost, and effective data rate. This work is organized as follows. Section 2 focuses on the formulation of the problem. Section 3 deals with four solutions to implement Ethernet interfaces, being the two existing ones based on microcontrollers and the two proposed ones based on FPGA. Section 4 presents a study that indicates

807 Table 1 Non-volatile memory requirements for several applications in a Ethernet-based embedded systems.

Application

Size (KB)

(a) UDP

16

(b) TCP

25

(c) HTTP

30

(d) SMTP

30

(e) HTTP + DHCP

38

(f) HTTP + SMTP+ DHCP + UDP

50

the relation between cost and effective data rate. Section 5 analyzes, comparatively, the performance of the solutions proposed considering the effective data rate in a case study. Final considerations are pointed out in Sect. 6. 2 Problem Formulation Over the past years, the number of devices deploying Ethernet interface increased considerably. However, several devices, such as control devices, sensors, actuators, communication interfaces, multimedia devices, among others, make use of limited hardware architectures, both in memory and processing capacity, which result in difficult to implement Ethernet interfaces. To help with the choice of the controller device, Table 1 illustrates the use of non-volatile memory for different types of application in embedded system (Silicon 2012), that are named as follows: (a) custom application based in user datagram protocol (UDP); (b) custom application based on telnet terminal or transmission protocol control (TCP); (c) application based on web-browser, hypertext transfer protocol (HTTP); (d) custom application based on e-mail—simple mail transfer protocol (SMTP); (e) HTTP application and automatic net configuration—DHCP (dynamic host configuration protocol); (f) custom application with HTTP, SMTP, DHCP, and UDP. The following characteristics have made Ethernet standard very attractive to embedded systems: versatility; easy of usage; large number of available equipments; high data rate capacity; access control to the Internet; reach long distances; electrically isolated interfaces; viable cost; and QoS guarantee for real-time applications. The Ethernet protocol specifies the medium access control (MAC) layer, the physical (PHY) layer and the cables. Ethernet protocols are: IEEE 802.3 (10Base-T: 10 Mbps), IEEE 802.3u (Fast Ethernet: 100 Mbps), IEEE 802.3z (Gigabit Ethernet: 1 Gbps), IEEE 802.3ae (10 Gigabit Ethernet: 10 Gbps) and IEEE 802.3ba (40 Gbps and 100 Gbps). In addition, there is a standard for real-time Ethernet (RTE) (Decotignie 2005; Felser 2005; Skeie et al. 2006). RTE attends the industrial needs which present repetitive and deterministic behavior.

123

808

J Control Autom Electr Syst (2013) 24:806–815 i)

CORE

ii) MAC

iii)

iv)

i)

v)

PHY

ii)

Ethernet MAC

iii)

#1

ARM7 CORE

#2

uC CORE

Ethernet MAC

PHY

#3

FPGA SOFT CORE

Ethernet MAC

PHY

#4

FPGA SOFT CORE

Ethernet MAC

PHY

iv)

v)

PHY

Fig. 1 Basic blocks of Ethernet interface for embedded systems.

The majority of the solutions to embedded systems is developed under the architecture of low cost microprocessors with limited processing capacity and an 8-bit architecture, and, as a consequence, they presents hardware and processing capacity limitations for providing Ethernet interfaces. Solutions at an acceptable cost have been developed based on ARM architecture with 32 bits. Solutions based on ARM deploy the system-on-chip concept that provides hardware resources for a wide range of applications demanding a minimum package of functionalities, low energy consumption, and accessible cost. However, there is still a gap, which are the embedded applications provided with Ethernet interface, requiring high data rates for both real and non-real-time applications. In general, Ethernet interfaces for embedded systems can be divided into five parts, see Figure 1, namely: (i) CORE, processor responsible for the application; (ii) MAC Ethernet; (iii) PHY Ethernet; (iv) Coupling, to guarantee isolation, and (v) RJ-45 connector. Considering the development of Ethernet interfaces for embedded systems, two main investigation questions are of major interest: • How to trade cost and development complexity/time versus effective data rate? • How to offer high data rate Ethernet interface with low cost? The first one is analyzed in Sect. 4, from a case study where four solutions are prototyped and the implementation cost, effective data rate, and development complexity are discussed. To discuss the second investigation question, this contribution discusses and analyzes, in Sect. 5, the proposal of new solutions based on FPGA devices, aiming at Ethernet interfaces with high effective data rates and low cost for embedded systems.

3 Solutions for Ethernet Iplementation in Embedded Systems The block diagrams of the implemented solutions, discussed in this contribution for Ethernet interfacing, are illustrated in Fig. 2, being the ones numbered #1 and #2 more commonly found in the literature and commercially available. Both of them make use of low cost microcontrollers and are differen-

123

Legend: Integrated Blocks

Fig. 2 Solutions for Ethernet implementation in embedded systems: (1–2) existing solutions and (3–4) proposed solutions

tiated by the microcontroller integration level of the Ethernet protocol. The difference between solutions #3 and #4 are also on the integration level of the Ethernet interface with a FPGA device. Once the comparative analysis between these solutions necessarily requires their implementations, solutions listed below were not only developed, but also prototyped. • Solution #1 : ARM 7 Microcontroller with native Ethernet; • Solution #2 : ATMEGA 128 Microcontroller with TIBBO EM-100 Module; • Solution #3 : FPGA with NIOS II and MAC/PHY layers based on LAN91C11 component; • Solution #4 : FPGA with NIOS II, MAC TSE and PHY layer based on Mavell 88E1111 component.

3.1 Solution #1: ARM 7 Microcontroller with Native Ethernet The ARM architecture restructures a 1983 project of Arcon Computers, whose objective was to introduce a microcontroller similar to MOS Technology 6502 processor. Besides the MOS Technology 6502 processor, the ARM architecture was influenced by Berkeley RISC (Limachia and Kothari 2012). The first version introduced to the market was ARM 2, in 1986. It became famous and popular for introducing high performance if compared with other microcontrollers of similar cost. ARM microcontroller presents the following characteristics: fixed instructions of 32 bits; 15 general propose 32-bit

J Control Autom Electr Syst (2013) 24:806–815

809

Fig. 3 The Development board based on ARM7 LPC2388 (Solution #1)

Fig. 4 The prototyped Board of the serial/Ethernet based on Tibbo EM-100 module (Solution #2)

registers; memory-mapped I/O peripherals supporting interruptions; 3 and 5 pipeline stages. Some ARM processors also include display controllers, universal serial bus (USB) ports, pulse width modulation (PWM) outputs, digital to analog (DA) and analog to digital (AD) converters, Ethernet interface, among other peripherals. Hence, ARM platform allows high performance, low cost, high integration level and reduced developing time. Nowadays, ARM microcontrollers are widely used in embedded system devices (ARM 2012b). The native Ethernet microcontroller used to establish communication via Ethernet is based on model ARM7 LPC2388. Figure 3 presents the development board in which solution #1 is prototyped. It is constituted by a ARM7 LPC2388, a DP83848VV component (specific external component to only implement Ethernet PHY layer) and a MagJack connector. The MAC layer algorithms are executed by the ARM microcontroller. This ARM7 LPC2388 microcontroller, produced by NXP (Phillips), operates at 72 MHz (64 DMIPs) clock speed and owns 16 KB buffer for Tx and Rx and 10/100 Mbps (ARM 2012a).

because it is possible to use serial/Ethernet converters. Nowadays, the majority of applications use this kind of solution to deploy Ethernet interface because it is cheap and the development time is short. Its only disadvantage is the serial communication rate of the microcontroller limited to 115.2 Kbps. The serial/Ethernet converter used in the solution #2 is the EM-100 module, produced by Tibbo (2012). It contains a TTL standard serial port (half or full duplex) that reaches data rates up to 115.2 Kbps and a 10-BaseT Ethernet. The module also has a 512 KB buffer for Rx and Tx modes. For the tests, an EM-100 Tibbo board, an RJ-45 Ethernet connector, Tx/Rx pins and the board power source (5VDC and 40mA), which is shown in Fig. 4, have been prototyped to implement solution #2. Note that the RJ-45 connector can be simpler than the one for the other solutions, once the transformer is integrated into the EM-100 module, see Fig. 2.

3.2 Solution #2: ATMEGA 128 Microcontroller with TIBBO EM-100 Module The ATMEGA 128 is a low cost 8-bit microcontroller based on AVR architecture from Atmel (2012), originally developed in 1996. The main features of this microcontroller are: 133 8-bits instructions; general propose 8-bit registers; I/O peripheral supporting interruptions; instructions executed in 1 clock period; 128 KB flash memory; 4 KB electrically erasable programmable read-only memory (EEPROM) memory; and 4 KB static random access (SRAM) memory. This microcontroller, as other low cost ones, does not have Ethernet interface. However, it does not prevent its use,

3.3 Solution #3: FPGA with NIOS II and MAC/PHY Layers Based on LAN91C11 Component FPGA is a programable silicon device that is used for data processing, and can be configured as the user (programmer) wishes. FPGA can be divided into three main components: input and output blocks (IOB—in/out blocks), configurable logical blocks (CLB), and interconnection switches (switch matrix). Using FPGA, relatively big and complex logical circuits can be implemented with logical cell arrays, also named CLB, linked to an integrated circuit. These blocks implement logical functions and can communicate with each other. Consequently, FPGA offers high performance when compared to conventional processors. However, the development time can be longer. One of the greatest advantages of FPGA is the implementation of processors as softcore. Softcores are differ-

123

810

ent from conventional microprocessors, since their internal architecture is reconfigurable and they are synthesized on the FPGA. These softcore processors are developed with hardware description language (HDL), very high speed integrated circuit hardware description language (VHDL) or Verilog language. Once designed on the FPGA, this processor can be programmed using high level language, such as “C”, which reduces the time and complexity of project development for embedded systems. Softcore allows, for example, change of the processing core, targeting the input of new peripherals, even after the project ends. The use of this processor reduces the complexity of coding to the level of the microcontrollers mentioned in sections 3.1 and 3.2. NIOS II is a softcore processor developed by Altera, which can be programmed in “C”, “C++” or Assembly (Yiannacouras et al. 2007; Jussel 2004; Altera 2012). NIOS II uses RISC architecture, with 32-bit instructions. The main characteristics of NIOS II/f are: memory management unit (MMU) or memory protection unit (MPU); access to over 2 GB of addressing space; tightly coupled memory for data instructions; six pipeline stages to obtain the best effective processing rate; hardware implementation of multipliers that are capable of doing operations in only one clock cycle; division implemented on hardware; more than 256 custom instructions; number of hardware accelerators is limited by the FPGA capacity; and a JTAG depuration module. The solution #3 uses an FPGA device with an external MAC layer to promote Ethernet communication, as illustrated in Fig. 5. The MAC controller is implemented in the NIOS II softcore. The prototype is composed of an EP2S601020C4 FPGA device from Stratix II family, an LAN91C111 component to implement PHY and MAC Ethernet layers, and an RJ-45 connector associated with a MagJack coupling transformer. Although this solution simplifies the project, it increases the final cost of this solution. In fact the LAN91C111 can cost up to 20 times more than a component which includes only the Ethernet PHY layer, see Fig. 2.

J Control Autom Electr Syst (2013) 24:806–815

Fig. 6 The diagram of the solution based on FPGA with external MAC Ethernet (Solution #4)

The LAN91C111 component has 8 KB of internal memory for Tx and Rx, operates at 10/100 Mbps, which allows data streaming, and supports full duplex communication. 3.4 Solution #4: FPGA with NIOS II, MAC TSE and PHY Layer Based on Mavell 88E1111 Component Solution #4 uses an FPGA device with internal MAC layer to promote Ethernet communication, see Fig. 6. This solution is constituted of the FPGA EP3SL150F1152C2 from the Stratix III family (Altera 2012); an external and specific integrated circuit (IC) to implement only PHY Ethernet layer, component Marvell 88E1111; an MagJack connector, see Fig. 2. To implement MAC Ethernet layer on FPGA, TSE MAC (triplespeed Ethernet MAC) (Altera 2012) is used, which allows half and full duplex communications, 10/100/1000 Mbps and operates with buffers inside the FPGA. Note that, the size of such buffers can vary between 4 KB and 4 MB for both Rx and Tx modes. TSE Ethernet MAC layer is parameterized by NIOS II and has three data buses (TSE 2012): (1) Avalon streaming bus, for data sending (source); (2) Avalon streaming bus, for data reception (sink); (3) Avalon data bus, for initial parameterization and control of TSE MAC.

4 Case Study 1: Web-server: Cost Versus Effective Data Rate

Fig. 5 The diagram of the solution based on FPGA with internal MAC Ethernet (Solution #3)

123

In order to assess and compare cost and development complexity against effective data rate among the proposed solutions and the ones mentioned in the literature, an HTTP web-server application was developed. In this application,

J Control Autom Electr Syst (2013) 24:806–815

811

Table 2 Effective data rates in Mbps

Table 3 Comparison among analyzed solutions

Solution

#1

#2

#3

#4

Solution

#1

#2

#3

#4

HTTP

0,390

0,060

0,763

2,230

Implementation complexity

M

L

M

M

Development time

M

L

H

H

Fig. 8 Fingerprint authentication system

Fig. 7 Comparison between normalized cost and effective data rate for the analyzed solutions

each one of the solutions hosted an HTML homepage, which allowed data upload (client → server). The data was stored in a secure digital (SD) card. The application consists of a realtime operating system (RTOS), a file system application, and a application programming interface (API) to interface with the TCP/IP protocol. Table 2 presents the results of the effective data rate for the solutions described in Sect. 3. Regarding performance, the FPGA-based solutions offer expressive improvement, reaching 2.23 Mbps in this case study. Another important parameter for the analysis is the implementation cost, because it guarantees good market acceptance. In this regards, the costs of each solution were obtained, considering unitary costs of all components in each solution, in American dollars (Digi-Key 2012). Delivery and tax costs were not considered. Despite the cost reduction that can be achieved if thousands of units are manufactured, this analysis portrays a good view of what can be expected. Figure 7 addresses a comparison between the costs of each solution and the effective data rates. The costs are normalized by solution #2, because it presents the greatest value (US$72,52). Even though it is well known that applicationspecific integrated circuit (ASIC) devices can reduce production costs in up to 20 times, this solution was not considered in this work. As it can be seen, solution #4 presents the best relation between effective data rate and total cost. In this graph it can also be observed that apart from being the most used solution of embedded systems, solution #2 presents the worst relation among the chosen solutions. Nevertheless, it can be easily integrated to embedded systems, while other solutions are more complex to be integrated. The presented

results indicate advantages of the proposed solutions because they offer an interesting tradeoff between effective data rate and cost. With the aim of giving relevant information for decision making, some observations consolidated during this research are highlighted in Table 3. Note that L, M, and H mean low, medium, and high, respectively.

5 Case Study 2: Authentication via Ethernet: Analysis of the Effective Data Rate This section presents an analysis of the effective data rate for the solutions #3 and #4. A case study based on the implementation of a fingerprint authentication system with Ethernet interface is addressed to verify the highest effective data rate. 5.1 Fingerprint Authentication System To assess the effective data rate of the proposed solutions, a prototyped fingerprint authentication system is depicted in Fig. 8. In this application, client stations on embedded systems (FPGA-based fingerprint reading devices) communicate through an Ethernet interface with a server (personal computer—PC). The server stores the information of each user’s fingerprint. If the scanned fingerprint matches the one stored on server, an authentication message is sent to the fingerprint-reading device through the Ethernet interface. For this application, data transfer with fingerprint authentication as well as data transfer without fingerprint authentication were considered. For both kind of data transfer, a TCP/IP socket connection has been deployed. Through this connection, the client sends a authentication request message to the server, which is executed in Linux platform, and then the authentication response message is sent to the embedded system. By doing so, it is possible to analyze the peak

123

812

J Control Autom Electr Syst (2013) 24:806–815

of the effective data rate of the established connection. The effective data rate is expressed by R=

n B (N T X + N R X ) bps, tT X + t R X

(1)

where n B = 8 is the number of bits per byte, N T X , and N R X are the number of sent and received bytes, tT X and t R X are the time intervals used to send fingerprint authentication request and response message, respectively. The choice of the TCP/IP package size, corresponding to the maximum transmission unit (MTU), was carried out to avoid the package fragmentation. The measurements of application execution time were made, by the FPGA, to obtain the effective data rate, because the execution of several processes by the PC interferes with the measurement of effective data rate. Algorithm 1 presentes the main source code of the functions for message sending and receiving.

In order to enable the reproduction of these tests, the source code of the server, running in a PC, and the source code of the client, based on the FPGA device of the embedded system, are provided. Algorithm 2 presentes the source code for the server application, in which the line #11 check for fingerprint authentication. Algorithm 2 Server application # define # define

s i z e 1 80 size2 1400 ... i n t main () { c h a r sent [ size1 ] , r e c e i v e d [ s i z e 2 ] , a u t e n t i c [ s i z e 2 ]; i n t sock ; m e n s e t ( autentic , ’ a ’ , size2 ) ; s o c k = s o c k e t ( PF_INET , S O C K _ S T R E A M , IPPROTO_TCP ); ... r e c e i v e _ e t h ( sock , r e c e i v e d ) ; i f (! s t r c m p ( recebido , a u t e n t i c ) ) s e n d _ e t h ( sock , sent ) ; r e t u r n (0) ; }

Algorithm 1 Functions for message sending and receiving int

s e n d _ e t h ( i n t sock , c h a r s t r e a m [ s i z e 1 ]) { i f ( send ( sock , stream , size1 , 0) != s i z e 1 ) { p r i n t f ( " E r r o r wile s e n d i n g stream ! \n"); exit (1) ; }

} int

r e c e i v e _ e t h ( i n t sock , c h a r s t r e a m [ s i z e 2 ]) { i f ( recv ( sock , stream , size2 , 0) != s i z e 2 ) { printf (" Error wile receiving authentication \n"); exit (1) ; }

}

1

6 7 8 9 10 11 12 13 14

2 3 4 5 6 7 8

Algorithm 3 presentes the source code for the NIOS II client application with fingerprint authentication. Algorithm 3 Client application with fingerprint authentication 1 2 3 4 5

9 10 11 12 13

Based on the aforementioned considerations, a fingerprint authentication application, coded with a “C” language for a Linux platform running in the PC, was developed to receive a message containing 1400 Bytes and send a fingerprint authentication message of 80 Bytes to the embedded system, if the received message is validated by the fingerprint authentication application. The following tests were executed: 1. FPGA in the embedded system sends a fingerprint authentication request message and receives a response message. Both sending and receiving times are measured by the FPGA. 2. FPGA in the embedded system is used to measure the time interval needed to send a message without requesting authentication response. Hence N R X = 0 and t R X = 0, that is, the authentication receiving time is not considered.

123

1 2 3 4 5

6 7 8 9 10 11 12 13

# define # define

s i z e 1 80 size2 1400 ... i n t main () { c h a r sent [ size1 ] , r e c e i v e d [ s i z e 2 ] , a u t e n t i c [ s i z e 2 ]; i n t sock ; m e n s e t ( autentic , ’ a ’ , size1 ) ; s o c k = s o c k e t ( PF_INET , S O C K _ S T R E A M , IPPROTO_TCP ); ... s e n d _ e t h ( sock , e n v i a d o ) ; r e c e i v e _ e t h ( sock , r e c e b i d o ) ; r e t u r n (0) ; }

Algorithm 4 presentes the source code for the NIOS II client application without fingerprint authentication response. Algorithm 4 Client application without fingerprint authentication 1 2 3 4 5 6 7 8 9 10 11

# define

size1 1400 ... i n t main () { c h a r sent [ size1 ]; i n t sock ; m e n s e t ( autentic , ’ a ’ , size1 ) ; s o c k = s o c k e t ( PF_INET , S O C K _ S T R E A M , IPPROTO_TCP ); ... s e n d _ e t h ( sock , sent ) ; r e t u r n (0) ; }

J Control Autom Electr Syst (2013) 24:806–815

813

Table 4 Maximum limit of the effective data rate of the TCP protocol (Mbps)

#3

#4

With fingerprint authentication response

2,9

11

Without fingerprint authentication response

4,0

29

Table 5 Maximum limit of the effective data rate at the IP protocol level

Solution #4 TSE MAC loopback

412 Mbps

nection). The control Avalon bus remained connected to the NIOS II system, enabling TSE MAC to be parameterized. As on this configuration the communication between layers L2 and the TCP/IP stack was interrupted, the FPGA IPMAC address relation became unknown by the address resolution protocol (ARP) table of the computers. Consequently, it was necessary to reestablish the IP-MAC relation. For the better understanding and for enabling the tests the command executed on the computer is as follows: arp − s < ip_fpga >< Mac_address_fpga >

Fig. 9 TSE MAC Ethernet in loopback

Table 4 presents the obtained values on the authentication tests, using proposed solutions #3 and #4, which are based on FPGA, see Sects. 3.3 and 3.4. Note that, the results reached with the use of sockets are lower than that ones specified for Ethernet interfaces running in a FPGA device (10/100/1000 Mbps). In fact, around 2.9 and 4 Mbps are achieved when the solution #3 with and without fingerprint authentications are, respectively, considered. For the solution #4, 11 and 29 Mbps are attained with and without fingerprint authentications, respectively. It means that the solution #4 is capable of offering the highest effective data rate, which is extremely high for modern embedded systems. 5.2 Maximum Effective Data Rate To verify the TSE MAC maximum effective data rate, the loopback configuration (Alachiotis et al. 2010) has been developed through an specific Verilog hardware, that is illustrated by a block diagram depicted in Fig. 9. The loopback configuration is a common test when using FPGAs because the parallelism characteristic of the FPGA device. When a data stream is sent to the FPGA device, it simply returns the same data stream, which enables the calculation of the time needed for this stream transmission and the calculation of the maximum effective data rate. The hardware was connected to the data bus (sink and source) and they were directly connected (loopback con-

The length of the sent data stream can be aleatory, but in order to simplify, a ping datagram of 1400 Bytes was chosen. The command can be executed in a Linux platform running in the PC, and the command used to generate this datagram is: ping < ip_fpga > −s1400 A software called Wireshark (Wireshark 2012; Wang et al. 2010) was used to verify this analysis. It was possible then to verify, by the Ethernet frame contents, that the transmitted data has the MAC address of the PC as source and the received data has MAC address of the FPGA, validating the application and the tests. The obtained result is presented in Table 5. The fact that the MAC was synthesized internally to the FPGA and, as a result, it enabled the design of a specific hardware for the assessment of the maximum limit of the effective data rate equal to 412 Mbps, which surpasses all the rates known up to these days. It has to be emphasized that the value of 412 Mbps would be unthinkable if other device, different from the FPGA configured as explained, were used. Note that disturbing factors and data traffic were note present in those tests because we have a direct connection between the FPGA board and the PC, if the FPGA board was connected to a switch or a hub, it may result in a lower effective data rate. In the literature, it is not found any low cost Ethernet solution for embedded systems that is close to this value, which is 3500 higher than the commonly used solutions with serial/Ethernet converters (115.2 Kbps) and approximately 43000 times higher than the 9600 bps, which dominate the embedded systems market today.

123

814

6 Conclusions This work discussed the implementation of four solutions for data communications based on Ethernet interfaces, when embedded systems are considered and show realistic compromise between performance and development cost. According to the analysis, the Solution #1, based on ARM7 32-bit Microcontroller, is appropriate for applications demanding low cost, low effective data rate and medium development time. Regarding the Solution #2, based on low cost 8-bit microcontroller, it was recognized that it is appropriated for applications requiring low cost, very low effective data rate and the shortest development time. On the other hand, the Solution #3, based on FPGA and a external MAC layer controller, is appropriated for applications that demand high effective data rate without a severe restriction on cost and development time. Finally, the Solution #4, based on FPGA and a on FPGA implementation of MAC layer controller is highly recommended for embedded systems demanding very high effective data rate with the reasonable compromise between effective data rate, development time and cost. It could be demonstrated that solutions #2 and #3, which are based on FPGA, can offer considerable gains for embedded systems demanding high effective data rates. In fact, such solution are capable of reaching data rates as high as 29 Mbps, with the possibility of reaching effective data rates around 412 Mbps. The comparison analysis among development time, effective data rate, and cost yields the conclusion that FPGA-based solutions are, among the chosen solutions, promising ones for devising new generations of embedded systems. Overall, the analysis, discussed in this contribution, highlighted that it is possible to design low cost and high effective data rate Ethernet interfaces with FPGA-based for embedded systems. Also, it reveals directions for specifying, designing, and prototyping high data rate Ethernet interfaces in embedded systems with realistic compromise among development time, solution cost, and effective data rate. Acknowledgments The authors would like to thank CAPES, CNPq, FAPEMIG, FINEP, INERGE, and SMART INOVE for their financial support.

References Alachiotis, N., Berger, S. Stamatakis, A. (2010). Efficient pc-fpga communication over gigabit ethernet. In 10th IEEE international conference on computer and information technology, CIT 2010, Bradford (pp. 1727–1734). Altera. (2012). Altera training material. http://www.altera.com. Arm, C. (2012a). Mcb2300 evaluation board populated with an lpc2388. http://www.keil.com/mcb2300/mcb2388.asp. Arm, C. (2012b). Semiconductor intellectual property (ip) supplier, USA. http://www.arm.com/.

123

J Control Autom Electr Syst (2013) 24:806–815 Atack, C., & Someren, A. V. (1993). The Arm Risc Chip: A Programmer’s Guide. Boston, MA: Addison Wesley. Atmel. (2012). Atmel. http://www.atmel.com. Bot, S. (2004). Key technical considerations when using ethernet solutions in existing atm and frame relay networks. IEEE Communications Magazine, 42(3), 96–102. Cucinotta, T., Mancina, A., Anastasi, G., Lipari, G., Mangeruca, L., Checcozzo, R. & Rusina, F. (2009). A real-time service-oriented architecture for industrial automation. IEEE transactions on industrial informatics 5(3), 267–277. Decotignie, J.-D. (2005). Ethernet-based real-time and industrial communications. Proceedings of the IEEE, 93(6), 1102–1117. Digi-Key, C. (2012). Electronic components distributor. http://www. digikey.com. Donnellan, B., Sheridan, C., & Curry, E. (2011). A capability maturity framework for sustainable information and communication technology. IEEE Computer Society: IT Professional Jornal, 13(1), 33–40. Drumea, A. Svasta, P. (2011). Designing low cost embedded systems with ethernet connectivity. In IEEE international symposium for design and technology in electronic packaging (SIITME) (pp. 217– 220). Evans, D. (2011). How the next evolution of the internet is changing everything. CISCO White Paper, 4(11) Felser, M. (2005). Real-time ethernet: Industry prospective. Proceedings of the IEEE, 93(6), 1118–1129. Ferrari, P., Flammini, A., Rinaldi, S., & Sisinni, E. (2010). On the seamless interconnection of ieee1588-based devices using a profinet io infrastructure. IEEE Transactions on Industrial Informatics, 6(3), 381–392. Joshi, N., Dakhole, P. Zode, P. (2009). Embedded web server on Nios II embedded fpga platform. In IEEE 2nd international conference on emerging trends in engineering and technology (pp. 372–377). Jussel, J. (2004). Nios soft processor gets an update. IEEE Electronics Systems and Software Magazine, 2(3), 44. Limachia, M., & Kothari, N. (2012). Modeling and simulation of ARM processor architecture using systemC. Saarbrucken: LAP Lambert Academic Publishing. Maestro, J., & Reviriego, P. (2010). Energy efficiency in industrial ethernet: The case of powerlink. IEEE Transactions on Industrial Informatics, 57(8), 2896–2903. Marin, R., Leon, G., Wirz, R., Sales, J., Claver, J., Sanz, P., et al. (2009). Remote programming of network robots within the uji industrial robotics telelaboratory: Fpga vision and snrp network protocol. IEEE Transactions on Industrial Informatics, 56(12), 4806–4816. Moyne, J., & Tilbury, D. (2007). The emergence of industrial control networks for manufacturing control, diagnostics, and safety data. Proceedings of the IEEE, 95(1), 29–47. Nguyen, V.I., Benjapolakul, W. & Visavateeranon, K. (2007). A highspeed, low-cost and secure implementation based on embedded ethernet and internet for scada systems. In IEEE society of instrument and control engineers annual conference SICE, pp. 1692–1699. Prabahar, A. & Prabhu, R. (2011). Development of a distributed data collection system based on embedded ethernet. In IEEE international conference on communications and signal processing (ICCSP), pp. 97–99. Pretz, K. (2013). The next evolution of the internet. IEEE Magazine The institute, Vol. 50(5). Qian, K., Den Haring, D., Cao, L., Qian, K., Haring, D., & Cao, L. (2009). Ethernet applications and the future of the microcontroller. Embedded Software Development with C. New York: Springer US. Richard, H. -J., & Kelly, M. (2007). Using fpga’s to generate gigabit Ethernet data transfers and studies of the network performance of daq protocols. Real-time conference, 15th IEEE-NPSS, pp. 1–6. Ruimei, Z., & Mei, W. (2010). Design of arm-based embedded ethernet interface. IEEE International Conference on Computer Engineering and Technology (ICCET), 4, 268–270.

J Control Autom Electr Syst (2013) 24:806–815 Silicon, L. (2012). An292: Embedded ethernet system design guide. http://www.silabs.com/Support20Documents/TechnicalDocs/ an292.pdf. Skeie, T., Johannessen, S., & Holmeide, O. (2006). Timeliness of realtime IP communication in switched industrial ethernet networks. IEEE Transactions on Industrial Informatics, 2(1), 25–39. Sofia, R. (2009). A survey of advanced ethernet forwarding approaches. IEEE Communications Surveys Tutorials, 11(1), 92–115. Sommer, J., Gunreben, S., Feller, F., Kohn, M., Mifdaoui, A., Sass, D., et al. (2010). Ethernet a survey on its fields of application. IEEE Communications Surveys Tutorials, 12(2), 263–284. Tibbo, T. (2012). Em100 ethernet module. http://docs.tibbo.com/soism/ index.html?em120.htm. TSE. (2012). Triple speed ethernet TSE user guide. http://www.altera. com/literature/ug/ugethernet.pdf. Wang J., W. H. Z., Y. 2008. An fpga based slave communication controller for industrial ethernet. In 9th international conference on ICSICT 2008 (pp. 2062–2065).

815 Wang, S., Xu, D., & Yan, S. (2010). Analysis and application of wireshark in tcp/ip protocol teaching. International Conference on EHealth Networking, Digital Ecosystems and Technologies, 2, 269– 272. Wireshark. (2012). Wireshark protocol analyzer. http://www.wireshark. org/. Xu, M. Zhu, W. 2009. A research and design of ethernet real-time application bus based on fpga. IEEE international conference on scalable computing and communications (pp. 42–46). Yiannacouras, P., Steffan, J. G., & Rose, J. (2007). Exploration and customization of fpga-based soft processors. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(2), 266–277. Zhen, Z., Guilin, T., Zhi, D. & Zhiping, H. (2007). Design and realization of the hardware platform based on the nios soft-core processor. In IEEE 8th international conference on electronic measurement and instruments (pp. 4-865–4-869).

123