Efficiency Enhancement Techniques and a Dual-Band ... - IEEE Xplore

Efficiency Enhancement Techniques and a Dual-Band Approach in RF Rectifiers for Wireless Power Harvesting Pouya Kamalinejad, Kamyar Keikhosravy, Reza Molavi, Shahriar Mirabbasi, and Victor C.M. Leung University of British Columbia, Department of Electrical and Computer Engineering, Vancouver, BC, Canada, V6T 1Z4 {pkamali, keikhosr, reza, shahriar, vleung}@ece.ubc.ca IN+

This research is funded in part by the Natural Sciences and Engineering Research Council of Canada (NSERC)and the Institute for Computing, Information and Cognitive Systems (ICICS) at UBC. CAD support and access to technology is facilitated by CMC Microsystems.

978-1-4799-3432-4/14/$31.00 ©2014 IEEE

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I. I NTRODUCTION Wirelessly powered devices have recently gained an extensive attention in a wide range of applications including radiofrequency identification (RFID), wireless sensor networks, and biomedical implants. RF-to-DC converter (rectifier) is a key component in many such wirelessly powered devices whose main task is to convert the RF energy (received by the antenna) to a DC voltage that supplies power to the succeeding circuitry. the performance of the rectifier is evaluated by its power conversion efficiency (PCE) defined as the ratio of the average DC output power generated at the output of the rectifier (Pout ) to the average real input power available at the input of the rectifier (Pin ) [1]. In practice, where the maximum transmitted power to the system is regulated and the transmitter/receiver antenna geometry and the frequency of operation are dictated by the application, to increase the communication distance (which is typically desired in wireless power delivery applications) one should improve the PCE of the rectifier. In this paper, the mechanisms that directly influence the PCE of a rectifier are analyzed and PCE enhancement techniques through optimal biasing schemes are investigated. The rest of the paper is organized as follows: Section II provides a PCE analysis for RF CMOS rectifiers and presents

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Abstract—Efficiency enhancement techniques for CMOS rectifiers used in wireless power harvesting applications such as radio-frequency identification (RFID) or biomedical implants are overviewed. More specifically, three recently proposed efficiency enhancement techniques, namely, switched-capacitor gate-boosting scheme, auxiliary cell scheme and quasi-floatinggate biased scheme are presented in which based on the RF input level, the gate-drive voltage of switching transistors in the differential-drive rectifier architecture is enhanced. The proposed designs are laid out in standard 0.13-µm CMOS and their performance metrics are compared with the state-of-the-art differential structures. Through dynamically adjusting the input capacitance of the rectifier, a dual-band input matching scheme is presented which enables efficient power delivery at two distinct frequencies. Index Terms—High Efficiency, RF Rectifier, Wireless Power Harvesting, Wireless Power Delivery.

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(b) Fig. 1. Conventional differential rectifier. Architecture(a), PCE curve and forward-to-reverse current ratios of MP2 versus input voltage (b).

recently proposed efficiency enhancement techniques. Then, Section III describes the proposed dual-band input matching scheme. Simulation results for the dual-band rectifier are provided in Section. IV, and Section V concludes the paper. II. PCE A NALYSIS AND E FFICIENCY E NHANCEMENT T ECHNIQUES The conventional Dickson-based rectifier is a well-known architecture and extensive studies on efficiency enhancement techniques associated with this architecture exists in the literature. As a more efficient alternative for the Dicksonbased rectifiers, the differential-drive (4T-cell) architecture has been introduced which provides a superior efficiency without a significant added cost in terms of complexity [2-3]. At the circuit-level, PCE is mainly degraded as a result of two main phenomena, namely, forward voltage drop and reverse leakage current in switching devices (diodes or transistors). Numerous studies have been performed on the differential rectifiers to further improve their efficiency [4], [5]. For a fixed set of load requirement and frequency of

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PCE curve and average gate-drive voltage for Mp1 .

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operation, usually, the PCE of a rectifier peaks at a specific input voltage/power level and drops drastically if the input deviates from this optimal point. Note that deviation from the optimal input level occurs as the result of variations in the distance between the transmitter and the receiver (in electromagnetically coupled systems) or misalignments between the primary and secondary coils (in inductively coupled systems). To provide insight on how the reverse leakage current and forward voltage drop adversely affect the PCE, Fig. 1 shows the second stage of a differential rectifier along with the average forward-to-reverse current ratios of Mp1 versus the input voltage level. As shown, the ratio of the average forward current (desired) to the average reverse leakage current (undesired) peaks at the optimal input voltage. This optimal input voltage generates the optimal gate-drive voltages for the switching transistors as shown in Fig. 2. Mn1

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Note that for a fixed set of design parameters, only the optimum gate-drive voltage maximizes the average forward to reverse current ratios for NMOS and PMOS switches and hence the efficiency. To guarantee a high efficiency when the input deviates from the optimal point, a mechanism is required to bias the gate of the switches to a value close to the optimal value. This can be achieved through floating voltage sources as schematically shown in Fig.3. Generally the PCE curve of the differential rectifier could be shifted to the left (smaller input levels) and to the right (larger input levels) upon proper biasing of the gate of switches through floating voltage sources. Many techniques have been presented in the literature to implement the floating voltage sources in an area and power efficient manner. Fig. 4 shows three recently proposed efficiency enhanced techniques with an emphasis on efficient implementation of the floating voltage source. Fig. 4-(a) shows the switched-capacitor (SC) gate-boosting scheme for the second stage of a three-stage rectifier [6]. The generated intermediate voltages (gate-drive voltage) of the preceding stage ML1,U1 and succeeding stage ML3,U3 are used to drive the gate of switches in a timely manner. Moreover, these voltages are further boosted by the floating sources VGB1,2 implemented by a SC network. Such a scheme requires high-speed comparators to control the switches and require added area for the SC voltage sources. Fig. 4-(b) depicts the auxiliary-cell boosting scheme [7]. The auxiliary floating cells are connected to appropriate output nodes of the main rectifier and generate larger output voltages (and accordingly larger intermediate voltages) as they do not drive a resistive load. These voltages could be used as the boosted gate-drive voltages to drive the switches in the main rectifier. Such an scheme requires two auxiliary cells (with typically smaller capacitors and switches compared to the main rectifier) for each stage of the main rectifier. Fig. 4-(c) shows the quasi-floating-gate (QFG) boosting scheme [8]. The gate of the switches could be biased to any desired value through the very large resistor RLarge implemented by the reverse-biased p-n junction of the PMOS transistor in cut-off region [9], while the RF signal is coupled to the gates by CQFG . The bias voltages BiasP,N could be generated in accordance with the output voltage to facilitate a flat PCE curve for a wide range of inputs. QFG scheme does

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Proposed efficiency enhancement techniques. (a) SC gate-boosting architecture, (b) auxiliary floating cell architecture , (c)QFG architecture.

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TABLE I P ERFORMANCE S UMMARY AND C OMPARISON OF THE P ROPOSED E FFICIENCY E NHANCEMENT T ECHNIQUES WITH S TATE - OF - THE -A RT R ECTIFIERS

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rectifier (similar to [7]) such that the desired variation in Cin is obtained by adjusting the bias voltage of the NMOS switches in a fashion similar to [8]. The resonance frequency of the p matching network in Fig. 5 is given by fres = 1/2⇡ Ls Cin . For a fixed LS , to obtain a voltage matching for two input frequencies f1 and f2 (where f1 < f2 ), Cin has to be adjusted 2 such that Cin1/Cin2 = (f2/f1 ) . As shown in Fig. 7, Cin could be increased by connecting the gates of M1,2 to a higher voltage (Vbias ). The rectifier starts in mode-2 (fin = f2 ) with Cin = Cin2 (as the flip-flop controller has reset SW = 0) and the output voltage starts to build up. The transition from the higher frequency (f2 ) to the lower frequency (f1 ) is followed by a rapid drop in the output voltage of the rectifier (Vout ) since the matching network (LS ) does not resonate with Cin2 at f1 and the voltage matching is compromised. The drop in the output voltage is sensed by the comparator which subsequently sets SW = 1 through the controller. The increase in the gate bias voltage of M1,2 increases the input capacitance to C1 so that it resonates with

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In practice, it is the combined efficiency of the antenna and the rectifier (rectenna) that affects the overall performance of the power harvesting unit. Various architectures have been proposed to facilitate a dual frequency band rectenna [10-13]. However, most of the designs address the problem by using discrete (off-chip) antenna structures which generally need a relatively large footprint and thus may not be applicable to applications that require a small antenna (e.g., biomedical implants). It should be noted that the input impedance of a CMOS rectifier is a parallel combination of a capacitor Cin and a resistor Rin as shown in Fig. 5 [4]. Therefore, for a fixed antenna architecture, one could modify the value of the input capacitance (Cin ) to obtain the required matching at different frequencies. The resistive (real) part of the input impedance represents the average DC current drawn by the input. As shown in Fig. 6 for the first stage, the capacitive part of the input impedance accounts for the series combination of the coupling capacitors CC and the parasitic capacitances seen at Cpar , the input the intermediate node, Cpar . Note that for CC capacitance is dominated by Cpar in which the capacitance of Mn1 (CS,n1 ) is the biggest contributor. The value of CS,n1 is a function of its gate bias voltage. Therefore, the input capacitance of the rectifier can be adjusted by modulating the bias voltage of the NMOS switches of the first stage (Mn1,2 ). To avoid the adverse effects of the bias voltage variation on the PCE of the rectifier (as discussed in Section II), an auxiliary floating cell could be connected in parallel with the main

Fig. 6. Schematic of the first stage of the rectifier and its input capacitance.

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not impose a significant overhead and in terms of layout area and power is the most efficient architecture among the three techniques. Table. I summarizes the performance metrics of these recently proposed efficiency enhancement techniques (based on post-layout simulations) and compares them with state-ofthe-art differential CMOS rectifiers for the similar range of operation frequency.

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[5]? SC[6]? AUX[7]? QFG[8]? 0.13 µm 0.13 µm 0.13 µm 0.13 µm 950 MHz 950 MHz 950 MHz 2.4 GHz 4 3 3 3 (4 µA) 10 k⌦ 50 k⌦ 30 k⌦ 0.9V @ 0.36V 0.6 V @ 0.34 V 1.25 V @ 0.29 V 1.8 V @ 0.45 V 60 % @ 0.36V 57 % @ 26 dBm 73 % @ 0.29 V 66 %c @ 0.3-0.5V 46 % @ 0.3 V 45 % @ 0.3 V 54 % @ 0.2 V 60 % @ 0.25 V At maximum frequency. b The whole power extraction system.

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Reference [2]?? [4]?? Technology 0.18 µm 0.18 µm Frequency 935 MHz 950 MHz Number of stages 3 2 Load 30 k⌦ (2 µW) Output Voltagea 2.5 V @ 6 dBm 0.5 V @ 0.36 V Maximum Efficiency 62 % @ 6 dBm 23 %b @ 0.36V Low-Voltage Efficiency 10 % @ 19 dBm 23 % @ 0.36V ? Post-layout simulation results. ?? Measurement results. c PCE>60% for 0.25V-to-0.7V.

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Block diagram of the proposed dual-band matching scheme.

IV. S IMULATION R ESULTS A proof-of-concept prototype of the proposed dual-band rectifier is designed and simulated in a 0.13 µm CMOS technology. Two 20 nH inductors are used to match the 50 ⌦ source to the input capacitance of the rectifier. For a 50 k⌦ load, Fig. 8 shows the transient response of the proposed scheme for the source input amplitude of 40 mV (before matching) at two different input frequencies of 950 MHz and 2.4 GHz. As shown, the comparator triggers the control signal, ctrl, once out2 falls below the reference voltage. The flip-flop turns on the switch signal (SW ), upon sensing the falling edge of ctrl to switch the input capacitance to its higher value Cin1 (mode 1). SW turns off at the next falling edge of ctrl to switch the rectenna back to mode-2. Accounting for the power consumption of the comparator, band-gap reference generator and the flip-flop controller, the rectenna generates an output voltage of ⇠1 V in mode-2 (fin = 2.4 GHz) and achieves the PCE of 64% for an input amplitude of 40 mV. The output voltage and PCE in mode-1 (fin = 950 MHz) are ⇠0.9 V and 55%, respectively. The slight degradation in output voltage and PCE performance of the rectenna in mode-1 can be attributed to the larger portion of the input power being shunt to the ground due to the added input capacitance (through M1,2 ). The auxiliary cell generates a bias voltage (Vbias ) of ⇠0.6 V. The simulated frequency response of the proposed matching scheme is shown in Fig. 9. V. C ONCLUSION In this paper, various efficiency enhancement techniques for CMOS differential rectifiers are overviewed. Through out

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LS at frequency f2 and establishes the voltage matching. The negative edge-triggered flip-flop is connected in a divide-bytwo mode to avoid the unnecessary transition of SW when the output voltage starts to grow. The comparator reference is generated by a band-gap reference generator. The bias voltage is extracted from the output of the floating auxiliary cell ([7]) and is fed to the gates of M1,2 in a QFG fashion ([8]). Note that the value of bias voltage could be designed such that the input capacitance covers the dynamic range of Cin and provides a range of resonance frequencies. The comparator, reference generator and the flip-flop controller are supplied by the output of the main rectifier to enable a self-sufficient operation of the proposed matching scheme.

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appropriately biasing the gate of switching transistors in a differential rectifier architecture, higher efficiencies for smaller input levels are achieved. The proposed techniques are exploited to implement a dual-band matching scheme to enable wireless power delivery with close to optimum PCE at two different frequencies. The separation between the two frequencies could be adjusted (within the range of the input capacitance variations) through proper design of the bias voltage circuit. The proposed matching technique facilitates on-chip matching and operates in a self-sufficient manner. R EFERENCES [1] S.-Y. Wong and C. Chen, “Power efficient multi-stage CMOS rectifier design for UHF RFID tags,” Integration, the VLSI Journal, vol. 44, no. 3, pp. 242 – 255, 2011. [Online]. Available: http://www.sciencedirect.com/science/article/pii/S0167926011000307 [2] K. Kotani, A. Sasaki, and T. Ito, “High-efficiency differential-drive CMOS rectifier for UHF RFIDs,” IEEE Journal of Solid-State Circuits,, vol. 44, no. 11, pp. 3011 –3018, Nov. 2009. [3] A. Facen and A. Boni, “CMOS power retriever for UHF RFID tags,” Electronics Letters, vol. 43, no. 25, pp. 1424–1425, 2007. [4] S. Mandal and R. Sarpeshkar, “Low-power CMOS rectifier design for RFID applications,” IEEE Transactions on Circuits and Systems I: Regular Papers,, vol. 54, no. 6, pp. 1177 –1188, June 2007. [5] A. Bakhtiar, M. Jalali, and S. Mirabbasi, “A high-efficiency CMOS rectifier for low-power RFID tags,” IEEE International Conference on RFID, 2010, pp. 83 –88, April 2010. [6] P. Kamalinejad, S. Mirabbasi, and V. Leung, “An efficient CMOS rectifier with low-voltage operation for RFID tags,” International Green Computing Conference and Workshops (IGCC), pp. 1–6, 2011. [7] P. Kamalinejad, K. Keikhosravy, S. Mirabbasi, and V. C. Leung, “An efficiency enhancement technique for CMOS rectifiers with low start-up voltage for UHF RFID tags,” International Green Computing Conference (IGCC), pp. 1–6, 2013. [8] P. Kamalinejad, S. Mirabbasi, and V. Leung, “A CMOS rectifier with an extended high-efficiency region of operation,” IEEE International Conference on RFID Technologies and Applications (RFID-TA), pp. 1– 6, 2013. [9] J. Ramirez-Angulo, A. Lopez-Martin, R. Carvajal, and F. Chavero, “Very low-voltage analog signal processing based on quasi-floating gate transistors,” IEEE Journal of Solid-State Circuits, vol. 39, no. 3, pp. 434–442, 2004. [10] Y.-H. Suh and K. Chang, “A high-efficiency dual-frequency rectenna for 2.45- and 5.8-GHz wireless power transmission,” IEEE Transactions on Microwave Theory and Techniques, vol. 50, no. 7, pp. 1784–1789, 2002. [11] Y.-J. Ren, M. Farooqui, and K. Chang, “A compact dual-frequency rectifying antenna with high-orders harmonic-rejection,” IEEE Transactions on Antennas and Propagation, vol. 55, no. 7, pp. 2110–2113, 2007. [12] J. Heikkinen and M. Kivikoski, “A novel dual-frequency circularly polarized rectenna,” IEEE Antennas and Wireless Propagation Letters, vol. 2, no. 1, pp. 330–333, 2003. [13] D. Wang and R. Negra, “Design of a dual-band rectifier for wireless power transmission,” 2013 IEEE Wireless Power Transfer (WPT), pp. 127–130, 2013.

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