15th European Signal Processing Conference (EUSIPCO 2007), Poznan, Poland, September 3-7, 2007, copyright by EURASIP
EFFICIENT HARDWARE ARCHITECTURES OF SELECTED MPEG-7 COLOR DESCRIPTORS ´ P. Sniatała, R. Kapela, R. Rudnicki, A. Rybarczyk Chair of Computer Engineering/Faculty of Computer Science and Management, Pozna´n University of Technology ul. Piotrowo 3a, 60-965, Pozna´n, Poland phone: + 48 665 23 64, fax: + 48 665 25 92, email:
[email protected] web: www.cce.put.poznan.pl
ABSTRACT This paper presents hardware implementation of most commonly used MPEG-7 color descriptors. The testing circuits was described using VHDL language and synthesized into FPGA. The proposed system architectures are used for description in real-time image’s color basing on features such as: distribution, spatial layout and spatial structure of color. The proposed hardware architectures split the computational burden into several processes where calculations of mentioned image’s features are made simultaneously in order to improve system’s speed. These methods make hardware realizations of main computational-consuming modules of the system more time efficient. The RC1000 board with a Xilinx Virtex V1000 FPGA was chosen as the target platform. 1. INTRODUCTION The MPEG-7 standard was approved as an effort to address the growing need for handling multimedia content [ 1, 2]. The key aspect of MPEG-7 is that provides a framework of standardized tools that can be used to describe and efficiently manage multimedia content. The standard specifies a set of descriptors and description schemes that can be employed in applications such as video indexing and retrieval, content summarization, real-time content delivery, surveillance, personalized services, etc. This paper is a continuation of a project whose goal is to implement selected MPEG-7 descriptors extraction algorithms as an Application Specific Integrated Circuit (ASIC). The proposed hardware implementation can be used to provide real-time annotation of MPEG-7 video streams, and can enable real-time content delivery applications ranging from home security to personalized news and entertainment. One of the possible applications of such an ASIC could be an MPEG-7 camera, what is illustrated in Figure 1. The MPEG-7 camera would convert an audio-visual scene into content-based representation which is the basis upon which the MPEG-7 standard is built [3]. The prototype approach, to test the hardware realization of the investigated descriptors was designed using HANDEL-C language. HANDEL-C allows to reduce the design time, however results in non-optimal hardware realization after synthesis. Those experiments were presented in previous works [4, 5]. This paper focuses on finding more efficient architectures of scalable color descriptor (SCD), color layout descriptor (CLD) and color structure descriptor (CSD). Each realization thanks to parallel computation techniques is faster than software solutions with resources utilization on the same level than solutions described in HANDELC language.
©2007 EURASIP
Figure 1: Example of a possible project application
The RC1000 board with a Xilinx Virtex V1000 FPGA was chosen as the target platform for all hardware realizations. The following section describes the efficient hardware realizations of selected MPEG-7 color descriptors. Next, the comparison of descriptors corresponding solutions are presented. Finally some goals of the future work are introduced. 2. EFFICIENT HARDWARE ARCHITECTURES OF SELECTED MPEG-7 COLOR DESCRIPTORS 2.1 Scalable Color Descriptor The scalable color descriptor (SCD) can be interpreted as a Haar transform–based encoding scheme applied across values of a color histogram in the HSV color space. The width of the histogram depends on the assumed HSV quantization scheme, and in our implementation is equal to 256 (16 levels for H coefficient, 4 levels for S and V coefficients). In addition quantization process normalizes and nonlinearly maps the histogram values, with higher significance to small values. The simple calculation process of a Haar transform consists of a loop which iterates I = log 2 (n) times, where n is length of the vector. In each iteration detail and approximation coefficients of the transform are calculated. The result vector has the same length and consists of one approximation and n − 1 detail coefficients. Notice, that one iteration can be written as [6]: histi+1 = histi · Hi (1) where, hist is histogram vector, i is current iteration number, Hi is matrix of i-th Haar coefficients.
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15th European Signal Processing Conference (EUSIPCO 2007), Poznan, Poland, September 3-7, 2007, copyright by EURASIP
After receiving the acknowledge signal for start the calculations from the host application, control unit converts the image color space from RGB to HSV. It is made by taking four most significant bits from each RGB coefficient of a particular pixel and putting it as an address of a double LUT memory. Conversion is made parallel for each of two parts of the image stored in memory banks. Conversion with usage of the double LUT memory warrants, that two bins of the HSV histogram are updated every single clock cycle. Reduction of four bits of each RGB pixel coefficient results in calculation just 64 HSV histogram bins instead of 256. Next step is calculation of the Haar transform across the HSV histogram (3). The basic unit of a Haar transform consists of a sum operation and a difference operation, which relate to primitive low-pass and high-pass filters. In proposed system eight adding/subtracting operations are performed in one clock cycle. In order to avoid calculations based on signed numbers dedicated subtracting unit was proposed – Figure 3.
Figure 2: Scalable Color Descriptor calculation architecture
The Hi matrix structure is as follows: ˆ Hi = Hi 01 02 1
process(A,B) begin if A > B then out_adder
