Efficient Linear Feedback Shift Register design for Pseudo Exhaustive Test Generation in BIST Nisha Haridas
M. Nirmala Devi
II MTech, VLSI Design Amrita Vishwa Vidyapeetham Coimbatore, India
[email protected]
Dept. of ECE Amrita Vishwa Vidyapeetham Coimbatore, India
[email protected] polynomial, that needs lower number of seed to produce all possible patterns, has been studied in detail in [1]. A property was introduced by [2,3] which a characteristic polynomial should satisfy in order to generate patterns efficiently in pseudoexhaustive manner is quoted in lemma1.1. Various approaches have been investigated keeping this property as standard; for instance in papers [4, 6].
Abstract— Pattern generation is the most important module in a BIST. Out of many test pattern generators (TPG) explored for BIST, linear feedback shift registers (LFSR) are widely used due to their ability to produce highly random patterns. Various improvements over the basic forms of LFSR are available. In the current study, the selection of an appropriate LFSR for a given benchmark circuit is analyzed. It is done by considering various factors such as selection of characteristic polynomial and seed to obtain high fault coverage, minimize invalid patterns, area overhead and time taken to generate the patterns. Keywords- BIST, LFSR,Characteristic polynomial, seed selection.
I.
INTRODUCTION
As the VLSI designs increase in integration density, associated modules becomes inaccessible and testing of the chip becomes more challenging. The test industry is facing with varied problems such as increase in test time and test volume when external ATE is employed for testing. To deal with this, in-system test generation and test application were introduced through built in self test architectures by the testing community. Test generation hardware and embedded algorithms reduce the need for test access for system-wide built-in self-test (BIST), which is a preferred DFT approach. A general form of BIST structure is given in Figure.1. Test pattern generation and output response analyzer are the two important functions that help in self testing of circuit under test (CUT) by BIST. Test pattern generator produces sequence of patterns to be applied to CUT for testing. Output response analyzer (also known as signature analyzer) compares the encoded output of CUT with expected output and indicates whether the circuit is faulty or fault free. Input isolation circuitry prevents the real time system inputs to enter the CUT, when the system is in test mode. Test controller takes care of initialization of the modules before test vectors are applied as well as before output responses are given for compaction. The test generation module that has been widely used in BIST design is the linear feedback shift register (LFSR). The type of test patterns that will be considered in our study will be pseudo exhaustive using LFSR. There are several issues of LFSR designs considered earlier in the literature. Of them two are considered here. First is selection of appropriate characteristic polynomial. Identification of characteristic
Figure 1. A simple architectural representation of BIST
Second issue on LFSR configuration that is dealt in the paper is the selection of seed vector. Seed selection has to be made to achieve maximum fault coverage, minimum invalid patterns and to reduce total test time. Study in this direction had been taken up by [5, 6, 7, 8, and 9]. In this paper, we combine the above ideas to arrive at an optimal design for LFSR with proper selection of seed/seeds for the objectives discussed above. This work attempts to bring together basic concepts involved in an LFSR design and verifies its efficiency on an ISCAS ’85 benchmark circuit. The rest of the paper is organized as follows. Basics of LFSR are reviewed in section II. The various approaches considered for implementation of LFSRs are studied in detail and compared in the following section III. Section IV gives analysis and discussion on the LFSR design studied in section III. Section V gives the result obtained on fault coverage obtained on sample circuit for various characteristic polynomials and seeds. II.
LFSR
The linear feedback shift register (LFSR) is one of the most frequently used in test pattern generator (TPG) and signature analysis (or Output Response Analyzer) for BIST applications. One of the reasons is that an LFSR is more
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area efficient than a counter, requiring less combinational logic per flip-flop. There are two basic types of LFSR implementations, the internal feedback and external feedback LFSRs are shown in Figure 2. For LFSRs, n is referred to as the degree of the polynomial and results in an n-bit LFSR. The characteristic polynomial completely defines the construction of the LFSR (for either internal or external feedback implementations) where the degree of the polynomial gives the number of flip-flops and the number of non-zero coefficients (not including xn and x0 gives the number of exclusive-OR gates. Figure.2(a) is an internal feedback shift register with characteristic polynomial, P(x) = 1 + x + x3 + x4 and Figure.2(b) shows an external feedback shift register with characteristic polynomial, P(x) = 1 + x + x3 + x4. The illustrative characteristic polynomial P(x) is a non-primitive polynomial. This means that the corresponding LFSR does not produce all 2n-1 patterns using a single seed.
Figure 3(b). Maximal length sequence produced
III.
CHARACTERISTIC POLYNOMIAL AND SEED SELECTION
Proper characteristic polynomial has to be selected for optimized pattern generation for a given circuit. The test stage of the IC design process usually employs LFSR to generate all the exhaustive random test patterns. The problem of “invalid test patterns” should be avoided. When a primitive polynomial is used as the characteristic polynomial for an LFSR, it results in 2n-1patterns once initialized with any n-bit vector. But all the patterns are not necessary for detection of every fault for the circuit under test. This gives rise to selection of appropriate seed for the given circuit. Also, since different seeds dominate different simulation results, seed selection is not arbitrary anymore. A. Characteristic polynomial selection A new method for obtaining the characteristic polynomial of an LFSR/SR pseudoexhaustive test pattern generator had been proposed by Dimitri Kagaris and Spyros Tragoudas [6].The goal of this approach is to minimize the required test length with low hardware overhead while obtaining pseudo-exhaustive TPG. When the LFSR part is initialized by a non-zero vector (seed), it cycles through p distinct states, where p is the period of the characteristic polynomial. The period of a polynomial is the least integer p for which the polynomial divides xP+1. As the successive states of the LFSR are shifted through the SR part, they provide test patterns for the test-phase outputs. The set of test-phase inputs upon which each test-phase output depends is referred to as Aset (Affector set). Each test-phase input is identified by its relative position in the LFSR/SR. The efficacy of this scheme depends on the choice of an appropriate characteristic polynomial. In order to guarantee a pseudoexhaustive test set, the characteristic polynomial must satisfy certain properties. One such property is described in lemma 1.1.
Figure 2(a). Internal LFSR with P(x) = 1 + x + x3+ x4
Figure.2(b). External LFSR with P(x) = 1 + x +x3+ x4
The longest possible sequence of patterns for any n-bit LFSR will be 2n-1, since any LFSR initialized to the all zeros state will remain in that state. An LFSR that generates a sequence of 2n-1 unique patterns before repeating the starting sequence, is referred to as a maximum length sequence (also referred to as a maximal length sequence or as an msequence) LFSR. A primitive polynomial of degree 4 is P’(x) = 1 + x + x4 which gives maximal length sequence is shown in Figure. 3(a) and Figure.3(b).
Lemma 1.1 [6] For each Aset Ai = {a1, a2,… awi}, all polynomials xa1 mod P(x), xa2 mod P(x), xawi mod P(x) must be linearly independent. If a primitive polynomial with period 2d -1 that satisfies Lemma 1.1 can be found, then the corresponding LFSR will test the circuit pseudo-exhaustively within time 2d -1 by using only one seed [10]. When there exists a polynomial that satisfies Lemma 1.1 but it is not primitive, then the corresponding LFSR can still test the circuit pseudo-
Figure 3(a). An LFSR with characteristic polynomial as P’(x) = 1+x+ x4
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exhaustively, but with more than one seed. If, however, no polynomial of degree d can be found, then the search is continued among polynomials of degree d + 1. Another way to obtain characteristic polynomial of degree d that is a product of two primitive polynomials P1(z) with degree d1 and P2(z) with degree d2 and GCD (d1, d2) =1. Problem is that the number of candidate polynomials is small because it is based on primitive polynomials whose degrees must be relatively prime. It is proposed that, if the characteristic polynomial G(z) be the product of a primitive P1(z) (of degree d1) and an irreducible polynomial P2(z) (of degree d2), then the number of seeds required to generate maximal length sequence could be reduced by large number. The periods of the two polynomial factors are relatively prime numbers so that the period of G(z) is simply the product of the periods of P1(z) and P2(z). Since P1(z) is primitive and has a controllably large period, the period of G(z) will be large as well. Number of seeds in this case is given by, N = ((2d1 - 1) *(2d2 - 1)) / (p(P1(x)) * p(P2(x))
IV. ANALYSIS AND DISCUSSION In Linear Feedback Shift Registers the main concern is to identify all possible tap selections that obtain the highest achievable transition coverage for an LFSR, as was discussed in previous section,. Also, in order to reduce time consumption and to obtain maximum fault coverage for testing a circuit, proper initialization (seed) has to be selected depending upon the circuit to be tested. The characteristic polynomial P(x) for an LFSR need not be primitive. But if the polynomial is primitive, the LFSR can generate the maximal length sequence starting from any nonzero initial state. In contrast, test generation for an LFSR with a nonprimitive polynomial is more involved. The LFSR must be initialized to a nonzero state and clocked until the initial state repeats. The LFSR is then re-initialized to a nonzero state that has not yet occurred. The seeding process is repeated until all nonzero states are covered. Clearly, an LFSR with nonprimitive feedback polynomial requires complex control. There are various theorems developed for seed selection in case of LFSR [6] as was discussed in previous section.
(1)
V.
where, p(P1(x)) = period of the polynomial
IMPLEMENTATION AND RESULTS
A 5-bit LFSR is implemented with characteristic polynomial derived as per [6] and test set corresponding to varied seeds for each of the implementation is found out. Fault free response on c17 circuit is found. It is implemented using FPGA Advantage 8.1, a tool available in HDL Designer series. The designs is simulated in Modelsim 6.2 environment is presented in Figure 6.
For example, for the primitive polynomial P1(x) = x3 +x+1 and the irreducible polynomial P2(x) = x4 +x3+x2 +x+1, resulting product is G(x) = P1(x) * P2(x) = x7 + x6 + x4 + x3 + 1. The number of seeds required according to equation (1) is [7], ((2d1 - 1) *(2d2 - 1))/(p(P1(x))*p(P2(x)) = (7 * 15)/(7 *5) = 3.
Figure 6. LFSR with characteristic polynomial P(x) = 1+x+x2+x5
B. Seed selection Even in pseudo-exhaustive pattern generation techniques, there are patterns which do not account for fault coverage due to linear dependencies that was discussed earlier. They are called invalid patterns usually waste mostly test cycle time and consume power. In paper [5], the fault simulation results obtained by employing LFSR to generate test pattern on a general CUT are found to follow a pattern. In the first phase, the test patterns generated by LFSR effectively tests most of the testable faults in a circuit. The total detected fault count is found to increase rapidly during this phase. Test time reduction can be achieved by partitioning the circuit [8, 9] and generating pattern generator for each subcircuit separately. Proper seed selection helps to reduce test cycle time.
Fault coverage is found using Turbo Tester software developed by Department of Computer Engineering of Tallinn Technical University (DCE). It has a database of some benchmark circuits in structurally synthesized binary decision diagram (SSBDD) format with extension ‘.agm’. The selected characteristic polynomial satisfies lemma 1.1 and it is seen to generate maximal length polynomial. P(x) = P1(x) * P2(x)
(2)
where, P1(x) = 1+x+x3 which is a primitive polynomial and P2(x) = 1+x2 ,that is an irreducible polynomial. The Table 1 given below gives the patterns generated using this polynomial and its fault coverage.
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The third polynomial is a primitive polynomial. If it is selected as LFSR characteristic polynomial, it will require memory storage of only one seed and achieves maximum fault coverage. But, the period is larger and involves overhead of producing 20 extra “invalid” patterns. The second characteristic polynomial with seed 11111 is able to give maximum fault coverage with little lesser time overhead. Rest of the seeds alone is inefficient to cater to the fault coverage requirement. So, for the first polynomial, we can consider reseeding by reloading a second seed after one set of patterns have been generated.
Fault coverage is calculated using ‘analyze’ module in the Turbo Tester tool [11]. C17.agm contains SSBDD form of c17 benchmark circuit. Test patterns for a given circuit are given in ‘.tst’ format. The tool has provision to generate test input file from a set of patterns given manually in a text file specified as follows. For each primary input variable a row corresponds, where the name of the variable is followed by ‘:’ and logic values (0 or 1) at each time step (pattern) are separated by spaces. C17 has 5 inputs denoted by i_1 to i_5. TABLE I.
PATTERNS GENERATED USING THIS POLYNOMIAL AND ITS FAULT COVERAGE Patterns Generated 11111 10011 10101 10110 01011 11001 10000 01000 00100 00010 00001 11100 01110 00111
Fault Coverage
TABLE III. FAULT COVERAGE AND INVALID PATTERNS FOR POLYNOMIAL P(X)= 1+X+X2+X3+X4+X5 WITH RESEEDING Seeds used 11010 11011 11010 11100 11010 11101 11010 11110 11100 11110 11100 11101
100%
Thus the pattern generated using the polynomial selected according to lemma 1.1 and using the method suggested by equation (1) is found to be highly efficient.
Polynomial Used
2
3
4
1
1+x+x +x +x +x
2
1+x+x5
3
1+x2+x5
Seed Used
5
Fault coverage (%)
Number of invalid patterns
10101
0
0
11010
80
0
11011 11100 11101 11110 11111 00111 01011 11111
53 60 96 93 93 96 50 100
0 0 0 0 0 0 0 10
11111
100
20
Fault coverage(%)
Invalid patterns
9
83
0
9
96
0
12
96
0
12
96
0
9
93
0
9
100
1
From Table III it can be observed that 11100 is an important seed from rows two and six. It gives maximum fault coverage when used with 11101. An extra seed accounts for area but achieves maximum fault coverage with just one extra pattern. This can be considered as an optimum pattern generation.
TABLE II. FAULT COVERAGE AND INVALID PATTERNS FOR VARIED POLYNOMIAL AND SEEDS ON C17 BENCHMARK CIRCUIT
S.No
Total number of patterns
VI.
CONCLUSION
Variations of the basic LFSR and its design considerations are studied. LFSR design has been examined in detail in terms of finding proper characteristic polynomial and seed selection. LFSR with varied characteristic polynomials have been implemented and compared in terms of fault coverage. Table I. has used a characteristic polynomial that satisfies lemma 1.1 and requires less number of seed for maximal length pattern generation. But the problem of invalid test pattern is evident from the results obtained. Thus lemma 1.1 is found to be a proper base for the selection, but the design needs to be modified so that invalid patterns can also be avoided. ACKNOWLEDGMENT The authors would like to thank Department of Computer Engineering of Tallinn Technical University (DCE) for the TURBO TESTER [11] developed by them and used in the current work.
The first seed for the first polynomial in Table II neither identifies any fault in the circuit nor produces any further patterns. Such seed should be avoided at any cost since it results in an inefficient LFSR configuration.
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[20] Sanjay Gupta, Janusz Rajski and Jerzy Tyszer, “Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns” IEEE Transactions on computers, VOL. 45, NO. 8, pp. 939-949, Aug 1996
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