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IEEE ELECTRON DEVICE LETTERS, VOL. 36, NO. 1, JANUARY 2015
Electrical Modeling of On-Chip Cu-Graphene Heterogeneous Interconnects Wen-Sheng Zhao, Member, IEEE, Da-Wei Wang, Gaofeng Wang, Senior Member, IEEE, and Wen-Yan Yin, Fellow, IEEE
Abstract— In this letter, novel Cu-graphene heterogeneous interconnects are studied by virtue of the equivalent circuit model. The effective resistances of such interconnects are extracted numerically, with the Cu/graphene and graphene/ graphene interface resistances treated appropriately. It is shown that such interconnects can provide superior performance and reliability over Cu wires for an on-chip interconnect applications. Index Terms— Cu-graphene heterogeneous graphene liner, equivalent circuit model.
interconnect,
Fig. 1.
Schematic of Cu-graphene heterogeneous interconnect.
I. I NTRODUCTION
A
LONG with the semiconductor technology advancement, the minimum feature size shrinks by 30% every 2-3 years, which leads to more functional blocks on a single chip. Due to the increasing grain boundary and surface scatterings, however, the effective resistivity of conventional Cu interconnect increases dramatically, which results in significant performance degradation and serious reliability problems [1]. To design high-performance integrated circuits (ICs), the interconnect issues must be addressed. As the interconnect-centric design era is coming, there are urgent needs for new candidate interconnect technologies [2], [3]. Kang et al. proposed that the interconnect reliability can be improved by capping Cu wire with graphene layers [2]. The advantages of such Cu-graphene heterogeneous interconnects could be further improved when the technology advances [3]. In addition to the high current-carrying capacity of graphene materials, it is found that 1-nm-thick multilayer graphene (MLG) can be employed as the barrier layer to prevent the diffusion of Cu atoms to the substrate [4]. Considering the continuous development of graphene growth technique [5], it can be anticipated that graphene liners can be used in the design of future nano-interconnects. In this letter, the equivalent circuit model of Cu-graphene heterogeneous interconnects Manuscript received October 28, 2014; revised November 15, 2014; accepted November 21, 2014. Date of publication December 2, 2014; date of current version December 22, 2014. This work was supported in part by the National Natural Science Foundation of China under Grant 61411136003, Grant 61331007, Grant 61431014, Grant 61171037, Grant 61404040, and in part by the Zhejiang Provincial Natural Science Foundation of China under Grant LQ14F010010 and Grant LZ14F040001. The review of this letter was arranged by Editor Z. Chen. W.-S. Zhao and G. Wang are with the Key Laboratory of RF Circuits and Systems of Ministry of Education, Microelectronics CAD Center, Hangzhou Dianzi University, Hangzhou 310018, China (e-mail:
[email protected]). D.-W. Wang and W.-Y. Yin are with the Centre for Optical and EM Research, State Key Laboratory of Modern Optical Instrumentation, Zhejiang University, Hangzhou 310027, China (e-mail:
[email protected]). Digital Object Identifier 10.1109/LED.2014.2375358
Fig. 2. Equivalent circuit model of Cu-graphene heterogeneous interconnect.
is presented by extending the modeling scheme in [6], and then the performance of such novel interconnects is studied in depth, to the best of our knowledge, for the first time. It is shown that Cu-graphene heterogeneous interconnects can provide superior performance and reliability over conventional Cu wires. II. E LECTRICAL M ODELING Fig. 1 shows the schematic of a Cu wire surrounded with graphene liners. The wire width, thickness, and length are denoted as W, T, and L respectively, and the numbers of graphene layers at the top, bottom, left, and right surfaces of the Cu wire are Nt , Nb , Nl , and Nr respectively. To establish the circuit model, the first step is to partition it into M segments along its length, as shown in Fig. 2. Here, M is chosen to be 40, which is sufficient for calculation accuracy [6]. It is assumed that the Cu wire and graphene layers are decoupled, and the inductive reactance is neglected as it is much smaller than the resistance even up to several gigahertzes [6]. For easy analysis, only the capping graphene layers are considered at first. Fig. 3 shows the equivalent circuit model, where the circuit elements RCu , Rgr , RCu-gr , and Rgr-gr denote the Cu, graphene, Cu/graphene interface, and graphene/graphene interface resistances, √ 2respectively. Specifically, RCu-gr = ρCu-gr /WL = 3 3acc ρpc /4WL [7], [8],
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ZHAO et al.: ELECTRICAL MODELING OF ON-CHIP Cu-GRAPHENE
Fig. 3. layers.
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Equivalent resistance network of Cu wire capped with graphene
where acc is the lattice constant and ρpc denotes the contact resistivity per carbon atom; Rgr-gr = ρgr-gr δ/WL, where δ = 0.34 nm and ρc_gr-gr denotes the c-axis resistivity of graphene layers that is in the range of [0.2, 30] ·cm [6]. Based on the modeling scheme described in [6], the effective resistance of Cu wire capped with graphene can be given as −1 M M 1 1 −1 I + [ A21 ]t [A11 ]t (1) Reff,t = M×M R1 m=1 m=1
−1 where [A]t = [H ]Cu-gr [H ]gN-tgr and [H ]Cu-gr ([H ]gr-gr ) can be obtained from equation (10) in [6] by replacing Ra and Rb with R2 (R4 ) and R3 , respectively. Equation (1) can be extended to the general case of Cu-graphene heterogeneous interconnects by applying the following conditions: [V1 ] = [V1 ]t = [V1 ]b = [V1 ]l = [V1 ]r and Is [I 1 ] M ×1 = [I1 ]t + [I1 ]b + [I1 ]l + [I1 ]r , where [V1 ] and [I1 ] are voltage and current vectors of the Cu wire, Is is the source current, and the subscripts t, b, l, and r represent the respective corresponding quantities when the graphene layers at the top, bottom, left, and right surfaces of the Cu wire are considered. The effective resistance of Cu wire surrounded with MLG can then be calculated as ⎛ ⎞−1 M M ⎝ 1 I1 ⎠ (2) + [ A21]i [ A11 ]−1 Reff = i M×M R1 m=1 m=1
i=t,b,l,r
where [ A]b , [ A]l , and [ A]r can be obtained with the similar procedure to [ A]t . III. R ESULTS AND D ISCUSSION In this Section, the effective resistivity of Cu wires and Cu-graphene heterogeneous interconnects are computed and compared at the 16 nm node [9]. The interconnect width is 16 nm, the aspect ratio (AR) is 2.1, and the liner thickness is 1 nm. To reduce the impacts of Cu size effect, the number of graphene layers is chosen to be 3 (i.e., 1-nm-thick MLG in [4]) for Cu-graphene heterogeneous interconnects. Both the specularity and reflectivity parameters ( pCu and R f ) of Cu are 0.5 based on the experimental data [1], while the Fermi energy and mean free path (MFP) of graphene are 0.2 eV and 100 nm, respectively. As shown in Fig. 4, three types of Cu-graphene heterogeneous interconnects with specularity parameter pgr = 0 and 0.8: Cu-graphene 1, Cu-graphene 2, and Cu-graphene 3
Fig. 4. Effective resistivity of Cu-graphene heterogeneous interconnects versus interconnect length. (a) pgr = 0; (b) pgr = 0.8.
are investigated by virtue of the circuit model. Here, the specularity parameter pgr for graphene ribbons is consistent with that for Cu wires, e.g., pgr = 0 indicates that the edges are fully diffusive. As stated in [2] and [4], the former two types can be fabricated by state-of-the-art techniques, while the last one may need a fabrication technique to be developed. Although the manufacturability of liners thinner than 1.7 nm is not yet guaranteed according to ITRS [9], it is evident that the ultrathin graphene is a potential candidate for the liner applications. More importantly, the conductance characteristics and high current-carrying capacity of graphene make it helpful for improving the interconnect performance and reliability. Fig. 4 plots the effective resistivity versus the interconnect length for Cu-graphene heterogeneous interconnects with specularity parameter pgr = 0 and 0.8. It can be seen from Fig. 4 that the effective resistivity can be reduced by introducing the graphene layers. For short interconnects, the conductive path of graphene layers are blocked by very large interfacial resistance RCu-gr and Rgr-gr . Therefore, reducing the c-axis resistivity of graphene layers can help improving the electrical conduction. When the length becomes larger than a certain value, named as the “transition length”, the effective resistivity of Cu-graphene heterogeneous interconnect tends to its minimum value, which can be calculated −1 −1 −1 + Rgr−t ) , where Rgr−t denotes the total simply by (RCu resistance of graphene layers surrounded. A similar phenomenon can be observed in top-contacted multi-layer graphene nanoribbon (MLGNR) interconnects [10]. It has been experimentally observed in [3] that the failures of Cu-graphene heterogeneous interconnects always occur at the graphene layers, which is due to their oxidation. However, the reliability of graphene layers can be improved by capping a dielectric layer [11], [12]. In real world applications, the Cu-graphene heterogeneous interconnects should be surrounded with dielectrics. The impacts of graphene oxidation would be alleviated, and the central Cu wire becomes crucial for the reliability issue. The currents flowing through the central Cu wires of Cu-graphene heterogeneous interconnects
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IEEE ELECTRON DEVICE LETTERS, VOL. 36, NO. 1, JANUARY 2015
lower than that of Cu wires with the same dimensions. This makes the multilayer graphene still a promising candidate as interconnects at the end of roadmap. IV. C ONCLUSION
Fig. 5. Normalized current flowing through the central Cu wires of the third type of Cu-graphene heterogeneous interconnects.
are extracted and compared in Fig. 5. It is evident that due to the conductive property of graphene layers, these currents can be reduced by introducing the graphene liners. These reduction in current can help improving the interconnect reliability. As the length increases, the advantages of Cu-graphene heterogeneous interconnects becomes more significant. Impacts of specularity parameter pgr on performance and reliability of Cu-graphene heterogeneous interconnects are also examined. It can be seen in Fig. 4(a) and (b) that with the increase of pgr , its effective resistivity decreases significantly due to the reduced graphene resistance, while the transition length is kept almost unchanged. In addition, the reliability of Cu-graphene heterogeneous interconnects can also be improved by increasing pgr , as shown in Fig. 5. Therefore, it is necessary to have high-quality graphene liners to improve both performance and reliability of Cu-graphene heterogeneous interconnects. However, it should be pointed out that with the scaling down of the interconnect dimensions, the fabrication and integration of Cu/low-k interconnects would be very difficult. More importantly, as stated in [13], the conductance of monolayer graphene could be larger than that of Cu wire when the width becomes smaller than 10 nm. Therefore, as the technology is approaching to the end of roadmap, the monolayer and multilayer graphene nanoribbons would be more suitable than the Cu/low-k interconnects and the Cu-graphene heterogeneous interconnects [13], [14]. However, special attention should be paid to the manufacture of MLGNR interconnects as the Fermi level and MFP of each layer are not the same, and in this regard some techniques need to be further pursued. More recently, sub-10-nm-wide multilayer graphene interconnects have been developed in AIST [15], with quality improved by intercalated with FeCl3 . It is found that such interconnects exhibit a resistivity of 3.2 μ-cm, which is predicted to be
The novel Cu-graphene heterogeneous interconnects are studied in this letter. Based on the equivalent circuit model, their effective resistivity can be extracted numerically. It is found that by applying the graphene liners, the electrical performance and reliability can be improved. The advantages of Cu-graphene heterogeneous interconnects become greater with the increase of length. However, for sub-10 nm region, the monolayer and multilayer graphene nanoribbon interconnects would be more suitable. R EFERENCES [1] W. Steinhögl et al., “Comprehensive study of the resistivity of copper wires with lateral dimensions of 100 nm and smaller,” J. Appl. Phys., vol. 97, no. 2, p. 023706, Jan. 2005. [2] C. G. Kang et al., “Effects of multi-layer graphene capping on Cu interconnects,” Nanotechnology, vol. 24, no. 11, p. 1157017, 2013. [3] C.-H. Yeh et al., “Scalable graphite/copper bishell composite for highperformance interconnects,” ACS Nano, vol. 8, no. 1, pp. 275–282, 2014. [4] B.-S. Nguyen, J.-F. Lin, and D.-C. Pering, “1-nm-thick graphene trilayer as the ultimate copper diffusion barrier,” Appl. Phys. Lett., vol. 104, no. 8, pp. 082105-1–082105-5, Feb. 2014. [5] Z. Peng et al., “Direct growth of bilayer graphene on SiO2 substrates by carbon diffusion through nickel,” ACS Nano, vol. 5, no. 10, pp. 8241–8247, Sep. 2011. [6] V. Kumar, S. Rakheja, and A. Naeemi, “Performance and energy-per-bit modeling of multilayer graphene nanoribbon conductors,” IEEE Trans. Electron Devices, vol. 59, no. 10, pp. 2753–2761, Oct. 2012. [7] Y. Matsuda, W. Q. Deng, and W. A. Goddard, “Contact resistance for ‘end-contacted’ metal-graphene and metal-nanotube interfaces from quantum mechanics,” J. Phys. Chem. C, vol. 114, no. 41, pp. 17845–17850, 2010. [8] Y. Khatami et al., “Metal-to-multilayer-graphene contact—Part I: Contact resistance modeling,” IEEE Trans. Electron Devices, vol. 59, no. 9, pp. 2444–2452, Sep. 2012. [9] (2013). International Technology Roadmap for Semiconductors. [Online]. Available: http://www.itrs.net/ [10] W.-S. Zhao and W.-Y. Yin, “Comparative study on multilayer graphene nanoribbon (MLGNR) interconnects,” IEEE Trans. Electromagn. Compat., vol. 56, no. 3, pp. 638–645, Jun. 2014. [11] X. Chen et al., “Graphene interconnect lifetime: A reliability analysis,” IEEE Electron Device Lett., vol. 33, no. 11, pp. 1604–1606, Nov. 2012. [12] N. Jain et al., “Graphene interconnects fully encapsulated in layered insulator hexagonal boron nitride,” Nanotechnology, vol. 24, no. 35, p. 355202, Sep. 2013. [13] A. Naeemi and J. D. Meindl, “Conductance modeling for graphene nanoribbon (GNR) interconnects,” IEEE Electron Device Lett., vol. 28, no. 5, pp. 428–431, May 2007. [14] C. Xu, H. Li, and K. Banerjee, “Modeling, analysis, and design of graphene nano-ribbon interconnects,” IEEE Trans. Electron Devices, vol. 56, no. 8, pp. 1567–1578, Aug. 2009. [15] D. Kondo et al., “Sub-10-nm-wide intercalated multi-layer graphene interconnects with low resistivity,” in Proc. IEEE Int. Interconnect Technol. Conf./Adv. Metallization Conf. (IITC/AMC), San Jose, CA, USA, May 2014, pp. 189–191.
