Electrical properties of III-V/oxide interfaces interfaces - Google Sites

Electrical properties of III-V/oxide interfaces G. Brammertz, H.C. Lin, A. Alian, S. Sioncke, L. Nyns, C. Merckling, W.-E. Wang, M.Caymax, M. Meuris., M. Heyns., T. Hoffmann

© IMEC 2010 / CONFIDENTIAL

G. Brammertz, PT/LDD

Outline • Introduction: interface states • Electrical interface state characterization techniques: • • • • •

Conductance method Terman method Berglund method Combined high and low frequency method Full simulation of electrostatics

GaAs/oxide interface properties In0.53Ga0.47As/oxide interface properties InP/oxide interface properties Electrostatic effect of interface states on MOS-HEMT devices • Conclusions • • • •



2

Interface states Interface states arise from the sudden disruption of the lattice structure, which creates carrier energy levels different from the usual energy band structure. DOS Derived mainly from As wavefunctions

EV

Derived mainly from Ga wavefunctions

EC

Energy

DOS

~1015 cm-2 broken bonds

~1015 cm-2 interface states Donors

EV © IMEC 2010 / CONFIDENTIAL


Acceptors

EC

Energy 3

Charge trapping/emission at the interface Interface defects are small localized potential wells at the surface of the material, if their energy level lies within the bandgap. EC ∆E

EC ∆E

Eg EV

EV

Charge trapping τt =

• •

Eg

Charge emission  ∆E  exp  kT   τ e (∆E) = σv t N c

1 σv t N c

The charge trapping time τt depends only on the capture cross section of the trap (σ), the thermal velocity (vt) and the density of states (Nc). The charge emission time also depends exponentially on the trap depth ΔE.



4

σ =10-14 cm2

10 10 10 10 10 10

4 0 -4 -8 -12 -16 -20

0

0.4 0.8 1.2 1.6

2

2.4 2.8 3.2

10 10 10 10 10 10 10

10

GaAs

8 6 4 2 0 -2

0

10 10 10 10 10 10 10

10

Si

8 6 4 2 0 -2

0

0.2

0.4

0.6

0.8

0.2

0.4

0.6

0.8

1

1.2

1.4

10 10 10 10 10 10 10

10

InP

8 6 4 2 0 -2

0

1

Energy in bandgap (eV)

10 10 10 10 10 10 10

10 8

In0.53Ga0.47As

6 4 2 0 -2

0

0.2

0.4

0.6


0.2

0.4

0.6

0.8

1

1.2


Energy in bandgap (eV) Characteristic trap frequency (Hz)

Characteristic trap frequency (Hz)



10

GaN

8


10



Characteristic frequencies

10 10 10 10 10 10 10

10

InAs

8 6 4 2 0 -2

0

0.2


The characteristic trap frequency varies strongly with the energy level of the trap in the bandgap, such that with typical AC measurement frequencies only small parts of the bandgap can be measured. © IMEC 2010 / CONFIDENTIAL


5

σ =10-16 cm2

10 10 10 10 10 10

4 0 -4 -8 -12 -16 -20

0

0.4 0.8 1.2 1.6

2

2.4 2.8 3.2

10 10 10 10 10 10 10

10 8 6 4 2 0 -2

0

10 10 10 10 10 10

10

Si

8 6 4 2 0 -2

0

0.2

0.4

0.6

0.8

0.2

0.4

0.6

0.8

1

1.2

1.4

10 10 10 10 10 10 10

10

InP

8 6 4 2 0 -2

0

1


10 10 10 10 10 10 10

10 8

In0.53Ga0.47As

6 4 2 0 -2

0

0.2

0.4

0.6


0.2

0.4

0.6

0.8

1

1.2





10

GaAs


10

GaN

8


10




10 10 10 10 10 10 10

10

InAs

8 6 4 2 0 -2

0

0.2




6

σ =10-18 cm2

10 10 10 10 10 10

4 0 -4 -8 -12 -16 -20

0

0.4 0.8 1.2 1.6

2

2.4 2.8 3.2

10 10 10 10 10 10 10

10 8 6 4 2 0 -2

0

10 10 10 10 10 10

10

Si

8 6 4 2 0 -2

0

0.2

0.4

0.6

0.8

0.2

0.4

0.6

0.8

1

1.2

1.4

10 10 10 10 10 10 10

10

InP

8 6 4 2 0 -2

0

1


10 10 10 10 10 10 10

10 8

In0.53Ga0.47As

6 4 2 0 -2

0

0.2

0.4

0.6


0.2

0.4

0.6

0.8

1

1.2





10

GaAs


10

GaN

8


10




10 10 10 10 10 10 10

10

InAs

8 6 4 2 0 -2

0

0.2




7






8

Conductance method

M

O

• Interface states induce an additional capacitance and loss contribution in the MOS structure, represented by Cit and Rit in parallel with the depletion capacitance.

S

• The capacitance and resistance of the interface traps will be measured only if the measurement frequency is equal to the characteristic trap frequency at the Fermi level position.

Ef eVG

f = 1 kHz

α Dit

Cd Cox

Rs

Cit

Rit

• In the example case, at Vg=1V, the Fermi level at the semiconductor surface passes through the trap level with a characteristic frequency of 1 kHz. © IMEC 2010 / CONFIDENTIAL


9

Conductance method: pitfalls* 1. Depending on the size of the bandgap of the material, only small portions of the bandgap can be measured with the conductance method. Performing measurements at lower and higher temperatures might help for characterizing larger parts of the bandgap (Beware of weak inversion effects!). 2. The amplitude of the measured interface state conductance is limited by the oxide capacitance, such that the largest Dit that can be extracted is of the order of Cox/q. Dit values that approach this value will be strongly leveled off.

*K. Martens © IMEC 2010 / CONFIDENTIAL


et al., TED 55 (2), 547, 2008 10

Conductance method: pitfalls* 3. Weak inversion responses, due to interactions of minority carriers with interface states, do behave similarly to majority carrier interface state responses. This can lead to overestimation of the Dit, if one applies equations that only take majority carriers into account.

300K

0.7

2

Capacitance (µF/cm )

4. Flatband voltage determination for energy-voltage relationship extraction can be very problematic if large frequency dependent flatband voltage shift is present.

frequencies shown 1kHz → 1MHz

100 Hz

0.6 0.5 0.4

1 MHz

0.3 0.2 -3

-2

-1 0 1 Gate voltage (V)

*K. Martens © IMEC 2010 / CONFIDENTIAL


2

3

et al., TED 55 (2), 547, 2008 11

Terman method (high frequency CV) Comparison of high frequency CV curve to theoretical CV curve without interface states:

 dψ  −1  s  C it (ψ s ) = C ox  − 1 − C s (ψ s )   dVg    

• If there is a large density of fast interface states at the band edges or even inside the conduction band of III-V semiconductors, this condition for application of the method is not verified. • f.ex. in the InGaAs case there is typically a large density of very fast Dit close to the valence band as well as inside the conduction band.


High frequency CV-curve meaning in this case: 1. Interface states do not respond to the measurement frequency and do not add any capacitance. 10 10 10 10 10 10 10

10

In0.53Ga0.47As

8 6 4 2 0 -2

0

EV

0.2

0.4

0.6


EC

• If there is a large density of very slow interface states inside the III-V semiconductor bandgap, this condition for application of the method is not verified. • f.ex. in the GaAs case there is typically a large density of very slow Dit close to mid-gap, which does not respond to the bias sweep.


2. Interface states do respond to the bias sweep, which leads to stretch out of the CV-curve. 10 10 10 10 10 10 10

10

GaAs

8 6 4 2 0 -2

0

0.2

0.4

0.6

0.8

1

1.2

1.4


For pretty much all III-V/oxide interfaces, at least one of the conditions is not verified, such that this method will in most cases lead to errors in the derived Dit values. © IMEC 2010 / CONFIDENTIAL


12

Berglund method (low frequency CV) Comparison of low frequency CV curve to theoretical CV curve without interface states:

−1

 1 1  C it =  −  − Cs  C LF C ox 

Low frequency CV-curve meaning in this case: 1. Interface states fully respond to the measurement frequency and add capacitance to the CV. • If there is a large density of very slow interface states inside the III-V semiconductor bandgap, this condition for application of the method is not verified. • f.ex. in the GaAs case there is typically a large density of very slow Dit close to mid-gap, which does not respond to the bias sweep, unless very slow sweep is used.


2. Interface states do respond to the bias sweep, which leads to stretch out of the CV-curve. 10 10 10 10 10 10 10

10

GaAs

8 6 4 2 0 -2

0

0.2

0.4

0.6

0.8

1

1.2

1.4


Due to low conduction band density of states the theoretical Energy-Voltage curves are more complicated than in the Si case: • Not a limitation, just a complication that can be addressed by using the correct theoretical model including Fermi-Dirac statistics for carrier concentrations.

For low bandgap materials (In0.53Ga0.47As, InAs, InSb,...) these conditions are typically verified, BUT: slow oxide traps can also introduce stretchout, which could falsify the results. © IMEC 2010 / CONFIDENTIAL


13

Combined high-low frequency method Derivation of Dit from both high and low frequency CV curves.

−1

 1  1 1  1  C it =  − −  −   C LF C ox   C HF C ox 

−1

High and low frequency CV-curves need to verify the conditions of the Terman and Berglund method respectively, which makes this method very restrictive.

For pretty much all III-V/oxide interfaces, at least one of the conditions is not verified, such that this method will in most cases lead to errors in the derived Dit values.



14

Full simulation of electrostatics Solution of the Poisson equation, d 2 V(x) ρ ( x) =− 2 dx εs

Ev

Vfb

Ei

Ec

In thermal equilibrium (Similar to Berglund method) • For low bandgap materials (In0.53Ga0.47As, InAs, InSb,...) these conditions are typically verified, BUT: slow oxide traps can also introduce stretchout, which could falsify the results. Trap response frequency (Hz)

Including the correct carrier concentrations for degenerate semiconductors, including Fermi-Dirac statistics.

In0.53Electrons Ga As Holes 0.47

10

10

10 10 10 10 10 10

8

6

4

AC-CV

2

0

QS-CV

-2

0.0

0.2

0.4

0.6

Trap energy within bandgap (eV)



15

Full model* Integrating the Poisson equation: e( N d − N a + p ( x ) − n ( x ) ) d 2V ( x) dE ( x) dx 2

= E ( x)

dV ( x)

=−

εs

n(V ( x) ) =

,where

2 π

(kT )3 / 2

∞

N C ∫E

C

(E − EC )1 / 2 1 + e ( E −V ( x )) / kT

dE

yields: E (V ' ( x) ) = 2Sign(V s )

•

e( N d − N a + p(V ( x)) − n(V ( x)) )

εs

B

.

Vs

∫ψ

B

− eε s ( N d − N a + p(V ( x)) − n(V ( x)) )dV ( x)

.

The semiconductor and interface state capacitances can be written as: and

d C it (V s ) =

(∫

+∞

Vs

V

Dit , D dE − ∫− ∞s Dit , A dE dV s

)

respectively.

The total capacitance of the MOS structure: 1 1 1 = + C tot (V s ) C ox C s (V s ) + C it (V s )

•

dV ( x)

Q s (V s ) = −2Sign(V s )

and accordingly:

dQ s (V s ) C s (V s ) = − dVs

•

−

Applying Gauss’ theorem from the bulk to the surface of the semiconductor gives: Es = −Qs / ε s

•

V '( x )

∫ψ

.

Finally, gate voltage and surface potential are related through: VG = V s + φ m − φ s −

Q s (V s ) Qit (V s ) − C ox C ox

.

OR, full self-consistent numerical solution of the Poisson equation for more complicated semiconductor heterostructures * G. Brammertz et al., APL 95, 202109 (2010) © IMEC 2010 / CONFIDENTIAL


16






17

Dit distribution of GaAs with Al2O3 (S-pass. and FGA)* n-type

p-type

0.6 0.5 0.4 0.3

1MHz

0.6 0.5 0.4 0.3

1MHz

100Hz

0.7

2

100Hz

0.7

25°C 0.7

0.6 0.5 0.4 0.3

1MHz

0.2

0.2

-3

-2


2

-2


2

-2



100Hz

2

2


0.7


0.8

2


150°C

150°C

25°C

2

100Hz

0.6 0.5 0.4 0.3 0.2 0.1 -2

1MHz -1

0 1 2 Gate voltage (V)

Measuring n- and p-type GaAs at both 25°C and 150°C shows the interface state distribution in the complete bandgap. *G. Brammertz et al., APL 93, 183504 (2008) © IMEC 2010 / CONFIDENTIAL


18

3

Dit distribution of GaAs-amorphous oxide interfaces GaAs-Gd2O3 (MBE)

GaAs-HfO2 (ALD)

GaAs-Al2O3 (ALD)

Not shown here, but also measured and showing similar interface state distribution: • GaAs-Al2O3 (MBE) • GaAs-Ge-GeO2-Al2O3 (MBE) • GaAs-LaAlO3 (MBE) • GaAs-ZrO2 (ALD) • GaAs-In-In2O3-Al2O3 (MBE)

The interface state distribution of the GaAs-amorphous oxide interface depends rather little on the nature and the deposition condition of the oxide. © IMEC 2010 / CONFIDENTIAL


19

Physical identity of GaAs interface states: Dangling bond states* Which defect peak corresponds to what physical defect? GaAs-Al2O3 before FGA

GaAs-Al2O3 after FGA

EC

EV As dangling bonds

Ga dangling bonds

EV

EC

As dangling bonds passivated

Ga dangling bonds passivated

H passivates dangling bond states. *G. Brammertz et al., APL 93, 183504 (2008) © IMEC 2010 / CONFIDENTIAL


20

Physical identity of GaAs interface states: Oxygen bond states* Which defect peak corresponds to what physical defects? Ga 3+ detectable

GaAs-Al2O3 after FGA

Ga 3+ not detectable

EC

EV

Ga 3+

Remaining defects close to the conduction band seem to be due to Ga3+ oxidation state (Hinkle et al.). *



C. Hinkle et al., APL 94, 162101 (2009). 21

Physical identity of GaAs interface states: Vacancies (Ga-Ga, As-As bonds)* Which defect peak corresponds to what physical defects? GaAs-Al2O3 after FGA Donor Acceptor

EV

EC

As vacancy (Ga-Ga bond) Ga vacancy (As-As bond)

The dominating mid-gap peaks, one donor-like, one acceptor-like, are likely due to structural defects at the interface (vacancies)* *W. E. Spicer © IMEC 2010 / CONFIDENTIAL


et al., JVST 16(5), 1422 (1979). 22

GaAs/oxide interfaces that diverge considerably from this picture

1.0

2

25°C

GaAs-aSi-HfO22 Capacitance (µF/cm )

GaAs-Ga2O-GGO1

25°C

0.8 0.6 0.4 0.2 -1.0

0.0

1.0

2.0

2

150°C


VG (V) 1.0

150°C

0.8 0.6 0.4 0.2 -1.0

0.0

1.0

2.0

VG (V)

1 M. Passlack

et al., EDL 30 (1), 2 (2009). M. Passlack et al., accepted by TED (2010). © IMEC 2010 / CONFIDENTIAL

1

J. De Souza et al., APL 92, 153508 (2008). C. Marchiori et al., JAP 106, 114112, (2010).


23






24

Dit distribution of In0.53Ga0.47As with Al2O3 (S-pass.) : Conductance method* n-In0.53Ga0.47As-Al2O3-Pt

300°K

300°K

2 2


0.7

2


100Hz

0.5

1MHz -2 -1 0 Gate voltage (V)

0.5 0.4 0.3 0.2

0.6 0.5 0.4 0.3

210°K

-2


2

3

-2


0.6 0.5 0.4 0.3 0.2 -3.0

-2.0 -1.0 Gate voltage (V)

0.0

77°K

0.7

100Hz

0.6 0.5 0.4 0.3

0.2 -3

1

0.7

2

2

-3


0.4

0.6


0.6


77°K

0.7

2


p-In0.53Ga0.47As-Al2O3-Pt

1MHz -2

2

-1

180°K

0.7


0.6 0.5 0.4 0.3 0.2 -2

-1


3

*

H.C. Lin et al., Microelectronic Engineering 86, 1554 (2009)



25

3

Dit distribution of In0.53Ga0.47As with Al2O3 (S-pass.): Conductance method Analysis of the trap properties: Gp/Aωq-f of p-InGaAs at 25°C

Schematic band diagram EC

0

EF EV Vg = 0.5 V

EC + 0

EF Vg = 0.1 V EV

Band bending fluctuations increase as the Fermi level approaches the valence band => donor-like interface states. © IMEC 2010 / CONFIDENTIAL


26

Dit distribution of In0.53Ga0.47As with Al2O3 (S-pass.): Full electrostatic simulations* p-In0.53Ga0.47As-Al2O3-Pt

n-In0.53Ga0.47As-Al2O3-Pt

Dit (1012/eVcm 2)

40

Acceptor D it Donor Dit

30

20

10

0

0

Ev

0.1

0.2

0.3

0.4

0.5

E-Ev (eV)

0.6

0.7

0.8

Ec

0.9

1

Large acceptor-like Dit peak in the conduction band allows good fit of experimental quasi-static C-V data * G. Brammertz et al., APL 95, 202109 (2010) © IMEC 2010 / CONFIDENTIAL


27

Comparison: Conductance method – electrostatic simulation* 40 D it from electrostatic simulations

Dit (1012/eVcm 2)

35

D it from conductance method

30 25 20 15 10 5 0

0

Ev

0.2

0.4

0.6

E-Ev (eV)

0.8

Ec

Conductance method

1

Electrostatic simulations

Horizontal errors arise from:

Capture cross section uncertainty

Gate metal work function uncertainty

Vertical errors arise from:

Cox limitation of conductance

Cox limitation of capacitance

Uncertainty on Cox value

Uncertainty on Cox value Non-parabolic conduction band Charge quantization

Within the error margins there is good agreement between the electrostatic simulation model and the conductance data * G. Brammertz et al., APL 95, 202109 (2010) © IMEC 2010 / CONFIDENTIAL


28

Dit distribution of In0.53Ga0.47As-amorphous oxide interfaces InGaAs-Al2O3 (ALD)

InGaAs-HfO2 (ALD)

40

40

40 35

Donor Dit

Dit (1012/eVcm 2)

30 25 20 15 10

25 20 15 10 5

0

0 0

0.2

0.4

0.6

0.8

1

E-Ev (eV)

Acceptor Dit

35

Donor Dit

30

5 0

Acceptor D it

Dit (1012/eVcm 2)

Acceptor D it

35

Dit (1012/eVcm 2)

InGaAs-Al2O3 (MBE) Donor Dit

30 25 20 15 10 5

0.2

0.4

0.6

0.8

E-Ev (eV)

1

0

0

0.2

0.4

0.6

0.8

1

E-Ev (eV)

Not shown here, but also measured and showing similar interface state distribution: • InGaAs-Al2O3 (ALD, O3) • InGaAs-LaAlO3 (ALD, O3) • InGaAs-Ge-GeO2-Al2O3 (MBE) • InGaAs-GdAlO3 (ALD) • InGaAs-ZrO2 (ALD) The interface state distribution of the In0.53Ga0.47As-amorphous oxide interface depends rather little on the nature and the deposition conditions of the oxide. Nevertheless, Hf- and Zr-based oxides usually show higher Dit at the conduction band edge energy as compared to Al-, Gd- and La-based oxides. © IMEC 2010 / CONFIDENTIAL


29

Effect of ALD precursor H2O vs O3 n-In0.53Ga0.47As with HCl-clean and 10 nm ALD Al2O3 O3 ALD precursor

H2O ALD precursor 0.8

Capacitance ( µ F/cm 2)


0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1

0.7 0.6 0.5 0.4 0.3 0.2 0.1

0 -3

-2

-1

0

1

2

0 -3

3

-2

-1

40 Donor D it

30

Dit (1012/eVcm 2)

Dit (1012/eVcm 2)

1

2

3

40 Acceptor D it

35

25 20 15 10 5 0

0

Gate voltage V g (V)

Gate voltage V g (V) 35

Acceptor D it

30

Donor Dit

25 20 15 10 5

0

0.1

0.2

0.3

0.4

0.5

0.6

E-Ev (eV)

0.7

0.8

0.9

1

0

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

E-Ev (eV)

O3-based ALD increases the Dit at the conduction band edge energy as compared to H2O-based ALD © IMEC 2010 / CONFIDENTIAL


30

Effect of forming gas anneal n-In0.53Ga0.47As with (NH4)2S-clean and 10 nm ALD Al2O3 with FGA

No FGA 0.8

Capacitance (µ F/cm 2)


0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1

0.7 0.6 0.5 0.4 0.3 0.2 0.1

0 -3

-2

-1

0

1

2

3

0 -3

-2

-1

Gate voltage V g (V) Acceptor D it

2

3

30

Acceptor D it

35

Donor Dit

Dit (1012/eVcm 2)

2

Dit (10 /eVcm )

35

12

1

40

40

25 20 15 10 5 0

0


Donor Dit

30 25 20 15 10 5

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0

0

0.1

E-Ev (eV)

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

E-Ev (eV)

Forming gas anneal reduces the Dit over the full bandgap. 80% of the improvement is a thermal effect and not related to H (not shown). © IMEC 2010 / CONFIDENTIAL


31

Effect of (NH4)2S clean n-In0.53Ga0.47As with 10 nm ALD Al2O3 and FGA (NH4)2S clean

HCl clean 0.8



0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1

0.7 0.6 0.5 0.4 0.3 0.2 0.1

0 -3

-2

-1

0

1

2

3


0 -3

Acceptor D it

35 30

0

25 20 15 10 5

1

2

3

Gate voltage V g (V) Acceptor Dit

35

Donor D it

Dit (1012/eVcm 2)

Dit (1012/eVcm 2)

-1

40

40

0

-2

Donor Dit

30 25 20 15 10 5

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0

0

0.1

E-Ev (eV)

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

E-Ev (eV)

(NH4)2S cleaned samples are better than HCl (10%) cleaned samples. The difference between the two interfaces is rather small though. © IMEC 2010 / CONFIDENTIAL


32

Effect of oxide scaling n-In0.53Ga0.47As with (NH4)2S-clean, ALD Al2O3 and FGA 10 nm Al2O3

1.6

1.6

1.4

1.4



5 nm Al2O3 1.2 1 0.8 0.6 0.4 0.2

1.2 1 0.8 0.6 0.4 0.2

0 -3

-2

-1

0

1

2

0 -3

3

-2

-1

Gate voltage V g (V) Acceptor D it

35

2

3

30

Acceptor Dit

35

Donor D it

Dit (1012/eVcm 2)

Dit (1012/eVcm 2

1

40

40

25 20 15 10 5 0

0


Donor D it

30 25 20 15 10 5

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0

0

0.1

E-Ev (eV)

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

E-Ev (eV)

Dit profile does not change much when the Al2O3 is thinned to 5 nm © IMEC 2010 / CONFIDENTIAL


33

Comparison to literature results n-type 2


0.7

2


p-type 0.6 0.5 0.4 0.3 0.2

0.7 0.6 0.5 0.4 0.3 0.2

-3

-2


Sputtered HfO2 Kim et al., APL 93, 062111 (2008)

2

3

ALD Al2O3 Xuan et al., EDL 28, 935 (2007)

MBE HfO2 Hwang et al., APL 96, 102910 (2010)

ALD Al2O3 Shin et al., APL 96, 152908 (2010)

ALD HfO2 O’Connor et al., APL 92, 022902 (2008)

ALD AlN-HfO2 Shahrjerdi et al., EDL 29, 558 (2008)

-2


2

MBE LaAlO3 Goel et al., APL 91, 091507 (2007)

ALD ZrO2 Koveshnikov et al., APL 92, 222904 (2008)

ALD Al2O3 Kim et al., APL 96, 012906 (2010)

Sputtered HfO2 Kim et al., APL 93, 062111 (2008)

Sputtered Si-HfO2 Zhu et al., ESL 12 (4), H131 (2009)

There does not seem to be any In0.53Ga0.47As/oxides interface in literature that diverges considerably from this picture © IMEC 2010 / CONFIDENTIAL


34






35

Dit distribution of InP with Al2O3 (S-pass.) : Conductance method

0.25

0.15 0.10 -2

-1

0

1

2

0.6 0.5 0.4 0.3 0.2 -1

Gate voltage (V)

0

1

2

Gate voltage (V)

3

0.6

180K n-type

0.5 0.4

2

2

2

0.20

-3

300K n-type


0.30


0.35


0.7

300K p-type

2


0.40

0.3 0.2 0.1

0.6

77K n-type

0.5 0.4 0.3 0.2 0.1

-1

0

1

2

Gate voltage (V)

3

-1

0

1

2

Gate voltage (V)

InP presents very large Dit in the lower half of the bandgap that is impossible to measure as the Fermi level pins well before reaching that part of the bandgap. Dit close to the conduction band edge energy is low, similar to InGaAs. © IMEC 2010 / CONFIDENTIAL


36

3



GaAs/oxide interface properties In0.53Ga0.47As/oxide interface properties InP/oxide interface properties Electrostatic effect of interface states on MOS-HEMT devices • Conclusions

• • • •



37

MOS implant-free quantum-well transistor Transistor geometry: Gate metal

Al2O3

SiO2 n+InGaAs

1.

Highly doped n+ source and drain are in-situ grown and etched on top of the channel.

2.

After surface clean, ALD Al2O3 oxide is grown followed by gate metal deposition.

3.

Source and Drain areas are opened and contacted with a metal.

30 nm ud-In0.53Ga0.47As 100 nm ud-In0.53Al0.47As SI-InP substrate

Band diagrams:

Off

1

On

0.5

Potential (eV)

Potential (eV)

0.5 0 -0.5 -1 -1.5

0

20

40

60

80

100

120

Position (nm)



0

-0.5

-1

-1.5

0

20

40

60

80

100

120

Position (nm)

38

Device:

- 4 nm EOT oxide. - Metal gate (Φm = 4.7 eV). - Dit distribution as measured on capacitors.

10

2

Surface potential (V)

1 0.8

10

0

0.6 0.4 10

0.2 0

Off

-0.2 -1.5

-1

-0.5

On 0

0.5

10 1.5

1

-2

-4

Semiconductor charge (10 12/cm 2)

1D electrostatic device simulation: In0.53Ga0.47As/oxide interface

~3 1012 cm-3 mobile carriers in channel SS ~ 110 mV/dec.


Off

40 35

35 30

~1012 cm-3 fixed charges

25 20 15

Dit (1012/eVcm 2

Dit (1012/eVcm 2

30

10

~2 1012 cm-3 fixed charges

25 20 15 10

+

5 0 0

On

40

0.1

0.2

0.3

0.4

0.5

0.6

-

5 0.7

0.8

0.9

0 0

1

E-Ev (eV)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

E-Ev (eV)

Influence of Dit on the electrostatics of the device is relatively limited. © IMEC 2010 / CONFIDENTIAL


39

Comparison to experimental data1 Gate metal

2

Gate oxide: 8 nm ALD Al2O3

Al2O3

Pretreatment: HCl + (NH4)2S Channel: 30nm ud-InGaAs (53%)

SiO2

*

FGA @ 370C,15min

n+InGaAs

30 nm ud-In0.53Ga0.47As 100 nm ud-In0.53Al0.47As SI-InP substrate

CET

3.8 nm

S.S.

115 mV/dec

Low field mobility

1600 cm2/Vs

10 µm gate length device: 40 30

Vg

30

2V 1.5V 1V 0.5V

gm (mS/mm)

Id (mA/mm)

50

20

20

Vd 2.1V 1.6V 1.1V 0.6V 0.1V

10

10 0 0.0

0.5

1.0 1.5 Vd (V)

2.0

2.5

0 -3

-2

-1

0

1

2

3

VG (V)

Experimental subthreshold slope in agreement with measured Dit values 1 A. Alian 2 © IMEC 2010 / CONFIDENTIAL

et al., submitted to Microelectronic Engineering (2010). H. Zhao et al., JVST B 27 (4), 2024 (2009). G. Brammertz, PT/LDD

40

*

1D electrostatic device simulation: InP/oxide interface

*

- 1 nm EOT oxide (1.6 nm CET). - 2 nm InP top layer – In0.53Ga0.47As channel. - Metal gate (Φm = 4.9 eV). - Dit distribution as measured on capacitors. 10

2

Surface potential (V)

1.5

10

1

0.5

10

Off

0 -1.5

-1

-0.5

On 0

0.5

1

10 1.5

0

-2

-4

Semiconductor charge (10 12/cm 2)

Device:

M. Radosavljevic et al., IEDM 2009.

~3 1012 cm-3 mobile carriers in channel SS ~ 90 mV/dec.

Off

50

Acceptor Dit Donor Dit

40

30

~1012

20

cm-3

fixed charges

10

0 -0.2

0

0.2

0.4

0.6

0.8

+ 1

1.2

1.4

Interface state density D it (1012/eVcm 2)

Interface state density D it (1012/eVcm 2)


On

50

Acceptor Dit Donor Dit

40

30

20

~ no fixed charges

10

0 -0.2

0

0.2

0.4

0.6

0.8

1

1.2

1.4

Ef-Ev (eV)

Ef-Ev (eV)

Influence of Dit on the electrostatics of the device is relatively limited. © IMEC 2010 / CONFIDENTIAL


41

Conclusions Schematic representation of different III-V/amorphous oxide Dit profiles. GaAs

InP

In0.53Ga0.47As

Acceptor Dit

1.6

Donor Dit

?

1.4

Acceptor Dit

1.6

Donor Dit

1.2

Acceptor D it

1

1.4

Donor Dit 0.8

1.2 0.8

E-E (eV)

1

v

E-E (eV)

0.6 0.4

0.6

v

v

E-E (eV)

1

0.8

0.4 0.2

0.6 0.2

0 11 10

0.4 0 11 10

10

12

10 12

13

14

10

2

Dit (10 /eVcm )

10

13

10

14

Dit (1012/eVcm 2)

0.2 0 11 10

12

10

10

12

13

10

10

14

Dit (1012/eVcm 2)

Despite high Dit in most parts of the bandgap, nMOS devices based on InP and InGaAs interfaces move the surface potential in an energy region close to the FLSE with relatively low Dit, which makes close to ideal device operation possible. © IMEC 2010 / CONFIDENTIAL


42

Acknowledgements European Commission for financial support in the DualLogic project no. 214579.

IMEC core partners within the IIAP on Logic-DRAM.



43