Embedded Chip BuildUp Using Fine Line Interconnect

Embedded Chip Build-Up Using Fine Line Interconnect Ray Fillion, Charles Woychik, Tan Zhang, Don Bitting General Electric 1 Research Circle Niskayuna, NY 12309 [email protected] 518-387-6199 Abstract Advanced packaging technologies are driven by two generally balanced forces: performance advances being made by the semiconductor industry and the product requirements of the leading electronics markets. The semiconductor advancements include shrinking feature sizes and innovative transistor structures that provide ever more functionality per unit area of silicon and faster clock rates. One of the leading electronics markets is the portable electronics market, covering cell phones, digital assistants, portable entertainment and digital cameras. These products are driving smaller and thinner packages, finer featured substrates, multichip packages, such as SiPs (System-in-Packages) and 3-D stacking. They are also driving to mixed analog, digital, and RF circuitry within one package with increasing concerns with interconnect parasitics, EMI shielding and thermal performance. A new family of embedded chip packaging and interconnection approaches are being developed to address the next generation portable electronics circuits. These embedded chip approaches feature embedded actives and passives, micro-vias, thin film polymer dielectrics and fine line build-up interconnections. This paper will look at a number of embedded chip approaches including the GE Embedded Chip Build-Up technology and analyze the electrical, density, reliability and cost advantages of this approach and show examples of its use in chip scale, chip carrier, and SiP applications for portable electronics applications.

Embedded Chip Approaches In response to these issues an increasing number of companies and research centers are developing embedded chip packaging approaches that eliminate the density and performance limitations of these current packaged part approaches. In all of these embedded chip approaches, multiple bare chips are placed within the interconnect structure, eliminating the package and the wirebond or solder joint connections to the circuit board. One of the most publicized embedded chip approach is Freescale’s Redistribution Chip Package (RCP)1. It is targeted at high volume, high performance chip sets for cell phones. The RCP process starts with a temporary frame with a releasable film in a wafer or panel format. Bare chips are placed face down onto the film with 3 to 6 chips or more per circuit. A molding compound is dispensed over the back side of the chips and cured to form the body of the package. The molded frame with its multiple set of components is released from the temporary film exposing the topside of the frame and the top surface of each chip. A liquid organic dielectric such as a polyimide, LCP, BCB, or other resin, is coated over the top of the frame, and cured to form the first build-up dielectric layer. Vias are photo-formed through the dielectric to the chip I/O pads. The surface is metallized and patterned forming the first build-up interconnection layer and the connections directly to the chip pads. Additional dielectric layers with microvias and interconnections are added as required. Typical cell phone modules with low to modest I/O chips (50 to 250) can generally be interconnected with only two build-up layers although RF shielding and reference plane requirements can require the addition of more build-up layers. An embedded RCP module from Freescale is shown in Fig 1.

Background Microelectronic packaging and interconnect is composed of device, package, board and system level fabrication and assembly. Devices are generally assembled into packages, mounted onto boards and electrically interconnected. Typically, bare die are mounted into surface mount packages and electrically interconnected to the package using wirebonds or solder bumps. The packages or, in the case of chip scale packages (CSPs), the devices themselves are then mounted onto a circuit board and connected using soldered perimeter leads or area array solder balls. Packages have much larger footprints than the chips, as much as 4 to 10 times larger and are much thicker, 4x or more, than the die within. Portable electronic applications such as cell phones are driven by the need to add more features while lowering envelope size (area and thickness). Conventional packaged parts not only make it difficult to meet the smaller footprints, but have high package parasitics and can be susceptible to EMI/EMS concerns.

1-4244-0985-3/07/$25.00 ©2007 IEEE

Fig. 1. Freescale RCP Radio-in-a-Package with Embedded Module on left and Full Assembly on right.

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Similar approaches have been developed at a number of European research centers. These include IMEC in Belgium, IVF in Sweden, and Fraunhofer IZM in Germany. In all of these approaches bare chips are placed into recesses in a substrate or in an opening through a substrate, and molded in place. The interconnect structure is built right over the top surface of the chips and over the substrate. Microvias are either photo-defined or laser formed and metallization is applied directly to the chip pads and the top dielectric surface. In some cases, the substrate contains interconnect structures or even integrated passives. A flexible embedded chip module from IMEC is shown in Figure 2.2 A cross-section of an Embedded Chip Module from Fraunhofer IZM is shown in Figure 3.3 Similar embedded chip approaches have been disclosed by Imbera and Intel.

heat are applied to bond the film to the surface of the die without voids. At this stage of the process, the chips are mechanically bonded to the film but there are not yet any electrically connections. There are a number of process and structure options available based upon the nature of the modules and their intended use. Chip scale and few chip SiPs go through a molding step that over molds the chips and the chip side of the film using the frame as a mold form. Liquid dispensed molding material such as a highly filled epoxy (for CTE control) is applied, covering the chips and is cured forming the molded body of the embedded chip module. Alternatively, for larger modules, a frame structure can be placed around each chip set for separate molding of each module site. Finally, the carrier can be left without molding, with just the chips bonded to the film. This structure permits bending of the circuit after processing to create a flexible module or a folded 3-D structure. The carrier is then flipped over and the processing of the build-up interconnect structure is initiated. Laser ablation using a UV laser is used to form micro-vias through the film and adhesive to the chip pads. After a standard plasma cleaning de-smear step, a seed layer of metal is applied to the top surface of the film, the micro-vias and the exposed chip pad metal. Because the chip pad metal may have an oxide layer, a sputter deposition is generally used to form a Ti barrier layer and a Cu seed layer. A standard semi-additive metallization and patterning process can be used that applies and photo-patterns a photoresist to open selected area of the seed metal. The exposed seed metal is plated-up in the microvias and in the areas of the top film surface where cover pads and routing traces are desired. Low current level circuits would be plated up to 1 – 2 microns while higher power circuits such as those used for high-end microprocessors could be plated up to 8 – 15 microns. Following plate-up, the remaining mask material is removed and the exposed seed metal is wet etched to complete the metal patterning. At this point the chips are electrically connected to the build-up structure. In a typical module, a second dielectric film is applied and bonded to the top surface of the metallized film using another polymeric adhesive. Again, pressure, vacuum and heat are used to cure the adhesive and bond the second film to the carrier. The laser ablation, metallization and patterning steps are repeated to form the second build-up interconnect layer. In simple chip sets, the circuit is completed with only these two build-up layers while in a complex, high I/O count chip set additional build-up layers may be required. At this point the fabrication steps are complete and each module site on the panel can be electrically tested prior to sawing the panel into individual modules. Figure 4 depicts a cross-sectional view of a complex mixed technology SiP that is truly a system-in-a-package. It contains a digital control chip, a thinned 3-D memory stack, a MEMS sensor chip, an analog chip that interfaces between the sensor and the control, an RF chip for wireless communication and a discrete IC for power management. The three-layer build-up structure includes both integral resistors and integral capacitors. Figure 5 shows a microphotograph of an ECBU cell phone module

Fig. 2. Flexible Embedded Chip Module from IMEC.2

Fig. 3. Cross-section of an Embedded Chip Module from Fraunhofer IZM.3 Embedded Chip Build-Up GE has also developed an embedded chip packaging approach, Embedded Chip Build-Up (ECBU), that is applicable to portable electronics. In the ECBU process, a fully cured polyimide film is mounted onto a frame to control dimensional stability during processing. The film is coated with a polymeric adhesive and cured to a “B-stage” condition, tacky but not viscous. Bare chips are placed face down onto the tacky adhesive and held in placed. Pressure, vacuum and

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containing six chips and more than 100 integrated passive elements. It is 2.5 cm square ECBU module a for a cell phone circuit. It is relatively large SiP because it is an old design, fabricated in 2000 using a 1998 chip set.

micro-via connections. Wirebonds are very resistive and inductive causing not only a severe transmission line discontinuity by a significant source of EM radiation. Solder bumps have moderate resistance and inductance but high capacitance. Organic adhesive bumps are similar to solder bumps except they have higher resistance and are not applicable to high performance or high reliability applications. The direct build-up layer to chip pad micro-via structure has low resistance, capacitance and inductance It has no measurable transmission line discontinuity and does not cause EM radiation. Cross-sections of a solder bump and of an ECBU micro-via are shown in Figure 6. The cell phone module shown in Figure 5 above was placed into a cell phone and electrically characterized. The cell phone with the ECBU module used the same chips and the same value of passives as did the standard cell phone, although most of the discrete passives were replace with integral, thin film passives. The analog signal performance was improved by a factor of 2X, with reduced noise, improved S/N ratio and increased range.

Fig. 4. Cross-Sectional View of an ECBU SiP with a Mix of Analog, Digital, RF, MEMS, and Power Chips and Thin Film Integral Passives

Fig. 6. Interconnect to Chip Connections: Flip Chip Solder Bump (left) and ECBU Micro-Via (right)

Table 1 Chip Connection Parasitics Fig. 5. ECBU cell Phone Module Containing Six Chips and More Than 100 Integral Thin Film Passives

Parameter

Embedded Chip Advantages In looking at embedded chip structures in general and specifically at the GE ECBU structure, there are a number of areas where there is significant advantages over conventional packaging approaches. We will look at electrical performance, EMI/EMS issues, area and volumetric density, robustness, and costs. Electrical Performance: In the case of electrical performance the two areas of concern in signal interconnections are the parasitics of the chip to build-up structure and the parasitics of the build-up structure itself. There are three standard structures used in connecting bare chips to an interconnect structure; wirebonds, solder bumps and organic adhesives. The key electrical parasitics of these connections are the resistance, the inductance and the capacitance of the connections as well as the level of transmission line discontinuities. Table 1 lists the typical parasitic resistance, inductance, and capacitance as well as the degree of discontinuity in wirebonds, solder bumps, conductive adhesives and direct

Wirebonds

Solder Bumps

Adhesive Bumps

Micro-via Metallization

Resistance- mΩ

30-100

1.0-3.0

15-30

0.2 - 1.0

Inductance- nH

1.0-3.0

0.05-0.1

0.05-0.1

0.01-0.03

Capacitance- pF

0.01-0.05

Discontinuities

Severe

0.002-0.01 0.002-0.01 0.0002-0.001 Moderate

Moderate

None

Density: The ECBU structure has unmatched area and volumetric density capability. Chips can be mounted almost edge to edge with silicon density (ratio of total chip area to module area) approaching 80% to 90%. Wirebonded modules are typically limited to 30% to 40% and flip chip modules to 60% to 70%. Module thickness is limited in the case of wirebonded modules to the thickness of the substrate plus the die thickness with adhesive and the wirebond height. This can add up to 500 to 800 microns, even with thinned die. Flip chip modules eliminate the wirebond height but add in the height of the bumps. These can range from 400 to 500 microns. The ECBU modules require only the die and buildup heights for total thickness in the range of 200 to 300 microns. Figure 7 below depicts cross-sectional

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representations of a wirebonded SiP, a flip chip bumped SiP and an ECBU SiP. ECBU module thicknesses have been demonstrated down to 100 microns, with either thinned chips or modules thinned after the processing is complete. The ECBU thinned module process is simple and does not require wafer thinning or chip thinning nor do thinned chips have to be handled. In this process variation, ECBU molded modules with typical unthinned die are fabricated in the normal way. The molded carrier is then placed onto a wafer-grinding table and the molding material and the bulk of the chip thickness are mechanically ground away. Thinning has been demonstrated on a six-chip cell phone module down to 50 microns of Si thickness and 50 microns of build-up structure. Figure 8 depicts this process sequence. Figure 9 shows a fully functional cell phone module from Figure 5 after thinning through the molding material and the chips to a thickness of only 100 microns.

component temperature cycling (TCB at –55 – +125C), assembly temperature cycling (TCA at 0 – 100C), HAST or Temp:Humidity to name a few.

Fig. 9. ECBU Cell Phone Module After Mechanical Grinding Through Molding Material and Chips to Thin The Module to 100 Microns. Multiple test lots of single chip ECBU test modules were tested to and successfully passed the JEDEC Level 4 220C and 260C Pre-Con, to 1000 TCB cycles and to UHAST 96 hours. High temperature storage, TCA and biased HAST will be run on a Cu/Low K test design. Full details of these tests and the test vehicles were presented at the 2007 Pan Pacific Symposium earlier this year.4 An additional issue facing cell phone applications, is the recently toughened drop shock test. Space qualification testing had shown that the ECBU structure was subjected to 110,000 G shock without failure or damage.5 Although sample modules will have to be subjected to the new drop shock test methodology, all past performance would indicate that drop shock will not be an issue.

Fig. 7. Cross-Sectional Representations of a) Molded Wirebond SiP, b) Flip Chip Bump SiP, and c) ECBU Sip.

Cost: It is very difficult to predict the cost of a new technology in high volume production that is only being run on a developmental facility and that is significantly different than any technology already in high volume production. The ECBU technology has only been run in the GE developmental facility in very low volumes and on a mix of prototype and production compatible equipment. Because the technology involves a mix of fine line fabrication process steps and precision assembly steps, there is no easy way to model the cost of the process before it gets transitioned into a production facility. Techlead Corp., Evergreen, CO, a microelectronics industry consulting company, develop a cost model for the ECBU process as it would run in a high volume facility. The cost model looked at similarities and differences in material sets, processing equipment, throughput rates, defect densities and estimated yields. First it looked at the relative cost of the ECBU process compared to that of a 32 cm2 square, 3:2:3 flip chip center core build-up carrier (three build-up layers on either side of a two layer PCB), targeted at a mid-range

Fig. 8. Cross-Sectional Depiction of the ECBU SIP Carrier Thinning Steps: a) Un-Thinned Module, b) Module Thinned to Chip Thickness, and c) Module Thinned to 100 Microns. Reliability: The ECBU technology was originally developed for military and aerospace applications. As such it was subjected to and passed all the normal military environmental tests (thermal cycling, thermal shock, high temperature storage, shock and vibration). In moving to apply the ECBU technology to commercial electronics such as high-end computing or portable electronics modules, the industry standard JEDEC reliability test requirements needed to be applied. These tests include solder reflow pre-conditioning,

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microprocessor. It did this for volumes of 0.5 to 10 million units per year. The cost factor for the ECBU module was 30% lower than that of the center core carrier, roughly $1.60 for ECPU verses $2.50 for the center core. It must be recognized that costs vary greatly by company, region and other factors and that these costs should only be used as relative cost not precise cost estimates. 6 In looking at applying this cost model to less complex portable electronics SiP modules a number of modifications were done to the model. First the SiP modules would be much smaller, allowing for more modules per panel unit area. The typical low end SiP module is assumed to by 10 mm square and the higher end SiP would be 1.4 mm square or one-tenth and one-fifth respectively of the area of the processor module. Second, the SiPs would only require two build-up layers rather than four typically needed for high-end processors. The assembly of the SiP would include placement of additional die per site, (4 or 6 chips verses 1 for the processor carrier) which adds additional capital equipment and costs. The cost estimate for the ECBU simpler module is forecast to be only $0.08 with the larger, the more complex module at $0.18. These cost predictions are based on assumptions on how the ECBU technology will be transitioned into a high volume facility, the equipment needed, through-put, hands on labor required and many other factors that are not verifiable without a operational, production facility.

A reliability and manufacturability demonstration project is underway with these IC houses and with one of their high volume fabricators. In addition, negotiations are underway to put the ECBU process into a US based production facility to support both the high-end processors application area as well as the portable electronics SiP application area.

Table 2 Complexity and Cost Comparisons Estimates of ECBU Modules for Various Application Areas.

References 1. Bartlett, G. et al, “Design and Process Technology, Multichip Modules , Packaging and Roadmaps (AE106)”, Freescale Technology Form, July 2006. 2. Christiaens, W, et al, “Polyimide Based Embedding Technology for RF Structures and Active Components,” Proc. 12th Pan Pacific Microelectronics Symposium, Maui, HI, Jan. 2007. 3. Neumann, A. et al, “Reliability Tests of a Stackable 3-D Package,” Proc. 14th European Microelectronics and Packaging Conference, June 2003, pp 352-357. 4. Woychik, C. et al, “Reliability Assessment of Embedded Chip Build-Up BGA Packages,” Proc. 12th Pan Pacific Microelectronics Symposium, Maui, HI, Jan. 2007. 5. Daum, W. et al, “High-G Multichip Modules for Defense Systems Using HDI,” Proc. International Society of Hybrid Microelectronics Conference, Boston MA, Nov. 1994, pp. 232-236. 6. Fillion, R., et al, “High performance, High Power, High I/O Chip-on-Flex Packaginh,” Proc. 15th European Microelectronics Packaging Conderence, Brugge Belgium, June 2005.

Application Area

Chip Count

Module Build -Up Area cm2 Layers

High-end Microprocessors

1

10

4

$1.60

Processor Plus Support Chips

4

12

4

$1.80

Cell Phone SiP Small

4

1

2

$0.08

Cell Phone SiP Large

6

2

2

$0.18

Conclusions The ECBU technology has been targeted at solving the packaging problems of the next generation high-end processor chips in BGA and PGA carriers. A demonstration project is now underway to apply a simplified version of the ECBU technology to the fabrication of few chip SiP modules for use in portable electronics such as cell phone mixed mode modules. The ECBU structure has demonstrated significant advantages in the area of electrical performance, size and density and reliability. A cost model has been developed that modeled the relative fabrication costs of the ECBU technology as compared to standard flip chip build-up approaches. The cost model predicts that the ECBU technology would have a 20 to 30% cost advantage over current high-end approaches. A significant effort is underway to put the ECBU technology into a low cost, high volume production facility to support high-end processor applications. This is being extended with a follow up project to put this technology into production for SiP modules targeted at portable electronics applications such as cell phones.

Cost Basis

Commercial Scale-Up Plans As of this publication date, the ECBU process is only being practiced in the GE Global Research Center prototype facility in upper state New York. Agreements are in place with a number of semiconductor fabricators that together produce more than 200 million complex processors per year.

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