Quality Requirements at Chip Level. â¡ Manufacturing Test for Chips. â¡ To achieve board defect levels < 1%. â¡ To maintain ATE cost. â¡ Diagnostics for Chip ...
Embedded Quality for Test Yervant Zorian LogicVision, Inc.
Electronics Industry n
Achieved Successful Penetration in Diverse Domains
Electronics Industry (cont) n
Met User Quality Requirements – satisfying users’ to buy products again
ers Us
Co m pe tito rs
Created an Unprecedented Dependency - market-driven product
Electronic Product
Quality Requirements at Chip Level n
Manufacturing Test for Chips n n
n
To achieve board defect levels < 1% To maintain ATE cost
Diagnostics for Chip Manufacturing n n
To enable physical failure analysis To enhance yield by enabling repair for large memories
Quality Requirements at Board Level n
Board Level Manufacturing Test n n
n
Full Coverage of board level defects Chip failures (handling, stress, infant mortality)
Diagnostics for Board Level Manufacturing n n
To determine failed interconnect or chip To enable speedy repair
Conventional Test Flow n n n
Functional Patterns Deterministic ATPG with Scan Path Full Pin Count Automatic Test Equipment
Emerging Electronics Industry n
Products Shift to Communications and Connectivity
n
Maintain competitive edge by providing: – – – –
Greater Product Functionality Lower Cost (product life cycle) Reduced Time-to-Profitability Higher Quality and Reliability
Emerging Infrastructure “The internet runs on silicon.” Andy Grove
“The information superhighway is paved in silicon.” Scott McNealey
Emerging Industry Trends n Caused
new technologies:
Greater Complexity Increased Performance Higher Density Lower Power Dissipation
The Key Challenge n
n
To meet Users’ Quality Requirements for new Technologies To assure New Products are adequately: Tested, Verified, Measured, Debugged, Repaired, ...
Emerging New Challenges
n
Observe Implications on Product Realization Analyze Existing Quality Assurance Approaches Identify Challenges
n
Demonstrate Potential Solutions
n n
Design
Manufacturing
Diag. & Yield
Field Service
Design Challenge: Quality n
Implications of SIA Roadmap: Testing
Implication:
Testing Complexity Index - [#Tr. per Pin]
– # of Transistors per pin (Testing Complexity Index)
1.60E+ 5 1.40E+ 5 1.00E+ 5 8.00E+ 5 6.00E+ 4 4.00E+ 4
– increased internal speed vs external
2.00E+ 4 0.00E+ 0 Year 1992 F. Size [µm] 0.5
1995 0.35
1998 0.25
2001 018
2004 0.12
2007 0.1
Source: W. Maly, 1996
Source: SIA Roadmap
Design
Manufacturing
Diag. & Yield
Field Service
Design Challenge: Quality Leverage Internal Bandwidth vs External Bandwidth
ASIC
off-chip bus 32-bits
I/O Drivers
System-on-Chip I/O Drivers
n
on-chip bus
DRAM
ASIC
DRAM 128/512-bits
Design Challenge: Quality
n
External Bandwidth – max bits of data/time from ATE to IC
250
Internal Bandwidth
150
max bits of data/time from onchip test resource to embedded core
n
Bandwidth Gap
200
100 50
Internal Bdw. (Capacity*IntFreq
Bandwidth Gap
n
0 Y1995 Y1998 Y2001 Y2004 Y2007 Y2010
External Bdw (IO*ExtFreq)
Design Challenge: Quality n
n n
External Test Data Volume can be extremely high (function of chip complexity) Requires deep tester memory for scan I/O pins Slow test throughput with long scan chains, especially for core-based designs
External Test
Memory
Super Tester
Logic Pattern Generation Precision Timing Diagnostics Power Management Test Control
.
MixedSignal
Very high pin count Deep memory
Slow throughput
I/Os & Interconnects
Design Challenge: Quality Solution: Dedicated Built-In H/W for embedded test functions n Repartition tester into embedded test and external test functions n
Include low H/W cost and high data volume embedded-quality for test n
Memory Embedded Test External Test Standard Digital Tester Limited Speed/ Accuracy Low Cost-per-Pin
(Built-in) Pattern Generation Result Compression Precision Timing Diagnostics Power Management Test Control Support for Board-level Test System-Level Test
Logic .
MixedSignal
I/Os & Interconnects
Chip, Board or System Source: LogicVision
Design Challenge: Quality Source/ Sink
Source/ Sink
Scan Paths
Test Access
External Test
External Test
Source/ Sink
Source/ Sink
HighBandwidth
Low bandwidth
External Test
Embedded Test
External Test
Embedded Test
Source/ Sink
High bandwidth
Embedded Test
Design Challenge: TTM Implication: Emergence of reusable core-based design n
n
n
Multiple hardware description levels (hard, soft, firm) Standard IC functions (library elements) and legacy cores
Source: VSI Alliance
SOC Market Growth Worldwide Revenue (Billions of Dollars) 30 25 20 15 10 5 0
1998
1999
2000
2001
2002
2003 Source: Dataquest
Paradigm Shift in SOC Design
System on a Chip
System on a board
Design Challenge: TTM n n n
n n
SOC manufactured and tested in single stage Core I/Os often more than Chip I/Os Test generation difficult due to limited core design knowledge Direct access to core ports unavailable Core & UDL test part of System-On-Chip test
System-on-Board (SOB) Process IC Design
ASIC Design
IC Manuf.
ASIC Manuf.
IC Test
ASIC Test
System-on-Chip (SOC) Process Core Design UDL Design
SOC Integration SOB Design SOB Manuf. SOB Test
SOC Manuf. SOC Test
Design Challenge: TTM n
Built-in dedicated H/W to create autonomous internal core test
Built-in dedicate SystemOn-Chip test optimization n
Built-In standard core test interface for each core n
Design Challenge: TTM n
IEEE P1500 (9/96) develops a standard for embedded core test interface comprised of: – Standard Core Test Information Model (CTL) using a Standard Description Language (STIL) – Standard Core Test Wrapper and Control Mechanism – Phase 1: Dual Compliance for Digital Cores (1149.1) – Phase 2: Analog Cores (1149.4), Testability Guidelines
n
VSI Manufacturing Test Related DWG supports IEEE P1500 standardization
Design Challenge: TTM Glue Logic
BIST Enabled Core
BIST Enabled Core
TP
TP
M BIST
Memory BIST
Logic BIST
Logic BIST
Glue Logic BIST Enabled Core BIST Enabled Core
TP
TP
M BIST M BIST
Logic BIST
Logic BIST
Logic BIST 1149.1 TAP TDI
TCK
TMS
TRST
TDO
Boundary Scan Chain
Boundary Scan Chain
M BIST
Design Challenge: Quality n
Implication: Increased chip internal speed (ASSP with 200MHz+, Microprocessors with 1 GHz+) – Multiple and overlapping clock domains – Multi-cycle data paths – Complex clock distribution
n
Recent SEMATECH study revealed criticality of performance faults
Design Challenge: Quality Time in nS nS,, Yield loss in %
n n
n
1000 High speed ATE substantially more expensive device speed (nS) projected yield loss (%) 100 ATE vs Chip Technology discrepancy: Tester uses 5 year old technology - chips move to 10 next generation every 2 years 1 ATE accuracy degrading: Chip ATE OTA(nS) cycle time will crossover ATE accuracy 1980 1985 1990 1995 2000 2005 2010 2015
Design Challenge: Quality n
Solution: Built-In dedicated H/W to run Built-In Self-Test at-speed and detect performance faults
Major move for mainstream systems to implement at-speed BIST for production test n
Source: Sun Microsystems
Manufacturing Challenge: Test Cost Logic n n
Embed in a single chip: Logic, Analog, DRAM blocks Embed advanced technology blocks: – FPGA, Flash, RF/Microwave
n
Beyond Electronic blocks:
Logic
Manufacturing
µP
Core Memory
Memory
Logic
Memory
Logic
– MEMS – Optical elements
Design
Mixed Signal
Diag. & Yield
Field Service
Manufacturing Challenge: Test Cost W(5FB 8A3) R(4C2 9E0) …
W(5FB 8A3) R(4C2 9E0) …
Logic Functional Tester
Logic
Mixed Signal
µP
Mixed-Signal Tester
W(5FB 8A3) R(4C2 9E0) … W(5FB 8A3) R(4C2 9E0) …
Core Memory
Memory
Logic Tester
Logic
Memory
Logic
Memory Tester
Multiple Insertions or Super ATE!
Moore’s Law for Test Cost of Silicon Mfg and Test 1 0.1
Si capital / transistor
0.01 0.001 0.0001
Test capital / transistor
0.00001 0.000001 0.0000001 1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012
cost: cents /transistor
Based on SIA Roadmap Data
Manufacturing Challenge: Test Cost JTAG 4 Pin Interface
Logic
Low Cost Sort Machine with LogicVision BIST Access Software
Logic
Mixed Signal
µP
I/O’s tri-stated no critical timing
Core Memory
Memory
Logic
Memory
If full scan already exists then the dues are already paid
Logic LogicVision’s Embedded Test
Manufacturing Challenge: Quality n
High Density Chips: Advanced Semiconductor Technology with very high density n number of millions of transistors per sq. cm. will increase by a factor of three in next five years n Test Escape due to unmodeled faults (ex: SOI process, Copper Interconnect)
– Use built-In dedicated h/w to execute fault model independent pseudo-random pattern based test
Manufacturing Challenge: Quality n
n
Challenge: High performance board and MCM applications (ex: 500MHz chip-to-chip) Require Chip-to-Chip Interconnect test for static and dynamic faults
Source: Stratus Computers
Manufacturing Challenge: Quality n
Solution: – IEEE 1149.1 BoundaryScan for static faults – At-Speed Interconnect Test requires Built-In dedicated H/W
Source: Stratus Computers
Diagnosis & Yield Challenge: Cost n n
n
Implication: Large Embedded: SRAM, DRAM, Flash Beyond certain size memories necessitate redundancy/repair during manufacturing test (and field reliability) Requires Logic ATE, Memory ATE, Laser Repair Equipment, and Redundancy Analysis Design
Manufacturing
Diag. & Yield
Field Service
Diagnosis & Yield Challenge: Cost Two reconfiguration strategies: 1. Hard: Built-in dedicated h/w for Redundancy Analysis and external repair (fuse blow) 2. Soft: Built-In dedicated reconfiguration mechanism using BISR (test repeatability) n Adopted by several chip manufacturers
WAFER
n
Memory test Analysis & Reconf Memory retest
Logic test (wafer) Packaging Logic test (package) Pass/Fail Testing/Repair of ASIC with Large Embedded Memory
Memory Repair
Diagnosis & Yield Challenge: TTM n
Advanced Packaging Technologies – Increased use of Flip-Chip Technology: Flip-Chip design dedicates a metal layer for area array interconnects (Direct Chip Attach, Chip Scale Packaging, BGA and MCM) – Increased use of Fine-Pitch Technology: probing limitations due to miniaturized package technologies (FC, CSP) -> very expensive probe cards – Increased use of bare die usage -> inadequacy of conventional package test (Direct Chip Attach, MCM)
Diagnosis & Yield Challenge: TTM n
n
Conventional failure mode analysis based on E-beam can not be used with flip-chip Solution: Use Embedded Quality functions for diagnosis: stop-on-error, data logging for memories, and scan-based diagnosis for random logic. This can be leveraged for interactive atspeed diagnosis.
Flip-chip die
Diagnosis & Yield Challenge: TTM n
n
Conventional failure mode analysis based on E-beam can not be used with flip-chip Solution: Use Embedded Quality functions for diagnosis: stop-on-error, data logging for memories, and scan-based diagnosis for random logic. This can be leveraged for interactive atspeed diagnosis.
Flip-chip die
Diagnosis & Yield Challenge: TTM
–Source HPL, Inc.
Diagnosis & Yield Challenge: TTM
–Source HPL, Inc.
Field Challenge: Quality n
n
Challenge: Increase Impact of Cosmic Radiation on Sea Level
Solutions: Embedded test dedicated h/w function for On-line BIST to detect transient (soft) errors Design
Manufacturing
Diag. & Yield
Field Service
Field Challenge: Cost, TTM n
n
n
Design and Manufacturing of Complex Boards and Systems costs too much and takes too long Test development cost is 35% of total product development time Test, Diagnosis and Repair cost for complex systems reaches 40-50% of total product realization cost
Hierarchical Embedded Test OS / Software Interface (accessible by network) at the Application layer
Operating System and Applications
Service Kernel Software Hardware
ATE / Hardware Interface (accessible by connector) for Manufacturing or Field
EQ
EQ
Box Board SOC EQ
Source: LogicVision Reuse of dedicated built-in quality hardware
Field Challenge: Cost, TTM n
Leveraging dedicated Embedded Quality function drastically reduces test development interval and test costs
29.4 %
Without
3
10
16.4
Built-In Quality
With
3.6 2.5
Built-In Quality
1.6
7.7 % 0
5
10
15
20
25
30
Test Cost as % of Total Life Cycle Cost Source: AeroSpace Study
Conventional Quality Paradox
Design Test Management
Manufacturing Test Management
“It is really not my problem, but I will do what I can to help out.”
“I have little control on the design process! I will buy the best testers possible and perform as much testing as possible to ensure the expected quality.”
Test Resource Partitioning DFT Methods
External ATE
Logic Tester Memory Tester Mixed Signal Tester Processor Tester Board Tester
Embedded Test H/W Automation Tools Test Programs Diagnostic Data
Scan Design Isolation & Access Random Pattern BIST Algorithmic BIST 1149.1 TAP/BSCAN
A Solution that Combines the Best of DFT and ATE
Conclusions n
n
To ensure quality of electronic products using emerging technologies: – Embedded Quality functions are added into the high level designs of embedded cores, SOCs, board and systems A range of Embedded Quality functions provide adequate test, verification, diagnosis, debug, measurement and repair
Design
Manufacturing
Diag. & Yield
Field Service
Thank YOU for your attention
