Enhanced Channel Mobility at Sub-nm EOT by ... - IEEE Xplore

Received 23 February 2015; revised 2 May 2015; accepted 3 June 2015. Date of publication 10 June 2015; date of current version 21 August 2015. The review of this paper was arranged by Editor S. Ikeda. Digital Object Identifier 10.1109/JEDS.2015.2443172

Enhanced Channel Mobility at Sub-nm EOT by Integration of a TmSiO Interfacial Layer in HfO2/TiN High-k/Metal Gate MOSFETs EUGENIO DENTONI LITTA (Member, IEEE), PER-ERIK HELLSTRÖM (Member, IEEE), AND MIKAEL ÖSTLING (Fellow, IEEE) School of Information and Communication Technology, KTH Royal Institute of Technology, Stockholm 164 40, Sweden CORRESPONDING AUTHOR: E. DENTONI LITTA (e-mail: [email protected]) This work was supported in part by the European Union ERC Advanced Grant OSIRIS 228229 and in part by the Swedish Foundation for Strategic Research.

ABSTRACT Integration of a high-k interfacial layer (IL) is considered the leading technological solution

to extend the scalability of Hf-based high-k/metal gate CMOS technology. We have previously shown that thulium silicate (TmSiO) IL can provide excellent electrical characteristics and enhanced channel mobility at sub-nm EOT. This paper presents a detailed analysis of channel mobility in TmSiO/HfO2 /TiN MOSFETs, obtained through measurements at varying temperature and under constant voltage stress. We show experimentally for the first time that integration of a high-k IL can benefit mobility by attenuating remote phonon scattering. Specifically, integration of TmSiO results in attenuated remote phonon scattering compared to reference SiOx /HfO2 dielectric stacks having the same EOT, whereas it has no significant influence on remote Coulomb scattering. INDEX TERMS Thulium, silicate, TmSiO, HfO2, high-k, CMOS, mobility, scattering, RCS, RPS, EOT.

I. INTRODUCTION

High-k/metal gate complementary metal-oxidesemiconductor (CMOS) technology relies on the integration of complex multi-layer gate stacks in order to fulfill the requirements in terms of electrical performance and device reliability. The bulk high-k oxide layer, which commonly is a Hf-based dielectric (e.g., HfO2 , HfSiON), is deposited on top of a thin interfacial layer (IL), whose primary role is to ensure high electrical quality of the interface with the channel. In Si technology, a sub-nm-thick silicon oxide (SiOx ) layer, grown by low-temperature chemical oxidation, is often employed as IL [1]. While this approach benefits from the high-quality Si/SiO2 interface, the presence of a layer with low dielectric constant in the gate stack poses strong challenges to its long-term scalability. As a matter of fact, scaling of the equivalent oxide thickness (EOT) in SiOx /HfO2 dielectric stacks relies on reducing the physical thickness of the IL, which can be achieved in a controlled way by means of scavenging techniques [2], [3]. However, reducing the thickness of the

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IL has been shown to cause degraded mobility [4], [5], threshold voltage control [6] and reliability [7], severely limiting the scalability of SiOx interfacial layers below 0.4 nm. Channel mobility has especially been shown to degrade significantly with decreasing IL thickness due to increased influence of the remote scattering mechanisms. In general, high-k/metal gate field-effect transistors (FETs) are affected by additional scattering mechanisms originating in the gate stack and not directly in contact with or inside the channel (hence the appellative “remote”). Charged impurities and dipoles in the gate stack can interact with current transport in the channel, giving rise to remote Coulomb scattering (RCS), which adds to the Coulomb scattering (CS) from dopants in the substrate already present in SiON/poly-Si stacks [8]. Furthermore, high-k dielectrics exhibit soft optical phonon modes which can efficiently couple with carriers in the channel, resulting in remote phonon scattering (RPS) in addition to the phonon scattering (PS) caused by interactions with bulk Si phonons [9]. Finally, the local

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DENTONI LITTA et al.: ENHANCED CHANNEL MOBILITY AT SUB-nm EOT BY INTEGRATION OF A TmSiO IL

properties in terms of EOT, interface state density, threshold voltage control, reliability, and channel mobility [12], [13]. Specifically, we have shown a 20% improvement in nFET and pFET mobility at sub-nm EOT in TmSiO/HfO2 stacks compared to state-of-the-art SiOx /HfO2 devices [14]. In this work, we provide a detailed analysis of the channel mobility in sub-nm-EOT TmSiO/HfO2 /TiN MOSFETs. Measurements at high temperature and under constant voltage stress have been the means to identify the physical mechanism responsible for the observed mobility enhancement. Comparison to literature data on SiOx /HfO2 dielectric stacks is used to determine the effect of TmSiO on remote scattering mechanisms. II. EFFECT OF THE IL ON SCATTERING FIGURE 1. Schematics of the effect of remote scattering mechanisms on channel mobility. RCS, RPS, and RSRS cause degraded mobility over the whole Eeff range in high-k/metal gate stacks compared to conventional SiO2 and SiON dielectrics.

This section summarizes the main conclusions regarding the effect of the interfacial layer on channel mobility, on the basis of theoretical and experimental evidence available in literature, with the purpose of providing a reference and guideline for the evaluation of a high-k IL. A. REMOTE PHONON SCATTERING

EOT variations caused by roughness at the IL/high-k and high-k/metal interfaces and/or by fluctuations in dielectric constant can affect carrier mobility via remote surface roughness scattering (RSRS), in addition to the surface roughness scattering (SRS) caused by roughness at the channel/IL interface [10]. Remote scattering mechanisms show a dependence on inversion charge density (Ninv ) and effective field (Eeff ) which is qualitatively similar to that of bulk scattering mechanisms, i.e., CS and RCS are dominant at low Ninv and Eeff , PS and RPS at medium Ninv and Eeff , SRS and RSRS at high Ninv and Eeff . Comparing mobility curves in SiON/poly-Si and high-k/metal gate stacks, the effect of the additional remote scattering mechanisms is to reduce channel mobility over the whole Ninv and Eeff range (Fig. 1), although the relative importance of each mechanism depends on the specific gate stack employed. Integration of lanthanide silicates to replace the conventional SiOx IL has been proposed as a way to improve the scalability of high-k/metal gate stacks [11]. Replacement of the chemical oxide with a high-k IL can help achieve very low EOT of the IL while maintaining a reasonably high physical thickness, with positive effects on remote scattering rates. However, increasing the dielectric constant of the IL could also be detrimental to channel mobility, since a high-k IL can potentially introduce additional scattering sources in the gate stack, as well as improve the capacitive coupling of charged scattering centers in the HfO2 layer with carriers in the channel. Therefore, it is crucial to thoroughly analyze the effects of the integration of a high-k IL on channel mobility in order to evaluate the suitability of the technology to improve the scalability of high-k/metal gate stacks. In previous reports, we have shown that thulium silicate (Tmx Siy O, TmSiO hereafter) is a promising candidate for integration as high-k IL, providing excellent device 398

Remote phonon scattering was initially regarded as the main obstacle in the integration of high-k dielectrics in CMOS technology. Careful evaluation of RPS is especially important since this mechanism is intrinsically connected to the dielectric constant and the choice of materials. Theoretical and experimental works have shown that RPS can substantially affect channel mobility and that effective ways to reduce its effect consist in the integration of a metal gate electrode and of a sufficiently thick interfacial layer [9], [15]. The IL has been specifically shown to be beneficial in removing the scattering sources further away from the channel, resulting in an exponential attenuation of the scattering potential over the IL thickness [9]. Specifically, a SiOx IL thickness of 1 nm is necessary to render RPS negligible (at least at reasonably high inversion charge density), whereas thinner layers, such as those employed in current technology (∼0.4 nm thick), result in mobility penalties [15]. These results highlight the potential benefit of the integration of a high-k IL, since this could provide a very low IL EOT, necessary for gate length scaling, while keeping a sufficiently high physical thickness and consequently low RPS. Although the remote phonon scattering strength is a function of both IL physical thickness and IL dielectric constant, the dependence on the two parameters is markedly different. Whereas IL dielectric constant only appears in the pre-exponential multiplicative factor, the scattering strength depends exponentially on IL physical thickness [9]. This leads to the reasonable expectation that a 1-nm-thick high-k IL should be roughly as effective as a 1-nm-thick SiOx IL in attenuating RPS at medium-high effective field but present the advantage of a lower IL EOT. However, it is important that the IL itself does not introduce additional RPS, i.e., the choice of material for the high-k IL must consider an evaluation of the optical phonon modes. A silicate with VOLUME 3, NO. 5, SEPTEMBER 2015


dielectric constant in the range 10-15 may be the optimum choice, since it can provide negligible RPS [9] and at the same time a relatively high dielectric constant and a highquality interface with the channel [11]. As a matter of fact, formation of hafnium silicate via annealing in SiOx /HfO2 dielectric stacks has been reported to result in improved mobility [16]. B. REMOTE COULOMB AND SURFACE ROUGHNESS SCATTERING

RCS and RSRS are conceptually different from RPS, in that they depend both on the choice of materials and on process conditions. The thickness of the SiOx IL has been shown to be a crucial parameter in determining the entity of the two scattering mechanisms [8], [10], and experimental results have demonstrated a strong decrease in RCS- and RSRS-limited mobility when the IL thickness is aggressively scaled [4]. Extension of the results on SiOx IL to high-k IL is, however, not straightforward in this case. The RCS scattering potential depends rather strongly on both the physical thickness and dielectric constant of the IL [8]. The different situation, as compared to RPS, is evident when one compares the analytical models reported in [8] and [9]: whereas in both models IL dielectric constant appears in the preexponential factor and IL thickness appears in the exponent, the relative weight between the two is different. It is shown in [9] that the exponential attenuation of scattering potential over the IL depends on the IL physical thickness and on the density of carriers in the channel, resulting in strong attenuation at medium-high inversion charge density (where RPS is dominant) and low attenuation at low inversion charge density (where RCS is dominant). This leads to the qualitative conclusion that the increased physical thickness afforded by a high-k IL would not be as effective in attenuating RCS compared to RPS, and its higher dielectric constant would enhance the coupling between remote charged defects in the high-k and carriers in the channel. Additionally, the introduction of a novel material in place of well-optimized SiOx may have negative effects on the density of charged defects in the IL, increasing RCS. No specific evidence has been published on the effect of a high-k IL on RSRS, to the best of the authors’ knowledge. However, it can be argued that RSRS should also depend on both the physical thickness and dielectric constant of the IL, given its nature as local fluctuations of the electrical thickness. III. EXPERIMENT

Long-channel (3 μm gate length) MOSFETs were fabricated on 100 mm p-type (100) Si substrates (B doped, 20-40 cm), following a simplified gate-last CMOS process flow. After isolation and twin well implantation and drive-in (doping density of 1017 cm−3 ), source and drain areas were implanted using a dummy gate as mask and activated at 1050 ◦ C for 10 s. After dummy gate removal, the TmSiO/HfO2 /TiN gate VOLUME 3, NO. 5, SEPTEMBER 2015

FIGURE 2. Process flow for the fabrication of the TmSiO/HfO2 dielectric stack. The TmSiO IL is formed via a sequence of three steps: deposition of Tm2 O3 by ALD, annealing in N2 at 550 ◦ C for 60s, selective removal of the unreacted Tm2 O3 in H2 SO4 .

stack was deposited according to the following procedure (Fig. 2). Surface cleaning in H2 SO4 :H2 O2 (3:1) and 5% HF was performed immediately before loading in the ALD reactor, ensuring deposition of Tm2 O3 on H-terminated Si surface. Tm2 O3 deposition was performed at 225 ◦ C, using TmCp3 and H2 O as precursors [17]. The silicate IL was then formed by rapid thermal annealing (RTA) in N2 at 550 ◦ C for 60s (target physical thickness of 0.9 nm), followed by selective removal of unreacted Tm2 O3 in H2 SO4 . A full description and characterization of the TmSiO formation process can be found in [12] and [13]. HfO2 was then deposited by ALD at 350 ◦ C (target physical thickness of 2 nm), using Hf[C5 H4 (CH3 )]2 (OCH3 )CH3 and H2 O as precursors. A post deposition anneal (PDA) was performed in the ALD reactor at 350 ◦ C in O3 /O2 /Ar ambient. TiN (15 nm) was deposited by reactive sputtering as gate metal, followed by deposition of TiW (100 nm) by sputtering and gate patterning. 400 nm SiO2 was deposited by plasma-enhanced chemical vapor deposition (PECVD) as inter-layer dielectric and patterned with contact holes, followed by deposition and patterning of Ti/TiW/Al (10/100/200 nm) metallization. Forming gas anneal (FGA) in 10% H2 /N2 was performed at the end of the fabrication sequence for 60 min at 400 ◦ C. Channel mobility was measured by the split-CV technique at varying temperature and after constant voltage stress (CVS) for variable time. Most of the analysis was performed on nFETs due to limited availability of SiOx /HfO2 pFET data in literature. IV. RESULTS AND DISCUSSION

It has been shown that optimized, scaled SiOx /HfO2 gate stacks follow the same EOT-mobility curve, independently of the specific implementation details and device geometry (similarly to how SiO2 /poly-Si MOSFETs follow the same universal mobility curves independently of the specific fabrication details), since IL thickness is the dominant parameter determining mobility at sub-nm EOT [2]–[5]. This observation justifies comparing a novel high-k/metal gate stack toward state-of-the-art SiOx /HfO2 stacks in order to evaluate 399


FIGURE 3. Electron mobility versus effective field in a representative TmSiO/HfO2 /TiN MOSFET with EOT = 0.8 nm. Indicated in the graph are the points were low-field, medium-field, and high-field mobility values were taken for the following comparisons. All devices had a gate length of 3 µm, with an effective channel length of 2.9 µm and an extracted parasitic resistance of ∼ 600 µm.

its effective advantage in terms of EOT-mobility tradeoff. Specifically, scaled data published by IBM [4] and imec [5] have been used for the comparison here, since they best represent the state of the art in terms of both EOT scaling and gate stack optimization, to the best of the authors’ knowledge. The comparison is also fair since the devices considered here present a gate leakage current density comparable to state-of-the-art nFETs (0.7 A/cm2 at 1V gate bias), as presented in [13]. Adapting to the available literature data, low-field and high-field mobility values are measured at Eeff = 0.5 MV/cm and 1 MV/cm respectively, whereas peak mobility is used as an estimate of mediumfield mobility (Fig. 3). Fig. 4 shows a comparison of channel mobility in TmSiO/HfO2 and SiOx /HfO2 nFETs at low, medium and high Eeff . A ∼20% mobility improvement is observed in TmSiO/HfO2 devices compared to SiOx /HfO2 stacks at medium and high effective field, whereas little to no improvement is visible at low normal field. This observation supports a preliminary hypothesis that the high-k interfacial layer is effective in reducing RPS and/or RSRS while having negligible effect on RCS. However, direct numerical comparison can be affected by a variety of sources of error, therefore an in-depth analysis of the measured data has been performed to confirm the comparison and investigate the physical mechanisms behind the observed behavior. In order to investigate the influence of the different scattering mechanisms, an analysis of the temperature dependence of mobility has been performed, highlighting the entity of RPS, whereas measurements under constant voltage stress were employed to evaluate RCS. A. TEMPERATURE DEPENDENCE OF MOBILITY

Split-CV mobility has been measured on TmSiO/HfO2 /TiN nFETs in the range 250-425 K (Figs. 5 and 6). Evidence of 400

FIGURE 4. Electron mobility in TmSiO/HfO2 and reference SiOx /HfO2 nFETs at (a) low, (b) medium, and (c) high effective field. An improvement of at least 20% is measured at sub-nm EOT at medium and high effective field, whereas no significant enhancement in visible at low effective field.

strong RPS in high-k/metal gate stacks can be found in the temperature dependence of medium-field mobility, which takes the form of T-α , since the presence of easily excited VOLUME 3, NO. 5, SEPTEMBER 2015


FIGURE 5. Electron mobility versus inversion charge density measured on TmSiO/HfO2 /TiN MOSFETs at 250, 275, 300, 325, 350, 375, and 425 K.

FIGURE 7. Temperature sensitivity factor of mobility versus effective electric field for TmSiO/HfO2 nFETs and reference SiOx /HfO2 nFETs. TmSiO/HfO2 /TiN devices exhibit positive temperature sensitivity factor, confirming a dominant phonon scattering, with values close to SiOx /HfO2 /TiN devices with the same physical thickness of the IL.

useful in analyzing scattering mechanisms, since, applying Matthiessen’s rule, it can be decomposed in three terms due to CS, PS and SRS respectively: d (1/μCS ) d (1/μPS ) d (1/μSRS ) d (1/μ) = + + , dT dT dT dT

FIGURE 6. Medium-field mobility versus temperature for TmSiO/HfO2 /TiN nFETs at EOT ∼ 0.8 nm, in logarithmic scale. An exponential factor α =0.91 is extracted by linear regression, indicating dominant RPS at medium field.

soft optical phonons leads to lower values of α compared to SiO2 /poly-Si stacks [18]. Even though the experimental value of α can differ slightly from the theoretically expected value due to the contribution of other scattering mechanisms, values much lower than 1.5 (the calculated value when bulk Si phonons are dominant [18]) can be taken as indicative of high RPS. Experimentally, values in the range 0.8-1.1 have been reported for SiOx /HfO2 nFETs, values in the range 0.6-1.0 for SiOx /HfO2 pFETs [18]–[22]. The values of α extracted here for TmSiO/HfO2 /TiN MOSFETs, namely 0.91 for nFETs and 0.62 for pFETs, are thus indicative of dominant RPS at medium effective field. In order to compare RPS in TmSiO/HfO2 and SiOx /HfO2 dielectric stacks, the temperature sensitivity factor of mobility has been calculated, defined as d(1/μ)/dT. This factor is VOLUME 3, NO. 5, SEPTEMBER 2015

where the first term is negative, the second term is positive and the third term is approximately zero, taking into account the different temperature dependence of the scattering mechanisms [15], [23]. The sign and magnitude of the temperature sensitivity factor of mobility can thus be employed to identify the dominant scattering mechanisms in a given temperature range. Fig. 7 compares the values of the temperature sensitivity factor measured in TmSiO/HfO2 devices with those reported for SiOx /HfO2 stacks. The positive sign of the sensitivity factor confirms the previous conclusion of dominant phonon scattering, which is also reasonable given the experimental temperature range. More interesting is the fact that TmSiO/HfO2 stacks achieve values very close to SiOx /HfO2 stacks using a thick IL (0.9 nm, similar to the physical thickness of the TmSiO IL) but lower than SiOx /HfO2 stacks employing thinner IL. It can therefore be concluded that TmSiO is as effective as a similarly thick SiOx in reducing RPS. This result confirms the previous considerations that high-k interfacial layers can be beneficial thanks to the exponential decrease of the RPS potential over the IL physical thickness and that soft optical phonons arising from materials with relatively low dielectric constant (< 15) are not expected to couple efficiently with channel carriers, thereby their effect on mobility is negligible. 401


FIGURE 8. Electron mobility versus inversion charge density after constant voltage stress at 1.7 V for variable stress time up to 5000s in a representative TmSiO/HfO2 /TiN nFET. The monotonic mobility degradation at low to medium inversion charge density is indicative of stress-induced charged defects increasing remote Coulomb scattering.

FIGURE 9. Electron mobility versus constant voltage stress time at low, medium, and high effective field in a representative TmSiO/HfO2 /TiN nFET. Lines are guides for the eye. The comparison of mobility dependence on stress time at varying effective field shows that the effect of the stress is highest at low field, reasonably strong at medium field and weak at high field, showing the same effective field dependence as Coulomb scattering.

B. MOBILITY DEGRADATION VOLTAGE STRESS

UNDER

CONSTANT

In order to evaluate RCS, the degradation in channel mobility after CVS for varying time was analyzed (Figs. 8 and 9). The devices were stressed at a constant voltage of 1.7 V, where the value was chosen so as to minimize stress-induced degradations in subthreshold slope and gate current, therefore avoiding the introduction of additional sources of error in the interpretation of the mobility data. A total stress time of 5000s was applied, during which measurements were performed at log-spaced intervals. It can be seen that low-field 402

FIGURE 10. Interface state density and increase in total trapped charge density in a representative TmSiO/HfO2 /TiN nFET after varying constant-voltage stress time. The stress conditions do not affect the interface state density, which is constant at ∼ 7 · 1010 cm−2 , whereas a strong increase in oxide trap density is observed.

mobility is the most affected by the constant voltage stress, which is compatible with the plausible physical explanation of increased trapped oxide charge causing additional RCS. This is confirmed by comparing the increased total oxide trapped charge (NOT ), obtained from the measured threshold voltage shift, and the change in interface state density (NIT ), measured by charge pumping (Fig. 10). It is clear that the voltage stress, under room temperature conditions, does not affect the interface quality (since NIT is constant at about 7 · 1010 cm−2 over the whole stress time) but causes a strong increase in bulk trapped charge and a consequent mobility degradation. Even though interpretation of low-field mobility variation is subject to errors due to threshold voltage variations, it can be clearly seen that even the peak mobility is strongly degraded, confirming that an actual stress-induced effect is observed here. In order to confirm that the degraded mobility is indeed due to RCS, Fig. 11 shows that a linear correlation is observed between the inverse mobility and the increase in trapped charge, as expected for RCS [24]: 1 1 = + α (q · NOT ), μ μ0 where μ is the peak mobility after stress, μ0 is the peak mobility before stress, α is the scattering coefficient and q is the electron charge. The use of peak electron mobility in this evaluation ensures limited effect of any threshold voltage related errors on the analysis. The scattering coefficient α, which is a useful indication of the strength of RCS, has been extracted by linear regression as 2600 Vs/C, which is very close to the reported value of 2565 Vs/C for SiOx /HfO2 devices [24]. This leads to the conclusion that TmSiO is not effective in reducing RCS, which explains the similar mobility values observed at low Eeff for TmSiO/HfO2 and SiOx /HfO2 MOSFETs at the same EOT [Fig. 4(a)]. VOLUME 3, NO. 5, SEPTEMBER 2015


[5]

[6]

[7]

[8] [9]

[10] FIGURE 11. Reciprocal peak electron mobility versus increase in trapped charge density in a representative TmSiO/HfO2 /TiN nFET. The scattering coefficient α =2600 Vs/C is extracted via linear regression. The strong correlation is a reasonable proof that the mobility degradation is caused by an increased charged defect density and therefore an increased RCS.

V. CONCLUSION

We have analyzed the channel mobility in TmSiO/HfO2 MOSFETs, with the aim of determining the physical mechanism responsible for the observed 20% improvement compared to state-of-the-art SiOx /HfO2 devices. Mobility analysis over a wide temperature interval has allowed to characterize the effect of remote phonon scattering, which was found to be reduced compared to SiOx /HfO2 stacks. Remote Coulomb scattering has been analyzed via measurements under constant voltage stress and was found comparable to SiOx /HfO2 devices. The observed mobility enhancement at high effective field is therefore ascribed to the introduction of the high-k IL, which can achieve scaled IL EOT while maintaining a relatively high physical thickness, thereby resulting in reduced remote phonon scattering compared to SiOx IL at the same EOT.

[11]

[12]

[13]

[14]

[15] [16] [17] [18]

[19]

ACKNOWLEDGMENT

The authors would like to thank Myfab, the Swedish National Research Infrastructure for Micro and Nano Fabrication, for their contribution.

[20]

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EUGENIO DENTONI LITTA (S’12–M’15) received the M.Sc. degree in electronics engineering from the University of Salerno, Salerno, Italy, in 2010 and the Ph.D. degree in information and communication technology from KTH Royal Institute of Technology, Stockholm, Sweden, in 2014. His Ph.D. thesis dealt with integration of TmSiO in scaled CMOS technology. He is currently a Researcher at the Department of Integrated Devices and Circuits at KTH Royal Institute of Technology. His current research interests include advanced high-k/metal gate stacks for scaled Si and Ge MOSFETs.

MIKAEL ÖSTLING (M’85–SM’97–F’04) received the M.Sc. degree in engineering physics and the Ph.D. degree from Uppsala University, Uppsala, Sweden. He is a Professor of Solid State Electronics and the Department Head with KTH Royal Institute of Technology, Stockholm, Sweden. He was a Senior Visiting Fulbright Scholar with Stanford University, from 1993 to 1994, and a Visiting Professor with the University of Florida, Gainesville, in 1997. His research focus is on semiconductor devices. He has supervised 35 Ph.D. theses work. He is currently the Vice President of EDS and an Editor of the IEEE ELECTRON DEVICE LETTERS.

PER-ERIK HELLSTRÖM (M’13) received the M.Sc. and Ph.D. degrees in electrical engineering from KTH Royal Institute of Technology, Sweden, in 1995 and 2000, respectively. His Ph.D. thesis dealt with polycrystalline Si1-x Gex as gate material for CMOS technology. Since 2000, he has been a Research Associate with the School of Information and Communication Technology, KTH Royal Institute of Technology. He has coauthored more than 70 papers in refereed journals and conference proceedings. His current research interests include Si and Ge process technology for nano-scaled MOSFETs.

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