Enhanced performance of SERDES current-mode output driver using 0.13 µm PD SOI CMOS D. Kamel 1 , M. Dessouky 2 , and D. Flandre 1 1
Microelectronics Laboratory (DICE), Universit catholique de Louvain, 1348 Louvain-la-Neuve, Belgium. 2 Faculty of Engineering, Ain Shams University, Cairo, Egypt. E-mail:
[email protected]
Abstract— A current-mode output driver that supports SERDES applications is implemented using 0.13 µm Bulk and PD SOI CMOS technologies. Schematic simulation results confirm the enhanced performance of PD SOI for very high-speed interfaces. The PD SOI current-mode driver shows a 3 times lower data dependent jitter than the Bulk current-mode driver at the same 3.125 Gbps data rate of XAUI standard.
I. I NTRODUCTION Serializer/Deserializer (SERDES) has become a more appealing solution for high-speed interfaces than the traditional parallel interfaces. It is well known for its reduced signal interference, noise, crosstalk and pin count [1]. With supported data rates from 1.5 Gbps to 3.125 Gbps and typical output differential amplitudes between 500 mV and 1200 mV, a programmable multi-purpose SERDES can cover many of the available commercial standards. High-speed interface standards such as Serial Advanced Technology Attachment (SATA) [2], Peripheral Component Interconnect Express (PCI Express) [3] and 10 Gigabit Attachment Unit Interface (XAUI) [4] can be implemented on a single chip. The main constraints on the design of SERDES are the area, the jitter, the power consumption and the speed. In this context, the use of SOI technology can greatly enhance the performance of the SERDES output driver due to the inherently reduced junction capacitance [5]. The current-mode driver described in [6] is implemented in this work using 0.13 µm Bulk CMOS and Partially-Depleted (PD) SOI technologies provided by the same foundry. II. D ESIGN
OF
C URRENT-M ODE D RIVER
The working principle of the driver is shown in Fig. 1. It consists of five binary weighted segments that contain different number of elements. The pre-emphasis block is not shown for simplicity. In order to achieve 50 Ω on-die termination, a digitally calibrated resistor scheme is implemented to compensate process and temperature variations. The linearity of the ondie termination can be improved by using unsilicided poly resistor in series with an NMOS transistor having a resistance ratio of 8. A programmable binary weighted current mirror network is used to support different amplitudes and different pre-emphasis ratios. For the driver to operate properly using Bulk and PD SOI technologies, their main process parameters have to be studied. Table I shows that, at typical condition, PD SOI has 100 mV higher threshold voltage (Vth ) than
Bulk provided by the same foundry. This results in a slight increase (17%) in the dimensions of PD SOI transistors in the resistor network and in the current mirrors to maintain almost the same resistor ratio and current mirroring, respectively. The differential pairs are sized identically in Bulk and PD SOI since by specifying the load and the output voltage, the SERDES standard (here XAUI which is the most demanding) imposes the current bias of the driver. Power consumption is thus similar in Bulk and PD SOI CMOS technologies while performance comparison is focused on speed and jitter. III. P ERFORMANCE C OMPARISON The driver is designed using both technologies for a 2 pF and 50 Ω load. The capacitive load sums up Electrostatic Discharge (ESD), pad and packaging capacitances, while the 50 Ω resistor represents the line impedance. The bottom and sidewall capacitances of the source/drain are included in the simulations. Figures 2 and 3 show the eye diagrams of the driver implemented in Bulk and PD SOI, respectively, in typical condition (TT 1.2 V 27o C) at 3.125 Gbps for a number of different input data. The PD SOI driver clearly shows a much better eye opening in terms of less jitter and larger eye height such that it passes the XAUI mask (the only jitter considered in this context is the data dependent jitter). It is clear from Table II that PD SOI driver adds 2.8 times lower jitter than Bulk driver at typical condition and 2.4 times less at fast condition (FF 1.32 V -40o C). The underlying reason behind that is the 10 times reduction in junction capacitance of the PD SOI driver which allows faster charging and discharging of the output nodes despite the increased Vth . This is the main reason why PD SOI driver has a larger eye height than the one implemented in Bulk. However at slow condition (SS 1.08 V 125o C) the jitter improvement is only 1.5 times. This is due to the fact that the Vth in Bulk is lowered by 13% from typical to slow condition which improves the rise and fall times of the output nodes, while that of PD SOI is lowered by only 2%. It is worth mentioning that simulation of Bulk driver without junction capacitance showed a reduction of the data dependent jitter by a factor of 3. This clearly confirms the importance of the junction capacitances and the benefit of their reduction in SOI. As a result, the PD SOI output driver can even operate up to 5 Gbps and still present about the same jitter (19.2 ps) as the Bulk output driver operating at 3.125 Gbps, as shown in Fig. 4.
IV. C ONCLUSION The use of PD SOI enhances the jitter performance of the SERDES current-mode driver by almost 3 times, thanks to the reduced junction capacitance, despite the higher Vth which is a property of the selected foundry. In addition, the PD SOI driver can support 60% higher frequency having the same jitter as the Bulk driver.
TABLE II C OMPARISON OF SIMULATION RESULTS AT 3.125 G BPS (TT, FF AND SS REFER TO PROCESS CORNERS ON N -
ACKNOWLEDGMENT This work was supported in part by the Walloon Region project E-USER (WIST program).
/ P -MOSFET S ).
Parameter
Condition
Bulk
PD SOI
Jitter (ps)
TT 1.2 V 27o C FF 1.32 V -40o C SS 1.08 V 125o C
18.4 10 44
6.6 4.1 28.7
Eye height (mV)
TT 1.2 V 27o C FF 1.32 V -40o C SS 1.08 V 125o C
382 448 280
563 630 410
700 mV 600 mV
R EFERENCES
500 mV
[1] A. Morgenshtein and I. Cidon, “Comparative analysis of serial vs parallel links in NoC,” International Symposium on SoC, 2004, pp. 185-188. [2] The serial ATA international organization. [Online]. Available: http://www.sata-io.org/ [3] PCI-SIG. [Online]. Available: http://www.pcisig.com/ [4] 10 Gb/s Ethernet, IEEE Std. 802.3ae, 2002. [5] Jean-Pierre Colinge, Silicon-on-Insulator Technology: Materials to VLSI, 3rd Edition, Kluwer Academic Publishers, 2004. [6] D. Heidar et al., “Comparison of output drivers for high-speed serial links,” International Conference on Microelectronics ICM, Dec. 2007, pp. 329-332.
300 mV
400 mV 200 mV 100 mV 0 mV - 100 mV - 200 mV - 300 mV - 400 mV - 500 mV - 600 mV - 700 mV 0p
Fig. 2.
20 40 60 80 10 12 14 16 18 20 22 24 26 28 30 32 p p p p 0p 0p 0p 0p 0p 0p 0p 0p 0p 0p 0p 0p
Simulated eye diagram using Bulk technology at 3.125 Gbps.
700 mV 600 mV 500 mV 400 mV 300 mV 200 mV 100 mV 0 mV - 100 mV - 200 mV - 300 mV - 400 mV - 500 mV - 600 mV - 700 mV 0p
Fig. 1.
Current-Mode Differential Signaling Driver Block diagram.
Fig. 3.
20 40 60 80 10 12 14 16 18 20 22 24 26 28 30 32 p p p p 0p 0p 0p 0p 0p 0p 0p 0p 0p 0p 0p 0p
Simulated eye diagram using PD SOI technology at 3.125 Gbps. 700 mV
TABLE I 0.13 µM B ULK AND PD SOI T ECHNOLOGY PARAMETERS FOR HIGH - SPEED (HS) N -MOSFET (T
=
TYPICAL , F
=
FAST,
S = S LOW ).
600 mV 500 mV 400 mV 300 mV 200 mV
Parameter
Condition
Bulk
PD SOI
Vth (mV)
T 1.2 V F 1.32 V -40o C S 1.08 V 125o C
310 331.8 270
408 451 399.2
ION (µA/µm)
T 1.2 V 27o C F 1.32 V -40o C S 1.08 V 125o C
666 804.4 515.6
631 688.4 420
27o C
869.9 E-6
85.3 E-6
T 1.2 V 27o C
3.73 E-11
7.14E-12
27o C
Cbottom
(F/m2 )
Csidwall (F/m)
T 1.2 V
100 mV 0 mV - 100 mV - 200 mV - 300 mV - 400 mV - 500 mV - 600 mV - 700 mV 0p
Fig. 4.
20 p
40 p
60 p
80 p
10 0p
12 0p
14 0p
16 1 0p 80p
20 0p
Simulated eye diagram using PD SOI technology at 5 Gbps.
