porally changes the local drive current [3, 4]. ... nique is presented by Vemuru in [4] which considers the delay ... this section for a high-to-low output transition.
Estimation of On-Chip Simultaneous Switching Noise on Signal Delay in Synchronous CMOS Integrated Circuits Kevin T. Tang and Eby G. Friedman Department of Electrical and Computer Engineering University of Rochester
A ?? Abstract—On-chip parasitic inductance inherent to the power distribution network has becoming significant in high speed digital circuits. Therefore, current surges result in voltage fluctuations within the power distribution network, creating delay uncertainty. On-chip simultaneous switching noise should therefore be considered when estimating the propagation delay of a CMOS logic gate in high speed synchronous CMOS integrated circuits.
I. I NTRODUCTION As the operating frequency increases, the average on-chip current required to charge (and discharge) total load capacitance also increases, while the time during which the current is switched decreases [1]. Therefore, a large change of the onchip current occurs within a short period of time. The primary sources of the on-chip current surges are those logic gates that switch close in time to the clock edges in a synchronous CMOS integrated circuit. Because of the non-negligible parasitic inductance inherent to the on-chip power distribution network, large current surges result in voltage fluctuations in the power distribution network [2]. These voltage fluctuations are called onchip simultaneous switching noise (SSN). On-chip simultaneous switching noise affects the signal delay, creating delay uncertainty since the power supply level temporally changes the local drive current [3, 4]. Furthermore, logic malfunctions may be created and excess power may be dissipated due to faulty switching if the power supply fluctuations are sufficiently large [5]. A modified tapered buffer design technique is presented by Vemuru in [4] which considers the delay uncertainty caused by off-chip simultaneous switching noise. In addition to the many constraints encountered in the design of on-chip clock and power distribution networks, on-chip simultaneous switching noise should be considered when estimating the propagation delay of a logic gate in a synchronous CMOS integrated circuit [6]. II. O N -C HIP S IMULTANEOUS S WITCHING N OISE An analytical expression characterizing the on-chip simultaneous switching noise voltage at the ground railisdeveloped in , , and this section for a high-to-low output transition. are the parasitic inductance, resistance, and capacitance of the ground rail, respectively, as shown in Fig. 1. In order to develop an analytical expression characterizing the on-chip simultaneous switching noise on the ground rail, the short-circuit current is neglected based on an assumption of a fast ramp input signal,
for
(1)
Once the input voltage exceeds the threshold voltage of an NMOS transistor, the NMOS transistor turns ON and is assumed to operate in the saturation region during the input transition. The current through the NMOS transistor (!#" ), the parasitic inductance (!$ ), and the simultaneous switching noise voltage % ( ) are given, respectively, as /4
&( )* + ,- /.102,3 % !#" ' 5 !#" , 7 % 4 !$ 6 7 % !#$ 8 9# 7 ! $ 4 7
(2) (3) (4)
This research was supported by the Semiconductor Research Corporation under Contract No. 99-TJ-687 and by grants from Xerox Corporation, IBM Corporation, Intel Corporation, Lucent Technologies Corporation, and Eastman Kodak Company.
> ;@??
:
