Estimation of Probability of Different Functional Faults Caused by Spot Defects in VLSI Circuits Mykola Blyzniuk, Witold Pleskacz, Mychajlo Lobur, Wieslaw Kuzmicz Abstract - In this paper we consider practical approach for identification of types of functional faults caused by shorts in conductive layers of IC layout and estimation of probability of occurrence of identified faults. Keywords - Spot Defects, Layout, Critical Area, Functional Faults, Identification, Probability of Occurrence.
I. INTRODUCTION The problem of estimation and decrease of the influence of spot defects on IC manufacturability is still important. It is explained by the fact that shorts and opens caused by spot defects may result in significant yield loss in manufacturing of VLSI circuit [1]. The degree of influence of spot defects is determined by the IC layout sensitivity to these defects. Special attention should be paid to the reduce of sensitivity of conductive layers of IC layout. Traditionally when the problem of reducing the layout sensitivity to spot defects is solved the shorts and opens are considered as the defects that are always fatal. On the one hand, it does not matter for schematic and layout designers what type of functional fault will be caused by shorts and opens. It is quite enough for them to know that such fault is fatal, i.e. circuit does not work (does not perform its own function). On the other hand, the information about types of functional faults (caused by shorts and opens) and their probability of occurrence is important for the developers of VLSI circuits tests. It would ease the work on development and generating of test cycles if we were able to foresee which type of functional faults was dominant and which one was negligible [5]. The main goal of this work is the development of the approach for identification of types of functional faults caused by shorts and opens in conductive layers of IC layout and estimation of probability of occurrence of identified faults. II. FORMALISATION OF THE PROBLEM OF IDENTIFICATION AND ESTIMATION OF PROBABILITY OF VARIOUS TYPES OF FAULTS CAUSED BY SHORTS. This work is limited to investigation of the problem of identification of faults types and estimation of probability of occurrence of faults caused only by shorts in standard gates. Obviously it is necessary to perform the analog circuit simulation for all possible shorts (double Shdouble, triple Shtriple and shorts of higher order) between nets (nodes of schematic) using circuit simulator to determine all possible types of faults in a gate. Taking into account the fact that probability of occurrence of shorts of order higher than double is very small we can neglect these shorts. But even for the double shorts the problem of identification of fault type is complicated. The problem complexity is determined by the number of circuit simulations ( C N2 ) necessary for determination of the type of functional fault caused by double shorts. Here the question arises: is circuit simulation necessary for all shorts? Taking into account the fact that the model of probability of occurrence of shorts between certain nets of schematic is layout-driven the number of necessary circuit simulations may be considerably reduced. Let us consider the formalisation of the problem of identification of types of faults (caused by double shorts) and estimation of their probability of occurrence. Net
Dr. M. Blyzniuk and Dr. M. Lobur - Computer Faculty, State University "Lvivska politechnika", S. Bandery Str., 12, Lviv, 290646, UKRAINE, E-mails:
[email protected];
[email protected] Dr. W. Pleskacz and Prof. W. Kuzmicz - Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warszawa, POLAND, E-mails:
[email protected];
[email protected]
II.1. Identification of types of faults. For identification of types of faults caused by double shorts we introduce the concept of symbolic matrix of functional fault types FTF with the dimensions [ N Net × N Net ] where the matrix element fTF =" type short fault" , i ≠ j is the type of fault caused by shorted Neti with Netj. The type of short fault is determined by the results of comparison of analog simulation of gate with shorted nets and gate without faults. As the results of comparison we can identify the different types of faults, for example: a) the result of shorts is stable one on the output Q of the gate (ST1); b) the result of shorts is stable zero on the output Q of the gate (ST0); c) the result of shorts modify the function of the gate, for instance from Q=not(A+B+C+D) for 4-INPUT NOR gate to Q=not(A*B+C+D) or to Q=A*(not(B+C+D)) and so on. II.2. Estimation of probability of occurrence of identified faults. Determination of the total probability of short fault occurrence is usually based on the development of the defect placement methods or region expansion methods [3] (i.e. development model of critical area of layout for shorts [1]). We use the model of critical area [1]. This model reflects the dependence of critical area value for shorts S CrAr on the value of spot defects radius R. This dependence is obtained not analytically but on the basis of computer experiment with the use of the developed software tools which allow to extract the critical area for certain defect radius from a given layout. The probability of short for certain defect radius may be determined geometrically as Psh( R ) = S CrAr( R ) / S GtAr . Figure 1 shows the dependence Psh( R ) obtained for the POLY1 layer of 0.8µm CMOS NOR4 gate. ij
0,8
0,00025
Defect radius probability density function pdf(R) Total probability of faults short Product of probability of faults short and defect radius probability density function
0,7
0,0002
0,6
Psh(R)
0,5
Pdf(R)
0,00015
Pdf(R) Psh(R)
0,4 0,0001
Psh(RSTART - RSTOP)
0,3 0,2
0,00005 0,1 0
0 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 1,1 1,2 1,3 1,4 1,5 1,6 1,7 1,8 1,9 2 2,1 2,2 2,3 2,4 2,5 2,6 2,7 2,8 2,9 3 3,1 3,2 3,3 3,4 3,5 3,6 3,7 3,8 3,9 4
RSTART
RSTOP
Defect radius R [um]
Fig.1. Determination of the total probability of faults shorts caused by spot defects. Obviously if we take into account that the defect probability distribution quickly falls off as the size increase the much more likely for short to occur for small defect than for a large one. The product of defect probability density function Pdf ( R ) and probability of short occurrence Psh( R ) allows to determine the most dangerous defect radius for certain layer of layout [1]. The total probability of short fault occurrence PShTotal can be calculated as: PSh ( R START ≤ R ≤ R STOP ) = Total
R STOP
∫D0 × Psh( R ) × Pdf ( R ) dR
R START
where R START ÷ R STOP – region of variation of the defect radius in computer experiment; D0 – density of spot defects [N/cm2]. The Pdf ( R ) and D0 are determined using statistical information from fabrication process or from published literature [1,3] . Traditionally modelling of the probability of fault resulting from shorts is accompanied by determination of the total probability of
short. Analysis of subdivision of probability caused by shorts between nets is not undertaken. Generally PShTotal consists of probabilities of shorts between nodes: PSh
Total
=
( N Net − 1) N Net
∑ ∑ PSh i =1
j= i+ 1
Net i Net j
,
where PSh – value of probability of shorts between i-th and j-th net. So, it should be introduced the concept of matrix of subdivision of probability of fault caused by shorts between nets PSh with the dimensions [ N Net × N Net ] . The element of the matrix PSh is determined as: Net i Net j
PSh
Net i &Net J
( R START ≤ R ≤ R STOP ) =
R STOP
∫D0 × PSh
Net i & Net J
( R ) × Pdf ( R ) dR
R START
Using model of critical area for determination of the total probability of short fault occurrence the probability of short between i-th and j-th net for certain defect radius may be determined geometrically as Psh ( R ) = SCrAr ( R ) / S GtAr , Net i & Net j
Net i & Net j
where SCrAr ( R ) - the value of critical area between i-th and jth net. Figure 2 demonstrates graphically the determination of the elements of the matrix subdivision of probability of fault caused by shorts between nets. Net i & Net j
III. SOFTWARE TOOLS. For organization of automatic solution of the described problem of identification and probability estimation of different fault types program system “FIESTA” (Faults Identification and EStimation of TestAbility” have been already developed. Input data for these software tools are output text files (ASCII) which are generated by Cadence™ Layout Editor and which contain the description of conductive layers of gate layout. Now “FIESTA” is able to solve the following tasks of the described problem automatically: a) processing of output Cadence™ files and forming of the own model of conductive layers of gate layout; b) forming of the model of critical area for shorts with determined matrix of critical area subdivision S CrAr ; c) determination and estimation the probability occurrence of the shorts (at range of variation of the radius defect) for identification of the type of functional fault; d) formation of the vector of subdivision of probability between types of functional faults caused by shorts and the determination dominant fault types and those types of functional faults which can be neglected. Figure 3 demonstrates the possibilities of program “FIESTA” during investigations of the 3µ m CMOS NOR4 gate [2].
0,00016 0,00014
Pdf(R)*Psh_A&B
Pdf(R)*Psh_A&C
Pdf(R)*Psh_A&D
Pdf(R)*Psh_B&C
Pdf(R)*Psh_B&D
Pdf(R)*Psh_C&D
0,00012 0,0001 0,00008
POLY:
0,00006
Net A Net B Net C Net D Net Q
PSh NetB&NetC
0,00004 0,00002 0
0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 1,1 1,2 1,3 1,4 1,5 1,6 1,7 1,8 1,9 2 2,1 2,2 2,3 2,4 2,5 2,6 2,7 2,8 2,9 3 3,1 3,2 3,3 3,4 3,5 3,6 3,7 3,8 3,9 4 4,1 4,2 4,3 4,4 4,5 4,6 4,7 4,8 4,9 5
Defect Radius [um]
Fig.2. Determination of the elements of the matrix subdivision of probability of fault caused by shorts between nets II.3. Estimation of probability of different functional faults. Matrix of subdivision of probability of fault PSh and the matrix of types of functional faults FTF are symmetric matrices but unlike FTF the S CrAr matrix is generally a sparse one. Namely for a given layout some non-diagonal elements will be equal to zero: PSh = PSh = 0, i ≠ j . The sparsity of PSh will determine the number of necessary circuit simulations of transistor level. This number will be equal to the quantity of non-zero elements in the upper triangular matrix. These elements indexes i and j will determine the nets - Neti and Neti - imitation of short in which should be done in schematic diagram (or introduce the changes to netlist of schematic) during modelling with the use of circuit simulator. Calculation of the number of necessary simulations of the circuit at transistor level on the basis of matrix of subdivision of probability of fault caused by shorts between nets allows to determine minimal quantity of necessary circuit simulations. It decreases the total number of possible simulations of a circuit. Carrying out the circuit simulations at transistor level with the imitation of corresponding shorts allows to determine the types of functional faults in a gate and to form the vector Ftype of types of functional faults caused by spot defects. For example: Net i Net j
Critical area: SA&B SB&C SC&D SA&Q
Net j Net i
{
Ftype = " ST 1" ," ST 0" ," SA 1" ," SA 0" ,...," Type of fault" .," Other"
}
The main result is formation of the vector of subdivision of probability between types of functional faults caused by shorts: PSh
type
{
= PST 1 , PST 0 , PSA 1 ,PSA 0 ,...,Ptype of
fault
,..., POther
}
Quantitative estimation of the Ptype of fault values in PSh vector will allow to determine dominant fault types in the m-th gate and those types of functional faults which can be neglected. type
a) Complete layout of NOR4 gate designed in 3µ m CMOS technology
b) POLY 1 layer layout with double shorts critical area for Rdanger=2.1µ m
Fig.3. Model of layer with critical area creating by “FIESTA” The program system was developed using C programming language and works under Solaris operation system for SUN station. GUI was developed using Tcl/Tk 8.2.
IV. PRACTICAL RESULTS. The proposed approach for solving the problem of identification and probability estimation of different fault types caused by spot defects was used for analysis of 0.8µm CMOS standard gates: NOR_4, NO42, NAND_4, AND_2/NOR_3, and AND_2,2/NOR_3. Let us consider the results carrying out of computer experiment. The conditions of experiment were the following: interval of defect radius range - [0 µm - 5 µm]; value of defect radius step - 0.1 µm; density of spot defects D0 =1 on gate area; layer of investigation – Metal 1 layer. After data processing we have obtained the results described below. The diagram presented in Figure 4 clearly demonstrates the subdivision of probability of shorts caused by spot defect between nets for NOR_4 standard gate.
0,0012
Net[1]=A 0,001
Net[2]=B 0,0009
Net[3]=C
0,0008
Net[4]=D
0,0007
Net[5]=Q
0,0008
0,0006
0,0006
0,0004
Net[6]=VDD 0,0005 Net[7]=VSS
0,0004
0,0002
0,0003 0
0,0001
Net[7]=VSS
Net[5]=Q
Net[6]=VDD
Net[3]=C
Net[4]=D
Net[2]=B
Net[1]=A
0
Ne t Ne [7]= V t[ Ne 6]=V SS t[5 DD ] Ne =Q t[4 ]= Ne D t[3 ]= Ne C t[2 ]= Ne B t[1 ]= A
Not detec A*(n ted ot(B +C+ D)) not( (A* C)+ D) A*(n ot(C +D)) not( B+C +D) not( C|D B*(n ) ot(A +C+ D)) not( (B* C)+ D) not( (B* D)+ C) B*(n not( ot(C (A* +D)) B)+ (A* not( C)+ A+C (A* D)+ +D) (B* C)+ (B* SA0 D)+ for (C* Q D)) not( (A* B)+ (C* D*(n D)) ot((A *B)+ D)) not( (A* B)+ D*(n D) ot((A *B)+ C)) not( (A* B)+ C) SA1 for Q
0,0002
Fig.4 Diagram of subdivision of probability of shorts between nets on Metal 1 layer of NOR_4 standard gate. Figure 5 demonstrates the subdivision of probability between types of functional faults caused by shorts for NOR_4:
Fig.7. Diagram for AND_2/NOR_3 standard gate. 0,0014 0,0012
0,0012 0,001 0,0008
0,001
0,0006
0,0008
0,0004 0,0002
0,0006
0 d C) D) D) D) rQ rQ )] )] )] B* B* B* C* tecte D)] 1 fo 0 fo t(B t(C t(A A* C* A* A* t de ST ST not( *no *no *no not( not( not( not( No ))* C)) D)) D)) *C B C* (D* (B* ( )+( D)+ D)+ C)+ D * * * * A A A B )+( )+( )+( )+( *B *B *C *B ((C ((A ((A ((A not[ not[ not[ not[
0,0004
0,0002
Fig.8 Diagram for NAND_4 standard gate Q ST1 fo r
not(B +C+D ) not((C *B)+ A+D ) not((D *B)+ C+A ) B*(n ot(A+ C+D )) not(A +C+D ) not((C *D)+ A+B) C*(n ot(A+ B+D)) not(A +B+D ) D*(n ot(A+ B+C)) not(A +B+C )
Q ST0 fo r
not((A *B)+ C+D ) not((A *C)+ B+D) not((A *D)+ C+B) A*(n ot(C+ B+D))
0
Fig.5 Diagram of subdivision of probability between types of functional faults caused by nets shorted. Figures 6, 7 and 8 demonstrate the subdivision of probability between types of the functional faults caused by nets shorted: Figure 6 for AND_2,2/NOR_2 standard gate; Figure 7 for AND_2/NOR_3 standard gate; Figure 8 for NAND_4 standard gate. Figure 9 shows the diagram (created by GUI of “FIESTA”) of the subdivision of probability between types of functional faults for NO42 (this gate is almost the same as NOR_4 standard gate but more complex design for higher capacity output load). Fig.9.Diagram of the subdivision of probability between types of functional faults for NO42 created by GUI of “FIESTA”.
0,0012
0,001
0,0008
0,0006
0,0004
0,0002
Fig.6. Diagram for AND_2,2/NOR_2 standard gate
SA0 for Q
SA1 for Q
not((C*D)+(A*B*D)+(A*B*C))
D*(not(A*B))
not((A*B)+(B*C*D)+(A*C*D))
not(A*B)
not(A+B+C)+(D*(not((A*B)+C)))
C*(not(A*B))
not(A+B+D)+(C*(not((A*B)+D)))
A*(not(C*D))
not(B+(C*D))
A*(not(B))
not((A*D)*(B+C))
not(C*D)
not((A*C)*(B+D))
not(A+(C*D))
B*(not(A))
B*(not(C*D))
not((B*D)*(A+C))
Not detected
not((B*C)*(A+D))
0
V. CONCLUSIONS The results obtained in this work show that there are significant differences between probabilities of various types of faults, and they depend strongly on physical design of a logic gate. This information may be used for the development of the approach of estimation of usefulness test vector components for detecting faults resulting from shorts in VLSI. VI. ACKNOWLEDGMENTS This work was financially supported by the grant for international cooperation provided by the Polish State Committee for Scientific Research (KBN Nr134/E-365/S/99) and by the INCO-Copernicus project VILAB (INCO 977133) funded by the European Union. REFERENCES 1. W.A.Pleskacz, W.Kuzmicz. Estimation of the IC layout sensitivity to spot defects. Electron Technology, 1999, Vol.32, No.1/2,pp.182-190. 2. Dennis V.Heinbuch. CMOS3 Cell Library. Addition-Wesley Publishing Company, 1988.,p.721 3. Phil Nigh, Wojciech Maly. Layout-driven test generation. ICCAD, 1989, pp154-157.
