Euler Path

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Outline: Optimized approach Graph-theoretical algorithm Heuristics Conclusion References

Euler Path for Optimal Layout

Developed by Gregory, 2004 Modified by Li Chen, 2013

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Two Versions of C • (A + B)1

Optimized approach (Euler Path)

(Observe the input order)

• The Euler path technique has been used in what is called the “standard cell technique”, which results in a dense layout for CMOS gates and one polysilicon strip that can serve as the input to both NMOS and PMOS devices. • Our main aim is to have a single strip of diffusion in both NMOS and PMOS devices. This depends on the “ordering” of the inputs. How do we determine the best order? ©Gregory Holder

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Consistent Euler Path1

Graph the theoretical approach

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• To reduce the size of an array and an uninterrupted diffusion strip we need to find this “Euler path” talked about previously. This is defined as the path through all nodes or vertices (source and drain signals) such that g ( transistor g gate inputs) p ) is only y visited exactly y each edge( once. (vertices maybe visited more than once). • Euler paths are not unique. • Euler paths must be consistent (same ordering in both PUN (pull up network) and PDN (pull down network). • Can Run in linear time3.

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A j B

2. 3.

Enumerate all possible decompositions to find the minimum number of Euler paths that cover the graph. Chain by means of diffusion area according to the order of edges in Euler path. path If more than 2 edges are necessary to cover the graph model, then provide a separation area between each pair of chains.

C

VDD

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PDN

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GND

A B C

A B C 5

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Heuristic Algorithm (of course life not being so easy) Theorem:

• Therefore for the previous consistent Euler path for the logic structure we achieve the optimal layout below.

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X X = C • (A + B)

The General Algorithm 1.

PUN

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C

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The following example and any circuit will have a single Euler path if the number of inputs to every AND/OR element is odd. Inaddition, Th There exist i t a graph h model d l such that the sequence of edges on an Euler path corresponding to the vertical order of the inputs on a planar representation of the logic diagram.

The Heuristic Algorithm

1) To every gate with an even number of inputs add a “pseudo” input. 2) The “pseudo” input does not contribute to separation area. But this input is added so that there is a minimal combination between “pseudo” and real inputs. 3) Construct the graph model according to the vertical order of inputs on logic diagram. 4) Chain together the gates by means of diffusion areas as indicated by the sequence of edges on the Euler path. A “pseudo" input gives a separation between diffusions. 5) Delete “Pesudo” edges in parallel and contacting “pseudo” edges in series with other edges for final circuit.

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Example

Heuristic Works We apply our Heuristic approach to the previous example and we obtain the following sequence (p1,2,3,1,4,5,p2) where we remove the “pseudo” pseudo inputs to get the same layout previously shown in slide 11. (Note we choose the combination with the minimum interlaced with real inputs) hence circuit (b).

We consider the following logic Circuit (a and b), the derived Euler Path (c) and the corresponding Layout. For our Euler path the PUNand the PDN -----.

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Analysis

Analysis (continued)

1. It must be noted that the heuristic algorithm may not always give the optimal layout but if the resulting sequence. However, if no separation areas are obtained then this is the optimal solution.

Here in (b) we see the final Euler Path interpretation the corresponding circuit diagram (c) and the a final layout.

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2. The heuristic gives excellent results for circuits which do not have a Euler path. This is Illustrated in the four-bit carry look-ahead adder3 circuit shown in this slide.

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Conclusion

References

• This Presentation has given a brief incite into optimizing the layout of complex CMOS gates. Using the Euler path approach and a heuristic algorithm. The results show that by use of this approach h we can optimize considerably d bl on area in our layout. Further work can be done to simulate the “real” gain of this method in terms of power and performance of a particular design.

1. Digital integrated circuits 2nd edition 2. Uehara, T. and Vancleemput, W. M “optimal layout of CMOS Functional Arrays”. 3. Robert Sedgewick “Algorithms Algorithms in C third edition”. 4. Forbes, B. E. “Silicon-on Sapphire Technology Produces High-Speed Single- Chip Processor, “Hewlett-Packard Journal, April 1977,pp 2-8.

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