Proceedings of the 2nd European Microwave Integrated Circuits Conference
60 GHz SiGe HBT Downconversion Mixer Viswanathan Subramanian1, Van-Hoang Do2, Wilhelm Keusgen3, Georg Boeck1 1
Microwave Engineering Lab, Berlin University of Technology, 1
[email protected]
2
TES Electronic Solutions GmbH, Berlin 2
[email protected]
3
Heinrich-Hertz-Institut, Berlin 3
[email protected]
Abstract - This work presents an active downconverter targeted for integration in 60 GHz high speed data communication RF front-ends. The designed downconverter has been realized in 0.25 µm SiGe BiCMOS technology with ft around 200 GHz. The downconverter consists of a single balanced mixer with an onchip balun for differential to single ended conversion. High linearity and bandwidth are the main design goals rather than high gain. A clear-cut investigation of the applied bottom up design approach will be presented with emphasis on modeling the critical on-chip signal path interconnects, matching and filtering components. The design and applied methodologies will be justified by comparing the measured and simulated performances. At 60 GHz an input 1-dB power compression of - 5 dBm, 2.5 dB conversion gain and a gain variation around 2 dB from 50 to 70 GHz, are measured. Current consumption of the mixer core is 4.7 mA from a 3.3 V supply and the active chip area is 0.48 mm2.
I. INTRODUCTION The requirements of future broadband multimedia applications exceed the capacity of the currently used standards like 802.11a and 802.11b/g. Due to special attenuation properties of 60 GHz signals and availability of a large bandwidth, the frequency band 57 GHz to 64 GHz is becoming a favourable region of choice for short range high data rate implementation [1]. This along with the continuous advancements of SiGe BiCMOS technology resulted in increased realization of millimetre wave (MMW) transceiver circuits [2] and [3]. The chosen SiGe BiCMOS technology with 0.25 µm emitter strip width feature HBTs with ft and fmax values as high as 200 GHz. The novel design of the collector enables high ft for the HBTs [4]. Other important technology features include five metal layers and MIM capacitors. The 3 µm thick top metal is used for forming on-chip microstrip transmission lines with metal 1 as ground plane. More details on the SiGe:C process technology can be found in [5]. Many active mixers are realized in SiGe and SiGe BiCMOS in the frequency ranges up to 40 GHz [6]. For RF frequencies 60 GHz and above they are comparatively less in number. In [7] a 60 GHz active downconversion mixer based on a single balanced Gilbert cell has been realized. The mixer has 9 dB conversion gain and an input 1 dB compression point (IP1dB) of – 7 dBm. The mixer output is loaded with a resonant circuit, which makes the mixer very narrowband and sensitive against process tolerances concerning the IF center frequency.
978-2-87487-002-6 © 2007 EuMA
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In [8] a 60 GHz SiGe receiver has been demonstrated with an active mixer based on double balanced Gilbert cell with resistive loads. The mixer has a conversion gain of 10.5 dB and -10 dBm IP1dB. Recently several SiGe active mixers working around 77 GHz are reported [9]-[12]. In our work a broadband, highly linear active downconversion mixer is presented with 2.5 dB conversion gain, - 5 dBm IP1dB and more than 20 GHz bandwidth. The applied design strategy is reviewed and important design steps like EM-modeling of critical paths, extraction of the parasitic elements from the layout and including them in the circuit design are discussed. All in all the entire design work led to a highly reliable design environment able for accurate prediction of the circuit performance at 60 GHz and beyond [13]. II. CIRCUIT DESIGN AND MODELING OF ON-CHIP PASSIVE ELEMENTS This section is divided into two parts. The first part deals with the circuit design while in the second part the modeling of critical passive components is described. A. Circuit Design Fig. 1 shows the simplified schematic of the designed downconverter with mixer core and on-chip active push pull balun. The trans-conductance part Q1 of the single balanced mixer is a resistively degenerated common emitter transistor. The emitter resistance leads to a negative feedback and reduces the gain but increases the linearity. The final value of this resistance is chosen through a proper trade-off between linearity improvements on the one hand and worsening gain and noise figure on the other hand [14]. The LO switching transistors Q2 and Q3 are loaded with a serial combination of resistance and inductance. The gain drop vs. frequency due to a resistive load [14] is compensated by the inverse response of the inductance. This idea is used instead of tuned loads [7] to avoid a shift of the IF frequency band due to parasitic effects at the IF-output. Although we have designed a fully differential circuit, one of the differential LO ports is grounded in this first design because of simplicity reasons concerning the experimental verification. Due to this single ended LO operations, the symmetry conditions are violated and the corresponding LO transistor in the switching pair works in common base configuration which
October 2007, Munich Germany
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Fig. 1 Simplified schematic of the downconverter with dominating parasitic elements
degrades the mixer performance and particularly the isolation values. Of course in the complete transceiver IC the fully balanced mixer will be implemented. An on-chip active push pull balun formed by a serially connected emitter follower with a common emitter transistor with degeneration is used as an output buffer. In the developed downconverter the balun just provides the differential to single ended conversion without any additional gain. The degeneration resistance in the common emitter stage of the balun has a strong influence on its linearity and gain. This is also carefully taken into consideration during the downconverter design for achieving the required linearity. The resistance R17 between the two transistors in the balun is used to facilitate the IF output matching to 50 Ω [15]. Current mirror circuits with ß helpers (not shown in Fig. 1) are used to bias the current sources of the mixer and output balun whose bias point setting is quite crucial. High ohmic resistors are used to completely decouple the biasing circuit from the high frequency part. The non critical biasing of LO transistors is performed through simple voltage dividers. B. Modeling of on-chip passive elements As shown in Fig. 1 the RF-signal is fed to the base of the common emitter stage through a series of matching elements. This path from the probe pad to the input RF transistor is quite significant for the circuit performance particularly at our frequency band of interest around 60 GHz. To characterize such critical paths we follow a bottom up approach in which the layout of the circuit is developed from first simulated schematic. Special care is taken in the layout design to model all interconnects as microstrip transmission lines by providing ground metals of sufficient width. These mircrostrip line models are used as a part of matching or filtering in the circuit design. T1, T2, T3 and T5 shown in Fig. 1 are such microstrip lines modeled for different metal layer interconnects. Further,
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critical on-chip passive structures like the tapered short circuited stub T4 introduced for broad band RF-matching and LO quarter wavelength open stub T6 at IF output for improving LO-IF isolation are 2.5 D modeled using the method of moments based EM solver ADS-Momentum [16]. These 2.5 D models are then co-simulated with the other models in the circuit design environment. Capacitors Cp are parasitic capacitors of the MIM capacitor metal plates to ground. Cpad is the parasitic capacitance of the pads. As will be shown in the results this design approach led to a very good agreement between simulations and measurements already at the first realized circuit. III. MEASUREMENT SETUP Fig. 2 shows a simplified block diagram of the mm-wave measurement environment used for the characterization of the downconverter. The chip photo of the DUT is included. RFRef, IFRef and LORef are measurement reference planes for RF, IF and LO. As shown in the photo the supply and reference voltages are connected by three separate pads for probing through a conventional 7-pin DC probe. To the left, right and bottom are RF, IF and LO signal pads in ground-signalground (GSG) configuration. The distinct short metal line on the left (T4) of the chip is the tapered short circuited transmission line formed by the top metal for RF-matching. The z-shaped structure at the bottom right is the implemented open-circuited transmission line T6. The two on-chip spiral inductors L1 and L2 at the collectors of the mixer cell are seen on the top of the chip below the DC pads. Agilent 83650 signal generators (10 MHz to 50 GHz) along with frequency quadruplers are used for generation of both LO and RF signals around 60 GHz. With this source environment signal power up to +5 dBm at 50 Ω can be generated until 75 GHz.
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Fig. 2 Simplified block diagram of the measurement environment with die photo. Die size is 1 x 0.7 mm2
Conversion Gain [dB]
IV. RESULTS In this section simulated and measured results against various parameters are presented. The complete characterization is carried out at a same bias point with mixer core current consumption of 4.7 mA from 3.3 V. The current consumption of the balun and the biasing circuits is 5 mA in summary. The conversion gain starts to saturate with an LOpower of about -3 dBm and LO-power is set to this value for all measurements. Fig. 3 shows the measured and simulated conversion gain as a function of RF-power. The 60 GHz RFsignal is swept from -25 dBm to -5 dBm while the LO-signal is kept at -3 dBm and 55 GHz.
The output IF-power is measured at 5 GHz. Simulated and measured linear conversion gains of 2.5 dB and 3.8 dB can be taken from Fig. 3. The curves show also the measured and simulated input 1 dB compression points at - 5 dBm and - 6.5 dBm. In summary this is a very satisfactory agreement for the first design cycle at 60 GHz. Possible reasons for the marginal differences may be the inaccurate description of the emitter circuitry of the RF transistor, the imperfect grounding of the common base switching transistor and slightly higher losses of the on-chip transmission lines compared to the simulations. Fig. 4 shows the broad band RF performance of the downconverter. The RF-frequency is swept from 50 GHz to 70 GHz with LO-frequency being swept in parallel from 45 GHz to 65 GHz thereby the IFfrequency is fixed at 5 GHz. RF- and LO-power levels are fixed at -31 dBm and -3 dBm. A 2 dB RF-bandwidth of 20 GHz is measured around the centre frequency of 60 GHz. This is due to the designed broadband RF-matching with tapered transmission lines. The optimum performance is slightly shifted towards lower frequencies due to minor over estimation of the parasitic capacitors at the input. But this is within acceptable limits due to the broadband performance of the mixer. 6
Conversion Gain [dB]
The Agilent spectrum analyzer HP8565E (9 kHz to 50 GHz) is used for measuring IF output power. For minimizing the losses between the 60 GHz sources and the probe heads mainly waveguides are employed for signal transmission and only very short coaxial cables are inserted between the waveguide transitions and the probe heads (Fig. 2). The test equipments are calibrated over the complete measurement frequency range. The frequency dependent attenuation of cables, connectors and measurement probes is eliminated by calibration. Due to this careful calibration procedure we expect a measurement uncertainty concerning the conversion gain of about ±0.5 dB. However, the measurements are repeated across about 5 different chips and results are found to be within a tolerance band of about ±1 dB which indicates a reliable measurement environment on the one hand and a pretty low process tolerance on the other hand.
Measurement Simulation
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Fig. 4 Conversion gain vs. RF-frequency; PLO= -3 dBm; fRF and f LO varied for fIF=5 GHz
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Table I summarizes the measured port to port isolation and input matching values. Simulated noise figure value at 60 GHz RF and 55 GHz LO signals is 16 dB.
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Fig. 3 Conversion gain vs. RF Power; fRF=60 GHz; fLO=55 GHz; PLO= -3 dBm
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[5]
TABLE I RESULTS OF PORT TO PORT ISOLATION AND MATCHING Parameter LO to IF Isolation RF to IF Isolation LO to RF Isolation RF to LO Isolation RF return loss (60 GHz)
Simulated Value > 25 dB > 30 dB > 27dB > 20 dB >10 dB
[6]
Measured Value > 20 dB > 25 dB >24 dB > 16 dB > 7 dB
[7]
[8]
LO to IF isolation and RF to IF isolation values better than 20 dB are achieved through the introduced open circuited stub at the IF-output. The rather low value of RF to LO isolation is due to single ended LO and is expected in this design. In the fully differential design a RF to LO isolation of better than 30 dB is targeted. Though the single ended LO design also influences LO to RF isolation, higher values are obtained compared to RF-LO due to the collector-base reverse isolation of the RF-transistor Q1. V. SUMMARY AND CONCLUSION In this work a MMW SiGe BiCMOS single balanced active downconverter is designed, simulated and measured. Active chip area and current consumption (including the output buffer for characterization reasons) are 0.48 mm2 and 9.7 mA from a 3.3 V supply. The measured performance is 2.5 dB gain with IP1dB of -5 dBm and more than 20 GHz RFbandwidth around 60 GHz. The needed LO-power is -3 dBm. Referring to chip area, power consumption, linearity and bandwidth the achieved mixer performance can be compared with the best results reported so far in the 60 GHz range. ACKNOWLEDGEMENT The authors would like to thank Dr. Dietmar Warning from TES Electronic Solutions GmbH in Berlin for his valuable discussions and for supporting this work. Gratefully, acknowledgement is given also to Daniel Gruner from Microwave Engineering Lab of TU Berlin for his measurement and paper review support. This project is funded by Investitionsbank Berlin IBB under contract No. 10022937 in using means of EFRE. REFERENCES [1]
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