Evaluation of solder joint reliability in flip-chip ... - Springer Link

Journal of ELECTRONIC MATERIALS, Vol. 34, No. 12, 2005

Regular Issue Paper

Evaluation of Solder Joint Reliability in Flip-Chip Packages during Accelerated Testing JONG-WOONG KIM,1 DAE-GON KIM,1 WON SIK HONG,2,3 and SEUNG-BOO JUNG1,4 1.—Department of Advanced Materials Engineering, Sungkyunkwan University, Gyeonggi-do 440-746, Korea. 2.—Reliability and Failure Analysis Center, Korea Electronics Technology Institute, Gyeonggi-do 451-865, Korea. 3.—Department of Materials Engineering, Hankuk Aviation University, Gyeonggi-do 412-791, Korea. 4.—E-mail: [email protected]

The microstructural investigation and thermomechanical reliability evaluation of the Sn-3.0Ag-0.5Cu solder bumped flip-chip package were carried out during the thermal shock test of the package. In the initial reaction, the reaction product between the solder and Cu mini bump of chip side was Cu6Sn5 intermetallic compound (IMC) layer, while the two phases which were (Cu,Ni)6Sn5 and (Ni,Cu)3Sn4 were formed between the solder and electroless Ni-P layer of the package side. The cracks occurred at the corner solder joints after the thermal shocks of 400 cycles. The primary failure mechanism of the solder joints in this type of package was confirmed to be thermally-activated solder fatigue failure. The premature brittle interfacial failure sometimes occurred in the package side, but nearly all of the failed packages showed the occurrence of the typical fatigue cracks. The finite-element analyses were conducted to interpret the failure mechanisms of the packages, and revealed that the cracks were induced by the accumulation of the plastic work and viscoplastic shear strains. Key words: Flip chip, reliability, finite-element analysis, fatigue, Sn-3.0Ag-0.5Cu

INTRODUCTION High-density and high-speed electronic packaging technology is progressing rapidly, and has become indispensable for realizing high performance personal electronic products.1–5 Recently, in the field of highdensity and high-speed packaging, flip-chip interconnection technology was developed. The flip-chip interconnection is the connection of an integrated circuit (IC) chip to a carrier or substrate with the active face of the chip facing toward the substrate. The flipchip technology is generally considered the ultimate first level connection, because the highest density can be achieved and the path length is shortest, so that optimal electrical characteristics are achieved.1 Thermally-activated solder fatigue and a premature brittle interfacial fracture at the intermetallic compound (IMC) layers are the major wear-out failure modes in the flip-chip packages, caused mainly (Received March 14, 2005; accepted July 28, 2005) 1550

by mismatch in thermal expansion coefficients between the silicon die and substrate.6 The fatigue failures occur as a result of the damage in the solders produced by the cyclic inelastic strains.7–9 On the other hand, the brittle nature of the IMC layers between the solder and under bump metallization is the driving force for the premature brittle interfacial fractures. Previous studies on the flip-chip packages with Sn-Pb solder bumps have shown that the creep strain plays a predominant role on the fatigue life of the flip-chip packages, while the formation of the continuous IMC layers, e.g., (Au,Ni)Sn4, Ni3Sn4, and Cu6Sn5, is the main cause for deterioration of the solder joint reliability.6,10,11 Lead-bearing solders have long been used as interconnection materials due to the advantages of the mechanical properties, low melting points, and excellent wetting properties.12,13 However, the effort to develop and promote Pb-free soldering has intensively occurred because of environmental and health concerns. Among various Pb-free solders,

Evaluation of Solder Joint Reliability in Flip-Chip Packages during Accelerated Testing

Sn-Ag-Cu alloys are regarded as the most promising candidate for replacement of Sn-Pb solders. They have superior mechanical properties of strength, elongation, creep, and fatigue resistance than Sn-Pb solders.14–16 For this reason, various associations related with electronics manufacturing in the world, such as the Japan Electronic Industry Development Association (JEIDA) and the National Electronics Manufacturing Initiative (NEMI), recommend the Sn-Ag-Cu solders for the replacement of Sn-Pb solders. However, in order to fulfill the reliability requirements, the knowledge of the failure mechanisms of the solder joints is crucial. The studies on the failure mechanisms of the conventional Sn-Pb solders were well conducted, while there is very limited research concerning the failure mechanisms of the candidate Sn-Ag-Cu solders. Therefore, research on the failure mechanisms of the joints between different solder and under bump metallization combinations should be conducted, since differences are expected in the types of the failure mechanisms and IMCs. We focused on the evaluation of the failure mechanisms of the Sn-3.0Ag-0.5Cu solder bumped flip-chip packages. Scanning electron microscopy (SEM) and electron probe micro analyzer (EPMA) were employed to investigate the microstructure and phase analysis of the solder joints. The thermal shock test was chosen for the reliability evaluation of the solder joints, because this test can compress the testing time by 5, thus reducing the qualification time and cost. The cross-sectional study was then conducted to investigate the failure behavior of the solder bumps. Finally, the computational simulation employing a finite-element modeling (FEM) was conducted to interpret the failure mechanism. EXPERIMENTAL AND ANALYSIS PROCEDURES

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Fig. 1. Loading condition for the thermal shock test of the flip-chip package.

solder bumped chip was bonded to bismaleimide triazine (BT) substrate using a flip-chip bonder (FINEPLACER-96LAMBDA, Finetech, Germany). The reliability of the flip-chip bonded packages was tested by means of thermal shock in the range 233 K to 398 K (15 min cycle time, air to air, 6 min dwelling time). The loading condition of the thermal shock test is schematically described in Fig. 1. After the thermal shock test, the specimens were mounted in epoxy, and then the cross-sectional studies were carried out by grounding with SiC papers followed by subsequent polishing with 1 µm and 0.3 µm alumina powders. The cross section was conducted through the diagonal line of the package. Nital etching solution was employed for the purpose of metallographic observation. The microstructural observation was conducted with SEM, and the resulting IMCs were measured by EPMA.

Experimental Procedures

Finite-Element Analysis

The solder composition used in this study was a Pb-free Sn-3.0Ag-0.5Cu (in mass %). Silicon wafers of 4 in. diameter were sputtered with Ti of 0.2-µm thickness and Cu of 0.8-µm thickness. The Ti and Cu layers are an adhesion layer and interconnection pad layer, respectively. The metallized wafers had area array pad arrangements at 500-µm pitch with rectangular pad opening of 130 µm in width. The bumping for the flip-chip devices was performed using an electrolytic Cu with thickness of 10 µm. The lateral overlap of the Cu under bump metallization on the chip passivation layer, SiO2, was about 5 µm. Solder paste was applied by stencil printing method and subsequent reflow employing an infrared (IR) four zone reflow machine (RF-430-N2, Japan Pulse Laboratory Ltd. Co.) with a maximum temperature of 523 K for 60 sec. After reflow, the average solder bump height and diameter were about 145 µm and 190 µm, respectively. The wafers were cleaned to remove flux residues. Then the

Finite-element simulations were performed to determine the plastic work and shear strain distributions within the flip-chip package when it is stressed by the temperature cycles from the environment. The finite-element code used in this study was ANSYS, release 8.0. Schematics of the three-dimensional (3-D) finite-element model are shown in Fig. 2. Due to the symmetry of the package geometries, only one-eighth of the flip-chip assembly was modeled using a 3-D-1/8th finite-element analysis symmetry model along the two symmetry planes. The solder joints along the diagonal cross-sectional symmetric plane are shown in Fig. 2b. As shown in Fig. 2b and c, the full details of the actual packages, such as sputtered Ti/Cu layer and thin SiO2 passivation layer, were implemented in the model to catch the highest degree of accuracy. The 3-D solid element (SOLID185) was employed to model the components containing the solder, Si chip, and SiO2 layer. The element thickness was 12.5 µm for solder bump.

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Kim, Kim, Hong, and Jung

Fig. 2. Finite-element models for the thermal shock test of the flip-chip package: (a) 1/8th octant model, (b) cross-sectional view of a single solder bump, and (c) magnified view near the chip side interface.

Because the thermal shock test temperature was in excess of a homologous temperature of 0.5, linear and nonlinear, time dependent, and independent material properties were incorporated in the finiteelement model.17 In the present work, the slightly modified Garofalo–Arrhenius steady-state creep constitutive equation was used to realize the exact deformation behavior of the solder material. Equation 1 shows the modified creep constitutive equation which is the same form of input for implicit creep model (TBOPT 8) of the ANSYS.18 dε = C1 sinh(C2 σ ) dt

[

]

c3

 C  exp − 4   T

(1)

where C1, C2, C3, and C4 are given constants in Table I for Sn-3.0Ag-0.5Cu solder alloy.19 This option was combined with Kinematics hardening model using von Mises plasticity to represent the viscoplastic properties of the solder material. The creep modeling was applied to the dwell time of the thermal shocks in both high (398 K) and low (233 K) temperatures. The other materials, except for the solder, were treated like linear elastic materials, and the elastic material properties are given in Table II. Table I. Input Parameters for Creep Analysis Solder Composition Sn-3.0Ag-0.5Cu

C1 (1/sec)

C2 (1/MPa)

C3

C4 (K)

6.385E6

0.08638

5.84

159.97

Table II. Linear Elastic Material Properties for Flip-Chip Assemblies

Material Sn-3.0Ag-0.5Cu BT substrate Si chip SiO2 Polyimide Cu Ti Ni

Young’s Modulus (MPa)

Poisson’s Ratio

CTE (ppm/°C)

52,340 26,000 131,000 74,000 14,500 76,000 116,000 207,000

0.4 0.39 0.3 0.17 0.16 0.35 0.34 0.31

22 15 2.8 0.4 13 17 8.9 13.1

RESULTS AND DISCUSSION Figure 3 shows the diagonal cross-sectional SEM micrographs of the as flip-chip bonded joints. Figure 3a indicates the first four solder bumps from the edge of the package. The other figures are the magnified views of the corner solder bump, which is indicated by a hollow square in Fig. 3a. As can be seen in Fig. 3b, the solder bump was well shaped and firmly bonded to both the chip side under bump metallization (Cu mini bump) and package side plating layer (electroless Ni-P). At the chip side interface between the solder and Cu mini bump, a layer of Cu6Sn5 IMC was formed in a thickness of about 1.5 µm. However, the EPMA element analyses revealed that the reaction products between the solder and electroless Ni-P layer at the package side interface were composed of two different phases, (Ni,Cu)3Sn4 and (Cu,Ni)6Sn5. The composition of these phases was (Ni0.73Cu0.27)3Sn4 and (Cu0.63Ni0.37)6Sn5, respectively. These results were nearly the same as those of our previous study, which involved treating Sn-3.5Ag-0.75Cu solder composition.17 The formation of the IMC layer at the interface between solder and substrate is very important to the reliability of the whole package, because an IMC layer which is too thick is sensitive to stress and sometimes provides sites of initiation and paths of propagation for cracks. The growth of IMC layer could degrade the solder ball joint reliability, and it is thus indispensable to study the IMC layer formation and growth when high temperature storage, temperature cycling, or extended bake-out creates thick IMC layers.20 Some Ag3Sn particles were distributed within the solder, and these particles were considered to be one of the influential factors controlling the mechanical properties and reliability of the solder.21,22 Figure 4a and b show the corner solder bump of the specimen after 100 thermal shocks, while Fig. 4c and d are those of the specimen after 200 thermal shocks. In these micrographs, any crack or a sign of crack initiation could not be found. However, the thickness of the IMC layer increased rather than the as-bonded joints, and the microstructural coarsening within the solder could be seen. These phenomena are important to the thermally-activated


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Fig. 3. Diagonal cross-sectional SEM images of the as-flip-chip bonded joint: (a) overall shape of the joint, (b) magnified view of a corner solder bump, (c) microstructure of the chip side interface, and (d) microstructure of the package side interface.

solder fatigue or a premature brittle interfacial fracture; therefore, further investigations should be conducted. The cross-sectional micrographs of the specimen after 400 thermal shocks are shown in Fig. 5. In these micrographs, the cracks finally occurred at the corner solder bump joint in both the chip side and package side interfacial product regions. From this result, it could be deduced that the fatigue crack initiation time is near 400 thermal shocks in this type of package and solder composition. In the case of the chip side, the crack initiated at the tip of the Cu6Sn5 IMC layer, and then grew through the solder region near the IMC layer and broken IMC particles. This could be conjectured to be a typical thermally-activated fatigue failure of the solder joints. However, further investigation should be conducted with more thermal shocks, because the length of the crack is not sufficiently long to determine the failure modes. At the same time, the crack that is located in the package side initiated at the tip of the IMC layer, and propagated through the IMC layer. This is due to the fracture at the interface with the under

bump metallization, where brittle IMCs are formed and grown during the thermal shock test. This failure mode is often the reason for early failure of the package, and thus is called the premature brittle interfacial fracture, which is different from the thermally-activated fatigue crack of Fig. 5b. More thermal shock tests were conducted to determine what type of crack occurrence was the primary failure mode of this package. Figure 6 shows the cross-sectional views of the corner solder bumps after 600 thermal shocks and 1000 thermal shocks. In these micrographs, the crack in the chip side propagated consistently, while the crack in the package side could no longer be seen. The cracks in the chip side initiated at the tip of the IMC regions. However, the crack did not propagate along the solder joint/Cu mini bump interface, but propagated inside the solder material with a saw tooth-type route and an overall direction parallel with the Cu bump. This is the well known fatigue crack formation in the bulk of the solder, along a rather straight horizontal path, following the direction of the highest strain. From these results, it

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Fig. 4. Diagonal cross-sectional SEM images of the flip-chip bonded joints after thermal shocks: (a) and (b) micrographs after the thermal shocks of 100 cycles and (c) and (d) micrographs after the thermal shocks of 200 cycles.

Fig. 5. Diagonal cross-sectional SEM images of the flip-chip bonded joints after thermal shocks of 400 cycles: (a) microstructure of the corner solder bump, (b) magnified view of the chip side interface, and (c) magnified view of the package side.

could be concluded that the major failure mechanism of this type of package and solder composition in the thermal shock test is the thermally-activated fatigue crack formation. This means that the various life prediction methods of the soldered packages, such as the energy-based or strain-based models, could be applied to this type of package. Additionally, it should be noted that this type of failure mode could also occur in this thermal shock test, which

has a completely different test mechanism from the typical temperature cycling test. After the thermal shocks of 1000 cycles, the crack finally broke out the solder bump interconnection. For analysis of the failure mechanisms of the thermal shock tested specimens, the finite-element analyses were conducted. Figure 7a shows the finite-element model of the diagonal cross-sectional plane, while Fig. 7b and c indicate the displacement


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Fig. 6. Micrographs showing the crack growth: (a) corner solder bump after 600 thermal shocks and (b) corner solder bump after 1000 thermal shocks.

variations in vertical direction and the plastic work increase for 3 thermal shocks, respectively. As shown in the figures, the displacement variations and the plastic work increase in the first dwelling time at high temperature varied significantly, but soon stabilized. This is due to the fact that the test initiation time of the thermal shock was set to the lowest temperature of 233 K, thus, the stress free temperature was specified to the lowest temperature. Therefore, a very large amount of deformation occurred at the initial temperature ramping period, which was followed by a relatively high amount of creep deformation at the high dwelling period. These figures prove that the displacement of the solder bump and the plastic work increase in 5th solder bump were most considerable. This means that the 5th solder bump has the highest potential for the first crack initiation and growth through that region. Figure 8 shows the finite-element model of the corner solder bump and the plastic work variations with different locations. Figure 8b indicates that the elements A and B have relatively high values of the plastic work increase, rather than those of elements C and D. This means that the possibility of the crack

Fig. 7. Diagonal cross-sectional view of the finite-element model and the displacement and plastic work histories with the thermal shock test: (a) cross-sectional view of the finite-element model, (b) displacement history of the solder bumps in vertical direction, and (c) plastic work history of the different solder bumps.

initiation is highest at the region near the element A, and the crack can propagate from element A to element B, because the thermomechanical failure of the solder joints is mainly caused by the accumulation of the plastic work. Therefore, these results could explain the experimental results, which had the crack initiation and growth through the region near IMC layers of the corner solder bump. It should be also noted that the plastic work values were

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Fig. 8. Plastic work histories with different locations in the corner solder bump: (a) finite element of the single solder bump and (b) plastic work history in different locations.

higher than those found in previous research.2,23 Because the solder joint life should be mainly affected by the value of plastic work increase per cycle, the high value of the plastic work increase is important. This is mainly caused by some different specifications of the package, such as absence of underfill application, applied SiO2 passivation layer (coefficient of thermal expansion of Si is 7 times higher than SiO2 passivation layer), and a relatively large pitch of the arrayed solder bumps. Figure 9 shows the distributions of the plastic work and viscoplastic shear strain after the simulation of 3 thermal shocks. As shown in Fig. 9b and d, the plastic work and strain were considerably accumulated at the chip side interface of the corner solder bump, and then expanded through the solder region in parallel to the Cu mini bump. This means that the location near the interface between the Cu mini bump and solder has the highest potential for crack initiation and propagation. These distributions are well matched to the experimental results. SUMMARY AND CONCLUSIONS The present study detailed the microstructural evolution of the Sn-3.0Ag-0.5Cu solder and IMC layer, and the thermomechanical reliability evaluation of the flip-chip packages during the thermal shock test. In the initial reaction, the reaction product between the solder and Cu mini bump of chip side was Cu6Sn5 IMC layer, while the two phases, (Cu,Ni)6Sn5 and (Ni,Cu)3Sn4, were formed between the solder and electroless Ni-P layer of the package side. The EPMA element analyses revealed that the compositions of these two compounds were (Ni0.73Cu0.27)3Sn4 and (Cu0.63Ni0.37)6Sn5. The thickness of the IMC layers increased and the microstructural coarsening occurred within the solder during the thermal shocks. The cracks occurred at the corner solder joints after thermal shocks of 400 cycles. The primary failure mechanism of the

solder joints in this type of package was confirmed to be the thermally-activated solder fatigue failure. The premature brittle interfacial failure sometimes occurred in the package side, but nearly all of the failed packages showed the fatigue cracks. The finite-element analyses revealed that the cracks were induced by the accumulation of the plastic work and viscoplastic shear strains. From these results, it should be noted that the thermally-activated solder fatigue failure is still the main failure mode of the flip-chip packages, and the plastic work and viscoplastic strain accumulations are primarily affecting the crack initiation and growth time (the life of the solder joint) in this thermal shock test condition. That is, the failure mode and mechanism of this case is very similar to the cases of typical temperature cycling test of the solder ball applied packages. At the same time, the plastic work and solder bump displacement histories with different solder bumps and locations indicated that the chip side inter-facial regions of the corner solder bump had the highest potentials for the crack initiation and propagation. This is well matched with the experimental results. ACKNOWLEDGEMENTS This work was supported by the Regional Technology Innovation Program of the Ministry of Commerce, Industry and Energy (MOCIE) (Grant No. RTI04-03-04). REFERENCES 1. J.H. Lau, Flip Chip Technologies, ed. J.H. Lau (New York: McGraw-Hill, 1995), pp. 123–179. 2. John H.L. Pang, and D.Y.R. Chong, IEEE Trans. Adv. Packaging 24, 499 (2001). 3. D.G. Kim, J.W. Kim, J.G. Lee, H. Mori, David J. Quesnel, and S.B. Jung, J. Alloys. Compounds, 395, 80 (2005). 4. D.G. Yang, G.Q. Zhang, Leo J. Ernst, Cornelis van’t Hof, J.F.J.M. Caers, H.J.L. Bressers, and J.H.J. Janssen, IEEE Trans. Components Packaging Technol. 26, 388 (2003). 5. T.Y. Lee, K.N. Tu, and D.R. Frear, J. Appl. Phys. 90, 4502 (2001).


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Fig. 9. Plastic work and viscoplastic shear strain distributions after 3 thermal shocks: (a) and (b) contours of the plastic work, and (c) and (d) contours of the viscoplastic shear strain. 6. P. Ratchev, B. Vandevelde, and I.D. Wolf, IEEE Trans. Dev. Mater. Reliability 4, 5 (2004). 7. X. Zhang, E.H. Wong, C. Lee, T.C. Chai, Y. Ma, P.S. Teo, D. Pinjala, and S. Sampath, Microelectron. Reliability 44, 611 (2004). 8. L. Zhang, V. Arora, L. Nguyen, and N. Kelkar, Microelectron. Reliability 44, 533 (2004). 9. X.Q. Shi, H.L.J. Pang, and X.R. Zhang, Microelectron. Reliability 44, 841 (2004). 10. John H.L. Pang, D.Y.R. Chong, and T.H. Low, IEEE Trans. Components Packaging Technol. 24, 706 (2001). 11. W.W. Lee, L.T. Nguyen, and G.S. Selvaduray, Microelectron. Reliability 40, 231 (2000). 12. J.W. Nah, K.W. Paik, J.O. Suh, and K.N. Tu, J. Appl. Phys. 94, 7560 (2003). 13. K.N. Tu, T.Y. Lee, J.W. Jang, L. Li, D.R. Frear, K. Zeng, and J.K. Kivilahti, J. Appl. Phys. 89, 4843 (2001). 14. K. Zeng, V. Vuorinen, and J.K. Kivilahti, IEEE Trans. Electron. Packaging 25, 162 (2002).

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