Experimental demonstration of high-speed free ... - OSA Publishing

Experimental demonstration of high-speed freespace reconfigurable card-to-card optical interconnects Ke Wang,1,2,*Ampalavanapillai Nirmalathas,1,2 Christina Lim,2Efstratios Skafidas,1,2 and Kamal Alameh3 1 National ICT Australia – Victoria Research Laboratory (NICTA-VRL), Melbourne, Victoria 3010, Australia Department of Electrical and Electronic Engineering, The University of Melbourne, Melbourne, Victoria 3010, Australia 3 Centre of Excellence for MicroPhotonic Systems, Electron Science Research Institute, Edith Cowan University, Joondalup, West Australia 6027, Australia * [email protected] 2

Abstract: In this paper, we experimentally demonstrate a high-speed freespace reconfigurable card-to-card optical interconnect architecture employing MEMS-based steering mirror arrays for simple and efficient link selection. A printed-circuit-board (PCB) based interconnect module is developed and 3 × 10 Gb/s reconfigurable card-to-card optical interconnect with a bit-error-rate (BER) of ~10−6 for up to 30 cm is realized using a 250 μm pitch-size micro-lens array. In addition, due to the usage of MEMS steering-mirrors, larger lenses can be employed at the receiver side for collecting stronger optical signal power to increase the achievable interconnect range or to improve the BER performance. Experimental results show that with 1-mm diameter lenses the interconnect distance can exceed 80 cm. ©2013 Optical Society of America OCIS codes: (200.4650) Optical interconnects; (060.4510) Optical communications; (200.2605) Free-space optical communication.

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Received 1 Oct 2012; revised 2 Nov 2012; accepted 8 Nov 2012; published 30 Jan 2013

11 February 2013 / Vol. 21, No. 3 / OPTICS EXPRESS 2850

11. L. A. Buckman-Windover, J. N. Simon, S. A. Rosenau, K. S. Giboney, G. M. Flower, L. W. Mirkarimi, A. Grot, B. Law, C.-K. Lin, A. Tandon, R. W. Gruhlke, H. Xia, G. Rankin, M. R. T. Tan, and D. W. Dolfi, “Parallel optical interconnects >100 Gb/s,” J. Lightwave Technol. 22(9), 2055–2063 (2004). 12. D. M. Kuchta, Y. H. Kwark, C. Schuster, C. Baks, C. Haymes, J. Schaub, P. Pepeljugoski, L. Shan, R. John, D. Kucharski, D. Rogers, M. Ritter, J. Jewell, L. A. Graham, K. Schr¨odinger, A. Schild, and H.-M. Rein, “120Gb/s VCSEL-based parallel-optical interconnect and custom 120- Gb/s testing station,” J. Lightwave Technol. 22(9), 2200–2212 (2004). 13. F. E. Doany, B. G. Lee, A. V. Rylyakov, D. M. Kuchta, C. Baks, C. Jahnes, F. Libsch, and C. L. Schow, “Terabit/sec VCSEL-based parallel optical module based on holey CMOS transceiver IC” in Proceedingsof Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference(OFC/NFOEC,Los Angeles, California, 2012), PDP5D.9. 14. R. Dangel, C. Berger, R. Beyeler, L. Dellmann, M. Gmur, R. Hamelin, F. Horst, T. Lamprecht, T. Morf, S. Oggioni, M. Spreafico, and B. J. Offrein, “Polymer-waveguide-based board-level optical interconnect technology for datacom applications,” IEEE Trans. Adv. Packag. 31(4), 759–767 (2008). 15. C. L. Schow, F. E. Doany, C. W. Baks, Y. H. Kwark, D. M. Kuchta, and J. A. Kash, “A single-chip CMOSbased parallel optical transceiver capable of 240-Gb/s bidirectional data rates,” J. Lightwave Technol. 27(7), 915–929 (2009). 16. C. J. Henderson, D. G. Leyva, and T. D. Wilkinson, “Free space adaptive optical interconnect at 1.25 Gb/s with beam steering using a ferroelectric liquid-crystal SLM,” J. Lightwave Technol. 24(5), 1989–1997 (2006). 17. N. McArdle, M. Naruse, H. Toyoda, Y. Kobayashi, and M. Ishikawa, “Reconfigurable optical interconnections for parallel computing,” Proc. IEEE 88(6), 829–837 (2000). 18. M. Aljada, K. E. Alameh, Y. T. Lee, and I. S. Chung, “High-speed (2.5 Gbps) reconfigurable inter-chip optical interconnects using opto-VLSI processors,” Opt. Express 14(15), 6823–6836 (2006). 19. L. C. Andrews and R. L. Phillips, inLaser Beam Propagation through Random Media, SPIE Optical Engineering Press, Bellingham, Washington, 1998. 20. T. Mizuochi, “Recent progress in forward error correction and its interplay with transmission impairments,” IEEE J. Sel. Top. Quantum Electron. 12(4), 544–554 (2006).

1. Introduction Over the past several decades, the CMOS silicon transistor technology has evolved through several generations and nowadays the transistors have been scaled down to the deep submicrometer range [1–3]. Therefore, higher speed and more powerful electronic devices can be achieved through dense integration of millions of transistors. In addition, various multi-core architectures have been widely employed in high-performance computing and in data-centers. Consequently, ultra high-speed interconnects between chips, cards, as well as racks are highly demanded. Sustained improvement in multi-channel on-chip and on-board interconnection has been demonstrated using the Si photonics and nano-photonics technologies [4–6]. However, the improvement of interconnection capacity between cards and racks has not kept to the pace. Conventionally, copper based cables are used for data transmission between cards and racks. However, the electrical technologies are not suitable for future high-throughput interconnects due to the fundamental limitations, including the electric power consumption, heat dissipation, transmission latency and electromagnetic interference [7, 8]. Some commercial products have already been developed and deployed for rack-to-rack interconnects, where electrical cables are replaced by low-loss, high-speed optical cables that significantly increase the maximum link length [9]. With the rapid advance in optical integration, the optical interconnect technology is now entering “inside the box” [10]. To solve the card-to-card interconnect bandwidth “bottleneck” problem, the usage of parallel short optical links has been proposed and intensely studied. Most reported approaches use multi-mode fiber (MMF) ribbons [11–13] and polymer waveguides [14, 15] based technologies. Polymer waveguides are considered as promising candidates because they can be integrated with the electrical printed-circuit-boards (PCBs) and easily packaged. A fullyintegrated bi-directional parallel optical interconnect structure reported by Schow et al. [15] employed parallel waveguides fabricated using the standard PCB technology and demonstrated an aggregate data rate of 240 Gb/s. On the other hand, the MMF ribbons based interconnect architecture has attracted considerable attention because of its attractive features, such as high bit rate, low-cost due to the mature fabrication process, and easy coupling due to the large optical fiber core-size. The structure reported by Doany et al. [13] demonstrated a

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data transmission throughput of up to 1 Tb/s using 48 parallel channels in conjunction with a single CMOS compatible holey chip. However, such point-to-point interconnection schemes are inherently non-reconfigurable, and their flexibility in dynamically interconnecting electronic cards is highly limited. Several reconfigurable free-space-based high-speed card-to-card optical interconnect structures have been proposed and investigated, where the modulated optical signal of each interconnect channel can be switched along different directions via a link selection block before it is detected by a final-destination electrical card [16–18]. Therefore, significant flexibility can be added to the communications between various cards. Henderson et al. [16] reported a 1.25 Gb/s free space card-to-card optical interconnect architecture employing a liquid crystal on silicon (LCoS) processor in conjunction with a polarization beam splitter as the link selection block, while the architecture reported by McArdleet al [17]. used a prism together with a lens and a spatial light modulator (SLM) as the link selection block. The use of an Opto-very-large-scale integration (Opto-VLSI) processor as the link selection block has also been reported by Aljada et al. [18], where a 3x3 2.5 Gb/s reconfigurable optical interconnect architecture was experimentally demonstrated. While such structures demonstrated the concept of reconfigurable card-to-card optical interconnects, the diffractionbased link selection block introduces high-loss and results in low link selection efficiency. To achieve a large tuning angle, high-order diffraction signals need to be utilized. In addition, these diffraction-based schemes have a comparatively complicated tuning mechanism (how the incident signals are tuned to the destination receivers), limited tuning range as well as low bit rates that are insufficient for future-generation card-to-card interconnects. In this paper, we experimentally demonstrate the concept of a novel free-space reconfigurable card-to-card optical interconnect architecture that offers flexibility and highspeed, simultaneously. The proposed architecture employs VCSEL and photodiode (PD) arrays in conjunction with MEMS-based steering mirror arrays that serve as the link selection block. Compared with the previously reported link selection methods [16–18], MEMS-based mirrors provide higher selection efficiency, simpler tuning mechanism through beam reflection, wider tuning range and possibly easy integration. A proof-of-concept 3 × 10 Gb/s PCB-based reconfigurable free-space optical interconnect demonstrator is developed, demonstrating both the port-to-port and board-to-board reconfigurability with a BER of ~10−6 over up to 30 cm card-to-card distances and a receiver sensitivity as low as −11.5 dBm at a BER of 10−9. In addition, due to the usage of MEMS steering-mirrors, it is possible to employ lenses with a diameter larger than the pitch-size of the PD array at the receiver side for collecting stronger optical signal power to increase the achievable interconnect range or to improve the BER performance. Experimental results show that by using 1 mm diameter lenses the interconnect distance can be extended to more than 80 cm without the need to increase the transmitter power. This paper is organized as follows: in Section 2, the proposed reconfigurable free-space card-to-card optical interconnect architecture is presented; in Section 3, the experimental setup for demonstrating the proposed reconfigurable optical interconnect is described and the experimental results are discussed; in Section 4, the usage of larger lenses at the receiver side to extend the achievable interconnection range is experimentally investigated; in Section 5, the reconfigurability of proposed optical interconnect scheme in the card-level is experimentally verified; and finally conclusions are given in Section 6. 2. Architecture of proposed free-space reconfigurable card-to-card optical interconnect The architecture of proposed high-speed reconfigurable free-space card-to-card optical interconnect is shown in Fig. 1, where a dedicated optical interconnect module is integrated onto each electrical card (typically a PCB) and these optical interconnect modules on different cards are identical. Each optical interconnect module mainly consists of a VCSEL array, a PD array, two micro-lens arrays, and two MEMS-based steering mirror arrays serving #176993 - $15.00 USD

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as the link selection block. At the transmitter side, the electrical signal from the attached card first modulates the VCSEL optical beam, and then the modulated optical beam is collimated by the associated micro-lens. To minimize the VCSEL beam divergence, the distance between the VCSEL and micro-lens is made equal to the focal length of the micro-lens. Subsequently, the optical signal is steered towards the corresponding receiver with a steering MEMS mirror element. At the receiver side, the modulated optical signal is appropriately steered with another MEMS mirror element and focused onto the corresponding PD element. With analog steering mirrors being used, the transmitted optical beam can dynamically be steered along arbitrary directions (limited by the tuning range), realising adaptive optical interconnection with receivers at arbitrary locations within a communication range. In addition, inside a typical rack, the electrical cards are placed in parallel and the free space link may be blocked if the optical interconnect modules are placed at the same position with respect to the adjacent cards. Since the proposed optical interconnect module is small in size, this possible blockage problem can be avoided by installing the module at different positions of the cards, as shown in Fig. 1, and this requires non-identical designs for the slots on different electronic cards.

Fig. 1. Architecture of the proposed reconfigurable free-space card-to-card optical interconnect.

Conventionally, short-range optical interconnects employ VCSEL and PIN-PD arrays operating at the same wavelength [11–18] instead of using the wavelength-divisionmultiplexing (WMD) technology. The same approach is adopted here as well for the realization of reconfigurable free-space optical interconnects because it (i) is cost-effective; (ii) eliminates the need for complex circuitry for the precise control of the wavelength of the VCSEL elements; and (iii) increases the aggregate bit rate. In the proposed reconfigurable optical interconnect scheme, the optical beams radiated from the VCSEL elements propagate directly in free-space until they are detected by the final destination cards. According to the Gaussian beam theory, the beam diameter expands as the propagation distance increases [19], thus inducing, severe inter-channel crosstalk and leading to a degraded BER performance. This crosstalk issue can be suppressed by using a receiver MEMS steering mirror array with a large spacing between the elements. This is because (i) the intensity of a Gaussian beam drops exponentially with the radial distance from the centre of the beam and (ii) the crosstalk signal induced by a Gaussian beam illuminating a MEMS element does not strike the other MEMS elements at their optimum incidence angles that maximize the optical coupling efficiency and signal detection by their associated PD elements.

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3. Experiments and discussions 3.1 Experimental setup To demonstrate the feasibility of our proposed reconfigurable free-space card-to-card optical interconnect architecture, proof-of-concept experiments were carried out and the setup is shown in Fig. 2. In the experiments, an optical interconnect module was designed, fabricated and integrated onto a small-size 4-layer PCB, as displayed in the inset of Fig. 2. Specifically, a 1 × 4 VCSEL array (multimode), the corresponding VCSEL driver circuits (4 packaged drivers), a 1 × 4 PD array and 4 trans-impedance amplifier (TIA) chips were integrated onto a single PCB. A micro-lens array was then aligned and mounted on top of the VCSEL array and the PD array to collimate the VCSEL beams and focus received optical beams onto the active windows of the PD elements. Each of the two micro-lens arrays was attached to an XYZ 3-axis translational stage, and the distance between the VCSEL/PD plane and the lens was changed manually to minimize the collimated signal divergence. It should be noted that in real applications, the micro-lens arrays can be placed on spacers of height equals to the focal length of the micro-lenses to minimize the beam divergence after collimation and for signal focusing. Furthermore, separate MEMS steering mirror chips with < 5 ms point-topoint large-angle switching time and > 96% reflectivity were used to switch the optical beams to various cards, as illustrated in Fig. 1. The MEMS mirror chips were also attached to XYZ translational stages and dynamically steered by changing the voltage applied to their actuators.

Fig. 2. Experimental setup (not to scale) for demonstrating the concept of free-space reconfigurable card-to-card optical interconnects.

In the experiment, an 850 nm VCSEL array with a 250 µm pitch was used and wirebonded onto the PCB. The average divergence angle of the VCSEL beams was ~16° and varied slightly among the 4 elements of the array (~15°, ~16°, ~16°, and ~18°, respectively). The maximum bit rate of the VCSEL driver chips was 11.3 Gb/s. The VCSEL and PD microlens arrays (fused silica) had a pitch of 250 µm, a clear aperture of ~236 µm, a refractive index of ~1.45, and a focal length of ~656.5 µm. Micro-lens arrays with a comparatively high fill-factor (large clear aperture) were chosen to minimize the diffraction effect at the transmitter side and to collect enough optical power at the receiver side. The PD array also had a pitch of 250 µm. Each PD element had an active aperture diameter of 60 µm and a responsivity of ~0.6 A/W at 850 nm, and was wire-bonded onto a TIA chip. The 3-dB bandwidth of the TIA was ~12.6 GHz and its differential trans-impedance was ~5 kΩ. In addition, the size of the MEMS mirror was larger than the pitch of VCSEL and PD arrays, so only three out of the four available channels were used and the channels 1 and 4 signals just stoke the MEMS mirrors on the edge, as shown by the inset of Fig. 2 (the third VCSEL and PD elements were not used). During the measurements, the bit rate for each channel was set to 10 Gb/s and on-offkeying (OOK) modulation was used. The output power from each VCSEL element was set to 2 mW using a DC bias current of ~6.5 mA. At the receiver side, to suppress the crosstalk, 2.5

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mm spacing between the MEMS steering mirrors was chosen. Furthermore, the vertical distances between the micro-lens array and the MEMS steering mirror array were ~1.5 cm at the transmitter side and ~10 cm at the receiver side, respectively. Since the MEMS mirrors at the receiver side had a larger channel spacing and the PD elements had a small active window, the incident angle onto the micro-lenses was highly limited. Therefore, the larger distance used at the receiver side was necessary to ensure that each optical beam strikes their corresponding micro-lens element at a small incident angle and that the focused light spots could be detected. This vertical distance at the receiver side was not negligible since the horizontal distance between the transmitter and receiver PCBs was only ~20-30 cm. While this comparatively large vertical distance used led to slight reduction in detected signal power due to the longer propagation distance between the interconnected VCSEL and PD elements, it, however, reduced the crosstalk induced at other PD elements significantly. In addition, it should be noted that the beam expansion with propagation distance mainly came from the imperfect beam collimation. 3.2 Experimental results and discussions

Fig. 3. BER of three working channels versus the horizontal distance between transmitter and receiver PCBs. Bit rate = 10 Gb/s, MEMS mirror spacing at the receiver side = 2.5 mm and VCSEL transmission power = 2 mW.

To demonstrate the concept of reconfigurable free-space optical interconnect architecture, two scenarios were considered. In the first set of measurements, VCSEL element n (n = 1, 2, or 4) was interconnected to PD element n. The measured BER versus the horizontal distance between the transmitter and receiver PCBs is shown in Fig. 3. Here, it should be noted that the horizontal distance is smaller than the total optical transmission distance from the VCSEL element to the corresponding PD element due to the considerably large vertical distance between the micro-lens arrays and the MEMS steering mirrors. During all measurements, the three working channels were always turned on simultaneously in order to investigate the worst-case scenario. It is clear from Fig. 3 that by increasing the horizontal distance between transmitter and receiver PCBs, the BER also increases, for all three channels. This is because the diameter of the Gaussian beam increases with the propagation distance, resulting in a smaller collected signal power (the transmission power from VCSELs was fixed) and more inter-channel crosstalk power being coupled into the various PD elements, thus degrading the BER performance. In addition, it can be seen from Fig. 3 that the performance of channel 4 is much better than those of the other two channels. This is because channel 4, which is relatively far from other channels, is less susceptible to crosstalk induced by channels 1 and 2. Furthermore, for all the three channels, even when the horizontal distance is 30 cm, which is typical for data center card-to-card interconnects, a BER of ~10−6 can still be achieved. Therefore, better error-free (BER < 10−9 or even < 10−12) high-speed optical wireless interconnections can be attainedby additionally using forward-error-correction (FEC) codes

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[20] or increase the output optical power of the VCSELs (the VCSELs used in the experiments had a maximum transmission power of ~5 mW).

Fig. 4. BER versus received power for the three optical interconnects. The horizontal distance between the transmitter and receiver modules is (a) 20 cm and (b) 30 cm. Bit rate = 10 Gb/s.

Figure 4 shows the measured BER versus the received optical power for different horizontal distances between the transmitter and receiver PCBs. The received power was varied by changing the output power levels of the VCSEL elements. It is clear that for horizontal distances of 20 cm (Fig. 4(a)) and 30 cm (Fig. 4(b)) between the transmitter and receiver PCBs, channel 4 receiver displays a better sensitivity (less than −11.92 dBm at BER