Extra-Inversion Charge Enhancing Substrate Current ...

ECS Transactions, 13 (14) 93-100 (2008) 10.1149/1.2998534 © The Electrochemical Society

Extra-Inversion Charge Enhancing Substrate Current during Increased Substrate Bias in 90 nm Process M.C. Wang*, a, Z.Y. Hsieha, C. H. Tua, S. Y. Chena, H. W. Chena, A. E. Chuanga, H.S. Huanga, Sam Choub a

Institute of Mechatronic Engineering, National Taipei University of Technology, Taipei, Taiwan b Special Technology Division, United Microelectronics Corporation, Hsinchu, Taiwan * Dept. of Electronic Engineering, Ming-Hsin University of Science and Technology; No. 1 Hsin-Hsing Road, Hsin-Fong, Hsin-Chu, 304, Taiwan; e-mail: [email protected]

Substrate current ISUB depends on source/drain voltage VDS, and can be used as an index of the hot carrier effect (HCE). Normally, substrate bias influences device performance and other parameters, such as the threshold voltage. On the other hand, the substrate biasing circuit benefits turn-on current and restrains the turn-off current. However, few studies assessed the change to substrate current when forcing different drain voltages and substrate biases. Furthermore, a unique phenomenon was observed: separate and consentient trends existed while gate voltage VGS increased from 0 to 1.8 V and a turning point locates around at the peak value of ISUB. Here, this study identifies the increase in surface inversion charge Qi from substrate effect in weak inversion layer more than in strong one; is correlated with this interesting symptom. In this study, gate length LG of a measured n-channel metal-oxidesemiconductor field effect transistor (nMOSFET) device is 0.18 µm with a 90 nm process. Introduction Recently, some studies, the complementary metal-oxide-semiconductor (CMOS) circuits employs biasing circuit of forward substrate bias, are highly concerned because forward substrate bias improves the electrical parameters of p-channel or n-channel MOS device, such as applied threshold voltage, which actively controlled and enhanced (1) transistor switching performance (2) and suppressed source/drain leakage (3). Both forward and reverse biases benefit standby power reduction. Additionally, forward substrate bias improved the hot-carrier reliability of CMOS device (4, 5). However, few studies identified the minor drain current variation while forward bias forcing. Measuring substrate current versus gate voltage, current-voltage characteristic curve (I-V curve), exposed a significant difference between drain voltage and body bias. This study determines why substrate current under drain voltage sweeping was larger than that under body bias sweeping. Otherwise, after the peak value of substrate current appearing, the curves of substrate current under each of substrate bias exhibit identical behavior. Thus, this study measured some characteristic curves and proposed the device model to identify separate and consentient trends when forcing substrate bias forward.

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ECS Transactions, 13 (14) 93-100 (2008)

Fundamental of Substrate Current The hot-carrier effect (HCE) device reliability test was employed to determine device performance under 10 years of operation. With a thick gate oxide (> 70 Å), a MOS device can tolerate high supply voltage (VCC). The drain site of an n-channel metal-oxidesemiconductor field effect transistor (nMOSFET) generates a large electrical field. Due to this high field, electrons are attracted from the source terminal and damage the drain junction. Then, these energized electrons can generate electron-hole pairs (EHPs) inside this junction location (Fig. 1) (6). The positive hole stream flowing to the substrate is called substrate current. This substrate current (ISUB) is an index that assesses the degree of impact ionization in this device under testing (DUT). Poly-gate

Spacer

Gate oxide Inversion layer

Drain

Traps Injection

n-

n+

LDD

EHP Generation Isub

Depletion region

∆L p-sub.

Figure 1. Simplified impact ionization in an nMOSFET (6). Hot Carrier Effect Impact ionization occurred near the drain region due to the high electrical field in the depletion region (Fig. 1). Here, the depletion region typically formed by n+-doped impurity for an nMOS device with a p-type substrate. Maximum lateral electrical field (Emax) on the y-axes (7) was presented as 2

Emax

⎛ V − VD ,sat ⎞ 2 ⎟⎟ + Esat = E y ( y = ∆L ) = − ⎜⎜ DS l ⎠ ⎝

[1]

where l: channel length on drawing, ∆L: depletion length between the peak of inversion layer and the end of lightly-doped-drain (LDD) n- layer, VD,sat: saturation voltage of VDS at pinch-off point, and Esat: saturated electrical field. To reduce the hot carrier effect, the lightly-doped-drain (LDD) implantation has been widely applied to smoothen peak electrical fields (8). Figure 1 presents the simple LDD structure profile. In principle, the doped concentration of LDD is less than that of the source/drain (S/D) implants by, at least, 1 order. In the submicron or nano-scale process, the shallow-junction and silicide processes (11) have been adopted to prevent a short channel effect (SCE) (9) and high channel or source/drain (S/D) resistance (10). However,



the size of the LDD profile decreased as did its resistance compared that with the inversion channel resistance. Hence, this LDD implant was recently renamed in 90 nm process technology by the source-drain-extension (SDE) implant. The SDE implant is closed to S/D implant, but is still lower than the S/D implant within one half. Both of LDD and SDE implants are used to reduce the peak electrical filed at the drain site. For advanced ultra large scale integration (ULSI) technology, the device shrunk and operated at a low supply voltage. This trend increases the density of devices in an integrated circuit (IC). Low supply voltage provides low power consumption and relaxes the vertical and lateral electrical fields, which benefits the hot carrier effect. Although the gate length of an nMOS device exceeds 110 nm (4), most device reliability issues are strongly dependent on the effect of the drain avalanche hot carrier (DAHC). The well-known I-V characteristic curve is ISUB vs. VG (Fig. 2). However, when device gate length is at 90-nm node, the channel hot carrier (CHC) (VGS= VDS) plays a very critical role. The lifetime test with CHC stress yields a poor lifetime result (12). 9.E-07

ISUB (A)

6.E-07

3.E-07

IB_@Vd=1.8V

0.E+00 0

0.5

1

1.5 VGS (V) 2

Figure 2. Typically I-V curve of ISUB vs. VG. Relationship between ISUB and (VGS, VDS, VBS) Surface channel electrons were attracted by the lateral electric field, induced by VDS. Near the drain region, the p-n junction is impacted by energized electrons. Some EHPs are generated. With the increase in gate voltage, the depletion length ∆L of surface channel also increases (Fig. 3) (13). The generated electrons usually flow toward to the drain or gate site. At the same time, most holes flow down to the substrate. This is the well-known index, ISUB, in HCE stress. Few of electrons penetrate the gate oxide due to the voltage difference between the gate electrode and drain site.



G (0 V~1.8 V)

VTH = 0.22 V

D (1.8 V)

S (GND)

LG=0.18 µm

en+

n+ h+ ∆L

VG=0 V ~ 1.8 V

p-Sub. B

Figure 3. Schematic illustration of substrate current with voltage setup. As VDS increases, the effective channel length decreases. The reduction amount, ∆L, can be expressed as 2 ⎤ ⎡V − V ⎛ VDS − VD ,sat ⎞ DS D , sat ⎢ ⎟⎟ + 1⎥ ∆L = l ln + ⎜⎜ ⎥ ⎢ lEsat lE sat ⎠ ⎝ ⎦ ⎣

[2]

where the saturation drain voltage VD,sat is represented (4) as

1 VD , sat

=

1

+

Esat L VGS

1 − VTH

[3]

For a long channel device, VD,sat is approximately equal to VGS−VTH. The lateral maximum electric field is derived by Eq. [1]. However, that VTH decreases when VBS increases is due to the body effect. Moreover, the relationship between VTH and VBS is

VTH = VTH 0 + γ

(

2φ f − VBS − 2φ f

)

[4]

where VTH0 is the zero-bias threshold voltage, γ is the body effect coefficient, and φf is surface potential (14). For the measurand condition, VGS increased from 0 to 1.8 V, VDS was fixed at 1.8 V, and the source terminal was grounded. Specially, VBS increased from 0 to 0.28 V. Due to the body effect in [4], VTH, calculated using the transconductance (Gm) method, decreased from 0.220 V to 0.198 V. As VD,sat ≈ VGS-VTH, VD,sat increased in [3] as result of the decrease in VTH. The value of VDS−VD,sat was decreased. Thus, while VD,sat decreased, the number of Emax obtained increased. Figure 4 presents test results.



2.5E-04 ID _VBS=0 ID _VBS=70mV ID _VBS=140mV GM_VBS=0 GM_VBS=70mV GM_VBS=140mV

2.0E-04 IDS↑

2.1E-05

1.5E-04

1.0E-04

GM ( I / V )

IDS (A )

4.2E-05

5.0E-05 VTH ↓ 0.0E+00

0.0E+00 0

0.09

0.18

0.27 VG (V)

0.36

0.45

Figure 4. VGS vs. ID and Gm with VBS=0 V, 0.14 V and 0.28 V in linear region. Measurement Results and Discussion The ISUB-VG Curve with Forward Body Bias Sweeping and Drain Voltage Sweeping Traditionally, the substrate current is measured to monitor the hot carrier effect, especially for different drain voltages. However, in this study, the substrate current curve was measured with different forward body biases. In this section, the ISUB−VG curves with forward body bias and drain voltage sweeping are analyzed to determine their effects. Forward Body Bias Sweeping. For a gate length (LG=0.18 µm) device with forward body bias, threshold voltage is decreased [4]. Additionally, the saturation drain current ID,sat can be expressed as in Eq. [5] (7) and is relative to threshold voltage VTH.

W (VG − VTH ) (1 + λVDS ) L 2m 2

I D ,sat = µ eff Cox

[5]

where λ: channel length modulation factor. Equation [5] indicates that as threshold voltage VT decreases, ID,sat increases. Furthermore, substrate current ISUB (or IB) is linearly correlated with ID,sat and can be expressed as in (15). IB =

⎛−β α I D l d E eff exp⎜ ⎜E β ⎝ eff

⎞ ⎟ ⎟ ⎠

[6]

=> I B ∝ I D Hence, summarizing Eqs. [4], [5] and [6], indicates that when forward body bias was forced, substrate current was enhanced. Comparing Fig. 5 with Fig. 6, although curve profiles of substrate current (Figs. 5 and 6) are similar, the incremental degrees differ. The degree of increase of substrate current in Fig. 5 is not obvious due to the minor deviation in threshold voltage, which is related to forward body bias. A 20-mV threshold voltage deviation is obtained in this study.



8.E-07 7.E-07 ISUB (A)

6.E-07 5.E-07

Lower increment

4.E-07

VBS=0V

3.E-07

VBS=0.14V

2.E-07

VBS=0.28V

1.E-07 0.E+00 0

0.3

0.6 0.9 VGS (V)

1.2

1.5

1.8

Figure 5. ISUB vs. VG at VDS= 1.8 V with VBS=0 V, 0.14 V and 0.28 V. Drain Voltage Sweeping. For the case with drain voltage sweeping, the value of VDS−VD,sat increases as drain voltage increases. Therefore, the lateral electrical filed in Eq. [1] is increased because of the increase in drain voltage. To verify the relationship between substrate current and drain voltage, substrate current can be transferred with another form IB =

⎛−β α I D (VD − VD ,hot )exp⎜ ⎜E β ⎝ eff

⎞ ⎟ ⎟ ⎠

[7]

=> I B ∝ VD Clearly, substrate current is proportion to drain voltage (Fig. 6). Both forward body bias and drain voltage change affect the increase in substrate current; however, the degree of increase differs significantly. This study demonstrates that forward body bias, causing the slight deviation in threshold voltage influences the small change in IB; however, a large deviation in IB is due to drain voltage. Thus, small and large increases in substrate current might be obtained in Fig. 5 and Fig. 6, respectively. 8.E-07 IB_@Vd=1.8V

7.E-07

IB_@Vd=1.7V

I SUB (A)

6.E-07

Larger increment

5.E-07 4.E-07 3.E-07 2.E-07 1.E-07

0.E+00 0

0.5

VGS (V)

1

1.5

2

Figure 6. VGS vs. ID with VDS=1.7 V and 0.18 V.



Separate and Consentient Trends of Substrate Current with Forward Bias Figure 7 shows the ISUB−VG curve under different forward body biases of 0 V, 0.14 V and 0.28 V. From Eq. [3], for a long-channel device, VD,sat is approximately equal to VGS−VTH,. Hence, the value of VD,sat can be set to 0 V when VGS=VTH. Next, threshold voltages VTH1= 0.220 V and VTH2=0.198 V with VBS=0 V and VBS=0.28 V were measured, respectively. In the mean time, the pinch-off point can be defined by VDS=VGS−VTH. Therefore, the pinch-off point in VBS=0 V and VBS=0.28 V is at VGS~0.220 V and VGS~0.198 V. Consequently, the reason is why the ISUB vs. VG curve in VBS=0.28 V gets ahead in VBS=0 V. 8.E-07

4.E-08 Consentient

ISUB (A)

6.E-07

3.E-08 VBS=0V

4.E-07

2.E-08 VBS=0.14V

2.E-07

1.E-08

0.E+00

Deviation of ISUB (A)

Separate

0.E+00 0

0.3

0.6

0.9 VGS (V)

1.2

1.5

1.8

Figure 7. ISUB vs. VGS and deviation of ISUB vs. VGS Additionally, few charges were induced by VBS and were defined as ∆Qi, a deviation of inversion surface charges. The increase in ∆Qi at a small VGS generated a weak inversion channel such that source/drain current IDS and impact ionization rate increased. The amount of EHPs also increased. The deviation of ISUB, ∆IB, increased at this mode. However, while gate voltage increased more, the EHPs were recombined by the electron stream from the source terminal. Therefore, the ∆IB gradually decreased when ISUB_max existed. The relationship between ISUB and the EHP generation rate (G) and recombination rate (R) (16) can be described as

I SUB ∝ −α R + β G

[8]

Conclusions

In this study, the nMOSFET substrate current was measured with a forward substrate bias. This study demonstrates and verifies different distributions of ISUB curves under VGS bias plus drain voltage adjustments or forward body bias tuning. Furthermore, the lateral electrical field at VBS=0 V is smaller than that at VBS=0.28 V. Therefore, the ISUB at VBS=0.28 V was greater than that at VBS=0 V prior to the turning point. Moreover, as VBS increased, VTH decreased, and an extra ∆ID was created due to a deviation in inversion



charges, ∆Qi, induced by VBS. When the device operated at the weak inversion, the generated holes (∆h+) were enhanced by ∆Qi. On the other hand, as VG increased and the device operated under a strong inversion, the minor ∆h+ contributing ISUB was reduced because of the recombination effect. Thus, the ∆IB after ISUB_max decayed gradually. Consequently, ∆ID or ∆Qi clearly contributed to ISUB and ∆IB was observed when VGS was closed to ~ 1/2 VDS. Beyond ~ 1/2 VDS, the ∆IB change increasing VGS was not obvious due to the hole recombination effect. Acknowledgments

The authors thank United Micro-electronics Corporation (UMC) for providing the precious 90-nm node wafers and appreciate the financial support from NSC 96-2221-E159-017 (National Science Council, Taiwan) project. References

1. 2. 3. 4. 5. 6. 7.

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