Extraction of a High-level Structural Representation from Circuit

23.1

Extraction of a High-level Structural Representation from Circuit Descriptions with Applications to D F T / B I S T * Ishwar Parulkar and Melvin A. Breuer Department of Electrical Engineering - Systems University of Southern California Los Angeles, CA 90089-2562. Abstract-- This p a p e r describes C L A R I O N , a circuit reorganization s u b s y s t e m o f the U S e - T e s t system. Most digital circuit designs are described as netlists of h u n d r e d s o f t h o u s a n d s o f gates and flip-flops, and C A D tools a n d engineers often do not have knowledge of the high-level s t r u c t u r e of the design. Starting from only a flat description of a circuit, C L A R I O N c o n s t r u c t s a 2-level h i e r a r c h y of the dataflow struct u r e of the circuit consisting of registers and blocks of c o n n e c t e d c o m b i n a t i o n a l logic. This circuit reorganization capability has applications in C A D areas such as floorplanning, p l a c e m e n t , routing, retiming and logic resynthesis. An application to the highlevel design-for-testability ( D F T ) and built-in self-test ( B I S T ) tools in the USC-Test system is presented. I.

INTRODUCTION

Digital circuits are often described as netlists consisting of hundreds of thousands of gates and flip-flops. Some CAD tools cannot process such large descriptions. Also, some CAD tools require a register-transfer level structural description of the design as an input. CLARION (Combinational Logic Blocks And Register IdentificatiON) is a CAD environment utility tool that extracts a canonical high-level structural representation comprising clusters of connected combinational blocks and registers from a flat gate level description of a circuit. It can be used as a pre-processor to a host of CAD tools as shown in Fig. 1. The USC-Test system provides a framework for applying various D F T and BIST techniques to circuits modelled at the high-level (registers and combinational blocks). One of the considerations in adding D F T or BIST hardware to circuits is the selection of registers as test resources such as test pattern generators, scan registers and test response compactors. To reduce the complexity in making a design testable, it is often advantageous to view a circuit as a combination of registers and combinational blocks instead of flip-flops and gates. The original design might be described in terms of a bit-sliced architecture rather than a word organized pipeline architecture which is a more preferred view for some CAD tools. Also some high-level descriptions present a view which cannot be efficiently used by a test subsystem. Hence whether the input is a hierarchical or a flat description, a canonical hierarchical view suitable for D F T and BIST application *This work was s u p p o r t e d by the A d v a n c e d Research P r o j e c t s Agency a n d m o n i t o r e d by the Federal Bureau of Investigation u n d e r C o n t r a c t No. JFBI90092.

Charles A. Njinda Vertex Semiconductors 1060, Rincon Circle San Jose, CA 95131

( IZ

GATE-LEVEL NETLIST

()

OTHER CAD TOOLS (FLOORPLANNING, PLACEMENT, ETC

I,~GH-LEVEL STRUCTURE

Fig. 1. Finding order from chaos needs to be identified. CLARION generates such a view automatically. In addition, the size and complexity of modern designs makes it difficult for most CAD algorithms to deal with a circuit as one logical unit. Partitioning a design into logical or physical components that can be handled separately often reduces the computational complexity. Most CAD tasks are NP-complete and hierarchical in nature. These algorithms can work on the top level description of a circuit consisting of registers and combinational blocks, dropping down to the gate level details of a block when necessary thus reducing computation time. In physical CAD, partitioning of the circuit is critical to efficient placement and routing. However most existing partitioning algorithms use metrics that typically do not reflect the inherent order that is present in the logical design [1], [2]. It has been shown that making use of the dataflow structure in the logic design can improve the quality of the layouts generated [3], [4]. The CLARION view of a circuit can be used for generating efficient layouts since it uses circuit structure and functionality of the design in addition to connectivity. The remainder of the paper is organised as follows. Section II presents an overview of the partitioning methodology. The concepts and definitions of registers, combinational logic units (CLU) and fanout units (FU) are discussed in Section III. Section IV describes the algorithms involved in the partitioning process. The CLARION output of some circuits with applications to high-level D F T tools is shown in Section V. II.

O V E R V I E W OF THE PARTITIONING M E T H O D O L O G Y

CLARION partitions a circuit into disjoint clusters of combinational logic and registers. The input is a hierarchical or a flat (gates and flip-flops) description of the circuit. If the input description is hierarchical, CLARION first extracts a flat gate level description. A sequential circuit is modelled as a d i g r a p h whose nodes are logic gates and flip-flops, primary input, primary output and fanout

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345

0 o

ONNECTIVITY ANALYSIS

REGISTER IDENTIFICATION

Primary

CLUSTERING COMMUNAL

inputs

o

CLUs

AND

17 0

o Primary outputs

o

points of the circuit, and whose edges are interconnecting lines oriented in the direction of the signal flow. Fig. 2 illustrates the steps involved in the CLARION methodology. The first step in CLARION is to obtain a flattened description of the circuit. A connectivity analysis of the circuit is then carried out using the graph model. The connectivity information about the flip-flops is stored as labels associated with them. Each flip-flop is given an input label (output label) that represents all the flip-flops that feed it (are fed by it) through paths consisting of only combinational logic paths. In the next phase, the register identification phase, the set of all flip-flops in the circuit is partitioned into registers. A r e g i s t e r is a maximal set of flip-flops subject to the following conditions. 1. The flip-flops drive maximally connected combinational logic and are driven by maximally connected combinational logic. 2. All the flip-flops of the register are in loops or none of them are in loops. 3. The flip-flops are homogenous in the sense that they are of the same type (e.g. D, J-K) and have the same functionality (e.g. hold, shift). The register identification phase is followed by clustering and partitioning of combinational logic. A c o m b i n a t i o n a l logic u n i t (CLU) is defined as a set of combinational logic blocks (or gates) which are connected to the same set of registers through only combinational gates. Fanout nodes whose branches feed the same set of registers are absorbed into the CLUs. Fanout nodes whose branches feed distinct sets of registers are excluded from CLUs and grouped into f a n o u t u n i t s (FUs). Fig. 3 shows a gate level circuit and Fig. 6(a) shows the high-level structure extracted by CLARION from the randomized netlist. The high-level view of the circuit after partitioning retains key low-level information and hides gate level information that may not be required in the application of the D F T and BIST methodologies. For example, information about self-loops and global loops is preserved along with some useful fanout points. However details such as gate fanouts and reconvergence are absorbed in the high-level view. REGISTEaS,

lq

° q-f+O

Fig. 2. Overview of CLARION

III.

3

~'r

FUs

This section describes the high-level components into which a given circuit is partitioned. A flattened sequential circuit is represented as a d i g r a p h G = (i, o, V, E), where V = Ve U Vs U VI, Ve is the set of combinational gates, Vs is the set of flip-flops and V! is the set of fanout nodes. Special nodes i and o correspond to primary inputs and primary outputs respectively. The set of edges, E, corresponds to signal flow between the nodes. The nodes fed by a fanout node are referred to as the b r a n c h n o d e s of that fanout node. A c o m b i n a t i o n a l p a t h in this graph is defined as a path from node u to node v 346

0

"

O - PI, PO node

• - Fanout node

O-Combinational node

O-

26

Storage node

Fig. 3. An Acyclic sequential circuit and its graph model such that all the nodes on the path, excluding u and v, are either combinational gates or fanout nodes. Note that the end points of a combinational path can be flip-flops but the other nodes in the path cannot be flip-flops. Fig. 3 shows an acyclic sequential circuit and its graph representation. A storage node v is said to be in a selfl o o p if there exists a combinational path from v to itself. A storage node v is said to be in a g l o b a l l o o p if there exists a path from v to itself which is not a combinational path. In the rest of the paper, the terms storage nodes and flip-flops will be used interchangeably.

A.

Register identification

In many high-level D F T and BIST techniques it is desirable to group as many flip-flops together as possible into a register that can be used as test pattern sources or response collectors for a block of connected combinational gates. To define a m a x i m a l r e g i s t e r we introduce the concept of s p a n and an o v e r l a p relation between spans. In the following definitions v ~ w denotes a path from node v to node w. D e f i n i t i o n 1: (a) The o u t p u t s p a n of a flip-flop v (v E Vs) is the set S~o u t = {w I w E V, v ~ w is a combinational path}. Node v is called the s o u r c e of the span. (b) The i n p u t s p a n of a flip-flop v (v e Vs) is the set 5~.'~ = {w I w E V, w v is a combinational path}. Node v is called the s i n k of the span. In Fig. 3, the output spans of nodes a, b and j are S~ut = { 3, 12, 10, 14, 15, e,g,h }, S~ut = { 4, 8, 11, 13, 15, f, h } and S~ut = { 26 }, respectively. The input spans of nodes e, f and g are S~" = { 12, 3, 5, a, c }, S}'~ = { 13,

7 , 8 , 2 , 4 , 6 , b,d,l,O } andS~n= { 1 4 , 1 0 , 7 , 3 , 5 , 2 , a,c, 1, 0 }, respectively. In the case of a cyclic circuit the concept of a w r a p p e d s p a n is useful. Our partitioning methodology is restricted to synchronous sequential circuits, hence there are no cy-

cles involving only combinational nodes. A span of a storage node v is a wrapped span if one of the elements of the span is v itself. Thus, if v is in a self-loop S~°ut and S~n are wrapped spans. We now define a relation o v e r l a p (o') on the set of input spans (or output spans). D e f i n i t i o n 2: Span Su o" S~ if (a) Su CI St, # ¢, o r (b) if S,, N S~ = ¢, then 3 S~ such that Su N Sw # ¢ and

Pm'imtry Outputs

0 Primer7

inputs

&aSw. For example, in Fig. 3 since S~~ N S~ut = {15, h} ¢ ¢,

S~utaS.~ ~". .However, in the case of input spans S~n and S}', S~'aS~" even though S~" N S~" = ¢. This is because there is another input span S~n such that S~n N S~n ¢ ¢ and S~nqSj, ". In the presence of wrapped spans in the graph model, the set of input spans is partitioned into a set of wrapped input spans and a set of non-wrapped input spans. The relation overlap (o) is then applied to these sets separately. Similarly for the output spans of the circuit• The relation overlap when applied to the set of wrapped input (or output) spans will be referred to as 0"w as opposed to 0" for the non-wrapped case. It can be easily shown that the relation overlap partitions all the output spans of the circuit graph G into • out out out eqmvalence classes S,~a= , S~a z 2 ,..., S~axk such that two. • , 1 distract output spans are in the same equivalence class if and only if they overlap. Similarly the set of input spans is also partitioned into equivalence classes. D e f i n i t i o n 3: (a) A m a x i m a l o u t p u t s p a n S,~'~ is an equivalence class formed by the relation overlap on the set of output spans of the circuit. (b) A m a x i m a l i n p u t s p a n S~a in ~ is an equivalence class formed by the relation overlap on the set of input spans of the circuit• The maximal output spans in Fig. 3 are: ~.qo~,t T T ~

},

= { s:-',

},

1

= { ~.¢o=t

= { s;-',

,

S~,"t } and S~n~, , = { S~"t, S]"'., S~u', S~"~' }. There is only one maximal input span, S~a., = { S~", S~n, Sin,

s o,

s?, sT, sr,

s?, sr,

}.

Fig. 4 shows a synchronous sequential circuit with feedback loops and its graph representation• The various output spans are: S~ ut = { 4, 7, 10, 12, a }, S~ t't = { 1, 4, 5, 7, 8, 9, 10, 11, 12, a,b,c }, S~°~'t = { 2, 5, 7, 8, 9, 10, 11, 12, a,b,e }, S~ ut = { 5, 8, 9, 11, 12, c },

Se°u' = { 3, 6, 9, 11, 12, c } and S} u' = { 6, 9, 11, 12, c }. S~ ut,S~ 'ut and S~°ut are wrapped spans while the others are not. Applying relation ~r~ to the wrapped output spans, we have Sr~t~=, = t-al'q°t't, S~ ut, ~cq°ut}" Applying relation cr to the non-wrapped output spans, we have S°m~=~ = {S~u', Se°ut, S}u'}. Note that even though S co u t N S do u t ~ ¢, they do not belong to the same equivalence class because one of them is a wrapped span while the other is not. The maximal spans represent maximally connected combinational logic bounded by flip-flops on one side and by flip-flops or primary inputs (outputs) on the other side. Corresponding to each maximal output span in the circuit graph we define a register that feeds the maximal span.

12

0

Fig. 4. Cyclic sequential circuit and graph model Similarly corresponding to each maximal input span we define a register that is fed by the maximal span. D e f i n i t i o n 4: (a) The set of sinks of the input spans belonging to a maximal input span equivalence class S~a~, constitutes a m a x i m a l l y r e c e i v i n g r e g i s t e r R~. (b) The set of sources of the output spans belonging to the maximal output span equivalence class S~Uat~ constitutes a m a x i m a l l y d r i v i n g r e g i s t e r R~. The set of storage nodes is thus partitioned into maximally receiving registers R~, R~, ...R,~. The same set of storage nodes is also partitioned into a set of maximally driving registers R~, R~, ..., Ram. Every pair of maximally receiving registers ~s disjoint and every pair of maximally driving registers is disjoint. However, a maximally receiving register will overlap with some maximally driving register. We now define a maximal register in the circuit as follows. D e f i n i t i o n 5: A m a x i m a l r e g i s t e r R is a maximal set of storage nodes such that for some R[ and R], R C R[ and R C R]. Corresponding to the maximal input and output spans of Fig. 3, we have one maximally receiving register R~ = { a, b, c, d, e, f, g, h, i, j, k, l } and four maximally driving registers R~ = { a, b, c, d }, R2d = { e, f }, Rad = { g, h } and R4d = { i, j, k, 1 }. By the definition of a maximal register we have four maximal registers, which in this particular case are the same as the maximally driving registers: R1 = { a , b , c , d } , R 2 = { e , f }, R a = { g,h } and R4 = {

i,j,k,l}. In addition to the basic definition of a maximal register there are some additional conditions which the flipflops have to meet in order to belong to the same register. Some of the D F T / B I S T techniques require the knowledge of which flip-flops are in global loops. A flip-flop is in a global loop if there exists a path from the flip-flop to itself

347 ....~

............ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

.~L

~........~ - - - i ~ -

~

passing through at least one other flip-flop. This property of a flip-flop needs to be translated to the high-level view if the D F T / B I S T techniques are to make use of the knowledge. Hence an additional condition for two flipflops to belong to a register is that both the flip-flops are in global loops or neither is. Moreover if the registers are to be configured as test resources all the flip-flops have to be homogenous in the sense that they should have the same functionality and the same control lines.

B.

R~

R2

R~

R3

R4

(a)

Re

R2

Ri

Combinational Logic Units (CL Us)

R4

R1

After identifying the registers, the combinational logic is partitioned into combinational logic units (CLUs). Each maximal input span gets divided into CLUs depending upon the connectivity of the combinational nodes in the span with the registers fed by the maximal span. R2

D e f i n i t i o n 6: A c o m b i n a t i o n a l logic u n i t is a maximal set of combinational nodes and fanout nodes, such that each node has combinational paths to the same set of registers. For example in Fig. 3, combinational nodes 19, 20, 21, 22, 23 and 24 have combinational paths to nodes of register R4 = { i, j, k, l } only. Fanout nodes 17, 18 and 25 are also included in the CLU because each one feeds register R4. Hence, CLU4 = { 17, 18, 19, 20, 21, 22, 23, 24, 25 } where the subscript refers to R4. The other CLUs in Fig. 3 are CLU2 = { 8 , 12, 13 }, CLUa = { 9, 10, 14, 11, 15 } and CLU2,3,4 = { 1, 2 } Note that fanout nodes 7, 3, 4, 5 and 6 are not included in any CLU since they do not feed the same set of registers as any of their branch nodes. Consider fanout node 3. One of its branch nodes, namely node 12, feeds only register R2 = { e, f }, and the other one, namely node 10, feeds only register R3 = { g, h }, while fanout node 3 itself feeds both R2 and R3.

I::1,3

R2

Ra

(b)

Fig. 5. Uniform and non-uniform FUs Fig. 6(a) and (b) illustrate the reorganized view produced by CLARION from circuit descriptions corresponding to Fig. 3 and Fig. 4, respectively. IV.

C. Fanout absorption and clustering In the high-level view of the circuit, fanouts offer more flexibility in the application of testing schemes. For example fanout at the output of a register, that feeds two disjoint combinational logic blocks gives more flexibility in the scheduling of tests for these blocks. The fanout nodes excluded from the CLUs need to be collapsed to fit into the 2-level reorganized hierarchy of registers and CLUs. Hence we consider the fanout nodes at the output of a register (or a CLU) to be grouped into a single component called a fanout unit (FU). Two types of fanouts are defined at the output of a register (or CLU). D e f i n i t i o n 7: (a) A u n i f o r m F U is the set of fanout nodes fed by a register (or a CLU) such that each of the fanout node feeds the same set of CLUs. (b) A n o n - u n i f o r m F U is the set of fanout nodes fed by a register node (or a CLU node) such that at least one pair of fanout nodes feeds different sets of CLUs.

ALGORITHMS

An algorithm that labels and merges flip-flops iteratively has been developed to form partial registers until a set of maximal registers is obtained. Initially, each flipflop is given a unique label. All primary inputs and primary outputs are given the same label. Then each flip-flop gets an i n p u t l a b e l and an o u t p u t l a b e l based on the connectivity with other flip-flops which are at a sequential depth of one in each direction. Depending on label compatibility, flip-flops are merged into partial registers. A p a r t i a l r e g i s t e r is a subset of a maximal register and it corresponds to an intermediate stage in the formation of the maximal register. D e f i n i t i o n 8: (a) The i n p u t l a b e l of a flip-flop (partial register) i, IL(i), is the union of the labels of all flipflops/partial registers that have a combinational path to i. (b) The o u t p u t l a b e l of a flip-flop (partial register) i, OL(i), is the union of the labels of all flip-flops/partial registers that can be reached from i through a combinational path. Based on the definition of a maximal register and the labelling method we have the following condition for merging of flip-flops or partial registers. C o n d i t i o n 1: Two flip-flops (partial registers) i and j, can be merged into one partial register if IL(i)NIL(j) ~ ¢ a n d OL(i) n OLU) ¢ ¢. To handle synchronous sequential circuits with loops, additional conditions are required. For a register to reflect the self-loop property of its flip-flops in the reorganized view, two flip-flops one of which is a self-loop and the other is not, cannot be merged together. Hence to merge two flip-flops (partial registers), either both have to be in a self-loop or neither should be in a self-loop. Also if both flip-flops (partial registers) are not in self-loops, but one of them feeds the other through a combinational path,

For example in Fig. 5(a) the fanout nodes 1, 2 and 3 feed CLU sets { CLU2, CLU3 }, { CLU2, CLU4 } and { CLU3, CLU4 }/respectively, and hence the FU is a nonuniform FU. In Fig. 5(b), the fanout nodes 1, 2 and 3 feed the same set of CLU nodes { CLU2,CLU3 } and they form a uniform FU. 348

"4

PI

Partitioning of combinational logic into combinational logic units (CLUs) is done after register identification. CLU partitioning is done by a backward labelling algorithm, cluster_CLUs. Individual labels are assigned to every register. All primary outputs are assigned the same label. For every combinational node and fanout node (v E V~ U V!), a set of labels label(v) is constructed such that a label i is present in label(v) if and only if there is a combinational path that starts at v and ends at a register with label 1. Combinational nodes that have exactly the same set of labels are clustered into CLUs, i.e., v and w are in the same CLU if and only if label(v) = label(w). A fanout node having the same set of labels as one of its branch nodes is clustered along with that branch node into a CLU. Most of the tasks performed in the partitioning process are simple graph traversals for which polynomial time algorithms exist [5]. The complexity of the whole procedure is dominated by the register identification phase and CLU clustering phase. The complexity of merge_ffs is O(n 3) where n is the number of flip-flops in the circuit and the complexity of cluster_CL Us is O(nm) where m is the number of combinational gates in the circuit.

CLU2'3'4

~U2 PO PI

CLUa

R3

(a)

(b)

Fig. 6. Reorganized views putting them into one register would create a combinational path from the register to itself. In the reorganized view, the register would appear in a self-loop. This leads to the second condition for merging. C o n d i t i o n 2: Two flip-flops (partial registers) i and j can be merged into one partial register if either (a) i E IL(i) a n d j E IL(j), or (b) i ~ Ii(i), j ~ IL(j) and i ~ Ii(j), j ~ Ii(i). L e m m a 1: Any two flip-flops satisfying Condition 1 and Condition 2 belong to the same maximal register. To ensure correct modelling of global loops in the reorganized view, a condition similar to the self-loop case is required for the compatibility of flip-flops (partial registers). C o n d i t i o n 3: Two flip-flops (partial registers) i and j can be merged into one partial register if / ~ / b o t h i and j are in global loops, or neither is in a global loop and all existing paths i ,,~ j and j ,,- i are only combinational paths. Since a register should have flip-flops that are functionally similar, the fourth condition is that of homogeniety of flip-flops C o n d i t i o n 4: Two flip-flops (partial registers) i and j can be merged into one partial register if (a) both i and j are of the same type, (i.e both are D flip-flops or both are J-K flip-flops), and (b) both i and j have the same functionality (e.g. shift, hold, etc.) and are driven by the same control lines. Two flip-flops are said to be compatible if and only if they satisfy Condition 1, 2, 3 and 4. The algorithm merge_ffs iteratively merges compatible flip-flops (partial registers). When two flip-flops (partial registers) merge into one partial register the newly created partial register gets a new label of its own and new input and output labels. This is because the newly created register inherits the connectivity and loop properties of both the flip-flops. For the same reason other flip-flops (partial registers) have their labels updated to reflect the merge. Suppose flip-flops with labels i and j are merged into a partial register, Rmerge, with the new label p. The input label of the newly created partial register, IL(p) = IL(i) O Ii(j). Similarly, an output label is created. The input and output labels of all the other flip-flops (partial registers) in the circuit are affected by this merge and need to be updated. The effect of the merge on some other flip-flop (partial register) k is as follows: If i E Ii(k) or j E IL(k) then Ii(k) = IL(k) - {i,j} U {p}, else IL(k) is unchanged. The output label OL(k) is updated similarly. The merg~ ing of partial registers and flip-flops iterates until no more merging is possible.

V.

IMPLEMENTATIONAND RESULTS

CLARION has been implemented in C + + and runs on a SUN-Sparc2 workstation. It has been integrated into the USC-Test system which supports a family of software tools and systems for making circuits testable. CLARION acts as a pre-processor to the subsystems which apply the various DFT and BIST techniques. To demonstrate the advantages of the reorganization methodology many circuits have been processed by CLARION. The reorganized high-level views of three circuits produced by CLARION are shown in Fig. 7. Circuits C1 and C2 are modified DSP designs while circuit C3 is a processor designed by GME Corp. All the circuits were entered into our system according to the hierarchy specified by the designer using library components such as ripple-carry adders, multipliers and multiplexers. The circuits were flattened down to the logic gate and flipflop level and then reorganized into a 2-level hierarchy by CLARION. The high-level descriptions generated very closely resemble the original descriptions provided by the designers. The numbers in the parentheses in Fig. 7 refer to the number of gates or flip-flops in the CLUs and registers, respectively. For the sake of simplicity, the control portion of the designs (control circuitry and control lines of registers, multiplexers, etc.) has been omitted. The CLARION view of the circuits was used to make the circuits testable by selecting scan registers. The scan system SIESTA identifies two classes of circuit structures that have desirable testability properties - acyclic in which there are no feedback loops and balanced, which are acyclic circuits where all paths between combinational gates pass through the same number of registers [6]. The partial scan methodologies ACYST and BALLAST have been developed to select scan registers such that the structures to be tested are acyclic or balanced, respectively. Another partial scan approach, suggested by Cheng and ,Agarwal [7], selects a minimal number of flip-flops to be r/iade scannable such that all global feedback loops are broken. Selecting a minimal number of such flip-flops is

349

TABLE I c

C1(173)

cc~"

SCAN

CC~(173)

REGISTERSSELECTEDBY HIGH-LEVELPARTIAL SCAN TOOLS

C1 C2 C3

c4(132) ~- C5(h2) ~ cdn2) Circuit C1

BALLAST 82, 83, R4 R~, Ra, Rs, 86, R,l

ACYST R4, Rs, Re

R,, R2, R4, Rs, R6, R,

R~, R4, Rs, R6

HL-CYC. 84

R2, Rs,

81(8) Ci(189) RI(8) C2(189) 83(8) TABLE II SUMMARY OF CIRCUITS REORGANIZED BY CLARION

Ckt name 8..,

~

~ 17 12)

s382 s444 s510 s713 s820 s1238 s1488 s5378 C1 C2 C3

811(4)

Rs(2) 89(2) Rio(2) Circuit C2

@

.n.A I

°

l

l

-c;

CPU

output CLUs Reg 7 3 8 3 7 2 8 3 6 2

Time (sec) 3.2 4.9 6.8 11.8 12.0

3

1

18.7

5 31 6 8 8

2 18 4 11 7

42.3 236.9 30.7 23.2 141.6

results

an NP-complete problem and because of the large number of nodes in the graph model of a flattened circuit, heuristics have to be used. H L - C Y C L I S T is a similar methodology that breaks global feedback loops at the high-level by selecting a minimal number of registers. Since the number of C L U s and registers in a circuit is usually orders of magnitude smaller than the number of gates and flip-flops, a minimal number of registers can be selected very efficiently. The registers selected to be scanned for the circuits using these methodologies are shown in Table I. Note that since circuit C1 is acyclic, A C Y S T and H L - C Y C L I S T do not select any registers. The circuit statistics in terms of the number of circuit components of some ISCAS89 benchmark circuits reorganized by C L A R ION and the C P U time required for the reorganization is shown in Table II. These results demonstrate the usefulness of the high-level view produced by C L A R I O N for high-level D F T techniques. Vl.

CLARION

the high-level dataflow structures extracted by C L A R I O N from random netlists actually m a t c h designer's views of the same circuit, and (2) such views are effective for the application of D F T and BIST techniques. Often when a designer does not have a good idea of the high-level structure of a design, the C L A R I O N view provides an excellent model for the structure and allows for a simpler analysis of the design.

Circuit C3 Fig. 7. C L A R I O N

Flat circuit Gates FFs 158 21 181 21 211 6 393 19 289 5 508 18 653 6 2779 179 794 32 458 52 1251 101

CONCLUSIONS

A technique for extracting high-level structure from circuit descriptions has been presented. This capability is very useful in most CAD applications and it allows CAD tools to operate more efficiently. The results show that (1)

REFERENCES

[1] B.W. Kernighan and S. Lin. An Efficient Heuristic Procedure for Partitioning Graphs. Bell Syst. Tech. J., pages 291-307, 1970. [2] E.S. Kuh and T. Ohtsuki. Recent Advances in VLSI Layout. In Proc. o/the IEEE, pages 237-263, February 1990. [3] T. Hattori, C. Miura, and S. Miayamoto. A Method of Dataflow Oriented Cell Initial Placement. In Proc. lnt'l Workshop on Layout Synthesis., May 1990. [4] G. Odawara, H. Takahisa, and N. Osamu. Partitioning and Placement Technique for CMOS Gate Arrays. IEEE Trans. on Comp. Aided Design, pages 355-363, May 1987. [5] T.H. Cormen, C.E. Leiserson, and R.L. Rivest. Introduction to Algorithms. The MIT Press and McGraw-Hill Book Company, 1990. [6] S. Narayanan, C.A. Njinda, R. Gupta, and M.A. Breuer. SIESTA: A Multi-facet Scan Design System. In Proc., Ist EURO-Design Automation Con/., September 1992. [7] K.-T. Cheng and V.D. Agrawal. An Economical Scan Design for Sequential Logic Test Generation. In Proc. FaultTolerant Computing Symposium (FTCS-19), pages 28-35, June 1989.

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