IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 7, JULY 2006
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Fabrication and Characterization of Field-Plated Buried-Gate SiC MESFETs Kristoffer Andersson, Mattias Südow, Per-Åke Nilsson, Einar Sveinbjörnsson, Hans Hjelmgren, Member, IEEE, Joakim Nilsson, Johan Ståhl, Herbert Zirath, and Niklas Rorsman
Abstract—Silicon carbide (SiC) MESFETs were fabricated using a standard SiC MESFET structure with the application of the “buried-channel” and field-plate (FP) techniques in the process. FPs combined with a buried-gate are shown to be favorable concerning output power density and power-added efficiency (PAE), due to higher breakdown voltage and decreased output conductance. A very high power density of 7.8 W/mm was measured on-wafer at 3 GHz for a two-finger 400-µm gate periphery SiC MESFET. The PAE for this device was 70% at class AB bias. Two-tone measurements at 3 GHz ± 100 kHz indicate an optimum FP length for high linearity operation. Index Terms—Buried-gate, field-plate (FP), microwave power, silicon carbide (SiC) MESFET.
have been presented for AlGaN/GaN HEMT technology. The FP reduces the peak electric field at the gate, enabling both higher operating breakdown voltage [5] and reduced dispersion [6], leading to higher output power densities and PAE. Physical simulations have indicated similar effects for SiC MESFETs [7]. This letter describes the process and results for SiC MESFETs fabricated using a standard SiC MESFET structure with the application of the buried-gate (or “buried-channel”) and integrated FP techniques to SiC MESFET fabrication. II. D EVICE F ABRICATION
I. I NTRODUCTION
T
HERE ARE increasing demands for higher RF power, more efficiency, broader bandwidths, and smaller more compact devices for communication and radar applications. Silicon carbide (SiC) has high thermal conductivity (3.5 W/cm · K), high breakdown voltage (3 MV/cm), and high electron saturation velocity (2.1 · 107 cm/s), making it suitable for these applications. During the development of SiC MESFET technology, several trapping problems have been identified. These trapping effects result in lower output power density and power-added efficiency (PAE) than expected. Previously, the vanadiumdoped semi-insulating SiC substrate attracted much attention in explaining the deterioration of the SiC MESFET microwave performance [1]. The larger part of the problems associated with the substrate was solved by the introduction of vanadiumfree (high-purity) substrates. Recently, the attention has shifted more toward surface traps, which cause gate-lag effects. In [2], a buried-gate approach was shown to result in less trapping, resulting in a reduction in current instability and higher output power density. In [3], an undoped spacer layer was shown to give nearly ideal gate-lag ratio, resulting in improved microwave power performance. Field-plates (FPs) are used in Si and III–V technologies [4] to enhance the breakdown of the devices. Recently, similar studies Manuscript received February 24, 2006; revised April 19, 2006. This work was supported by the Swedish Agency for Innovation Systems (VINNOVA). The review of this letter was arranged by Editor K. Kornegay. K. Andersson, M. Südow, P.-Å. Nilsson, E. Sveinbjörnsson, H. Hjelmgren, H. Zirath, and N. Rorsman are with the Microwave Electronics Laboratory, Chalmers University of Technology, 412 96 Göteborg, Sweden (e-mail:
[email protected]). J. Nilsson and J. Ståhl are with the Ericsson Microwave Systems AB, 431 84 Mölndal, Sweden. Digital Object Identifier 10.1109/LED.2006.877285
The MESFETs were made on 4H-SiC semi-insulating wafers with a buffer/channel/cap epi stack grown by Cree, Inc. The buffer is p-doped (NA = 5 · 1015 cm−3 ) and 0.34 µm thick. The channel and cap layers are n-doped (ND = 2.7 · 1017 and 1.6 · 1019 cm−3 ) with thicknesses of 0.34 and 0.33 µm, respectively. Details of the process have been described previously [8]. In short, the process includes mesa etching for channel definition and device isolation, Ni contacts, Ti/Pt/Au gates, Au pads, passivation, air bridges, and an optional via-hole grounding step. Gate patterning is made using e-beam lithography, whereas the other steps are patterned with standard contact photolithography. Etching is made using an inductively coupled plasma (ICP) with a fluorine-based plasma. MESFETs with a gate length of 400 nm and varying gate peripheries were made. To create the FP structure used in this work, the gate areas of the transistors were made as follows: First, a thermal oxide, with a thickness of 1400 Å, was grown on top of the channel area. An opening where the gate should be placed was etched through this oxide and continued down into the SiC channel. This step defined the gate length, and the drain current of the device could be determined by the etch depth into the SiC channel [3]. Second, the Ti/Pt/Au gate was deposited on top of the opening, and an overlap toward the drain side gave an FP. The FP length was varied from 50 to 450 nm. The overlap of the gate on the source side is 50 nm for all devices. A cross section of the device is shown in Fig. 1. To get the correct etch depth, the current level between source and drain contacts was measured during the etching process. The etching was then stopped at a specific current value, which was determined from physical device simulations with Synopsys/ISE-TCAD. The simulations began with finding the etch depth that would give the targeted pinch-off voltage and drain current of the completely processed transistor. This etch depth was then used
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IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 7, JULY 2006
TABLE I EQUIVALENT CIRCUIT PARAMETERS (ECPS), AVERAGE TRANSIT FREQUENCY (fT ), MAXIMUM FREQUENCY OF OSCILLATIONS (fmax ), OUTPUT POWER AT 1- AND 3-dB COMPRESSIONS (P1 dB AND P3 dB ), SMALL SIGNAL GAIN (Gp0 ), AND MAXIMUM PAE (PAEmax ) FOR THE D IFFERENT FP L ENGTHS FOR A T WO -F INGER 400-µm G ATE PERIPHERY SiC MESFET AT VDS = 60 V AND VGS = −17 V. THE ECPS ARE EXTRACTED FROM S-PARAMETERS AT VDS = 40 V AND VGS AT MAXIMUM fT . ALL VALUES ARE AVERAGES TAKEN FROM FOUR DEVICES
Fig. 1. IDS versus VDS for a two-finger 100-µm gate periphery SiC MESFET. The top curve is for VGS = 0 V, and the step is −4 V. The inset shows a cross section of the buried-channel and FP SiC MESFET.
in the simulations to determine the corresponding current level between drain and source, thus the etch stop criteria. Although this method requires a carefully calibrated simulation input desk, it has several advantages; e.g., we do not have to know the exact etching rate and thickness of the channel layer. III. M EASUREMENTS A. DC Both static and dynamic current–voltage (I–V ) were measured. The saturated drain-to-source current is 370 mA/mm with a pinch voltage Vp of −18 V (Fig. 1). The dc transconductance gm is 31 mS/mm. The gate-lag ratio, defined as IDSS(pulsed) /IDSS(DC) , was 98% and 86% at VDS = 1 and 10 V, respectively, when pulsing from VDS = 15 V and VGS below Vp . The 0.5-µs-wide pulses were separated by 1 ms. Gate–drain reverse breakdown measurements were performed for the different FP sizes. It increased from 190 to > 200 V for FP lengths of 50 and 150 nm, respectively. B. S-Parameters S-parameters were measured on-wafer from 50 MHz to 45 GHz for several groups of MESFETs. Measured transistors had a gate periphery of 2 × 200 µm. From measured S-parameters, extrinsic fT and fmax [maximum available gain (MAG = 1)] were calculated (Table I). The FP causes a reduction in high-frequency performance due to the increased gate associated capacitances. However, the negative impact of FPs on fT is almost negligible (less than 8% reduction). fmax is somewhat higher for wider FPs. This is mainly due to a reduction of output conductance for wide FPs (Table I). C. Microwave Power Measurements Load–pull and power sweep measurements were performed on-wafer at 3 GHz with a temperature-controlled chuck (Summit 10 000 and Temptronic). The chuck had a temperature of 25 ◦ C. The wafer (thickness 360 µm) has a backside metalization of Ti/Au. The wafer is only mounted to the heat sink
Fig. 2. Pout , Gp , and PAE versus Pin for a two-finger 400-µm gate periphery SiC MESFET. The device was biased in deep class AB (VDS = 65 V, VGS = −19 V).
by vacuum. Measured transistors had a gate periphery of 2 × 200 µm2 and 10 × 100 µm2 . The load and source impedances were tuned for maximum output power and a Gp of 12–15 dB, respectively. The highest continuous-wave (CW) output power density (7.8 W/mm) was measured for a two-finger 400-µm gate periphery SiC MESFET with an FP of 450 nm at VDS = 65 V and VGS = −19 V with a maximum PAE of 70% (Fig. 2). For a 1-mm MESFET with an FP of 250 nm, the maximum CW output power density was 5.2 W/mm at VDS = 65 V and VGS = −17 V with a PAE of 36%. The influence of FP length on microwave power performance was investigated by load–pull and power sweep measurements. The measurements were performed in class AB at a VDS of 40–65 V. The average (from four device groups) maximum output power at 1- and 3-dB compressions (P1 dB and P3 dB ), small signal gain (Gp0 ), and maximum PAE (PAEmax ) for the different FPs are presented in Table I. The FP is favorable for all parameters. To verify the results, measurements on the identical tenfinger 1-mm gate periphery SiC MESFET were performed in two different load–pull systems [at Chalmers University and Ericsson Microwave Systems AB (EMW)]. At EMW, CW
ANDERSSON et al.: FABRICATION AND CHARACTERIZATION OF FIELD-PLATED BURIED-GATE SiC MESFETs
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lengths were fabricated and characterized. The output power density at 1-dB compression increased from 5.0 to 6.0 (20%), and the maximum PAE increased from 56% to 66% when the FP length increased from 50 to 450 nm. These improvements are explained by the increase in breakdown voltage and decrease in output conductance. The combination of buried-gates and FPs resulted in a very high power density of 7.8 W/mm at 3 GHz. This is, to our knowledge, among the highest reported output power densities for small SiC MESFETs. The PAE for this device was 70% at class AB bias. Two-tone measurements at 3 GHz ± 100 kHz indicate an optimum FP length for high linearity operation. An OIP3 of 39.8 dBm was measured for a for a two-finger 400-µm gate periphery SiC MESFET at VDS = 60 V. Fig. 3. Third-order output intercept point (OIP3 ) versus FP length for a twofinger, 400 µm gate periphery SiC MESFET at a VDS of 40, 50, and 60 V.
measurements were made on a standard chuck (no temperature control), and no vacuum was used to hold the wafer to the chuck. The maximum output power (maximum PAE) was similar, 35.4 and 35.1 dBm (38% and 34%) at VDS = 40 and VGS = −15 V, in the Chalmers and EMW measurement setups, respectively. The discrepancy in efficiency can be explained by different harmonic impedances and gains (13 and 10 dB). Finally, two-tone measurements at 3 GHz ± 100 kHz were performed on two-finger 400-µm gate periphery SiC MESFETs with different FP lengths to determine the linear characteristics at a VDS of 40, 50, and 60 V. The devices were matched for optimum power, at the fundamental frequency. The measurements are summarized in Fig. 3. The measurements indicate that there is an optimum FP length for high linearity (around 200–250 nm) for this SiC MESFET design. IV. C ONCLUSION SiC MESFETs were fabricated using a standard SiC MESFET structure with the application of the buried-channel and FP techniques in the process. MESFETs with different FP
R EFERENCES [1] N. Sghier, J.-M. Bluet, A. Souifi, G. Guillot, E. Morvan, and C. Brylinski, “Study of trapping phenomena in 4H-SiC MESFETs: Dependence on substrate purity,” IEEE Trans. Electron Devices, vol. 50, no. 2, pp. 297–302, Feb. 2003. [2] H.-Y. Cha, C. I. Thomas, G. Koley, L. F. Eastman, and M. G. Spencer, “Reduced trapping effects and improved electrical performance in buriedgate 4H-SiC MESFETs,” IEEE Trans. Electron Devices, vol. 50, no. 7, pp. 1569–1574, Jul. 2003. [3] H. Henry, G. Augustine, G. DeSalvo, R. B. R. C. Brooks, J. Oliver, A. Morse, B. Veasel, P. Esker, and R. Clarke, “S-band operation of SiC power MESFET with 20 W (4.4 W/mm) output power and 60% PAE,” IEEE Trans. Electron Devices, vol. 51, no. 6, pp. 839–845, Jun. 2004. [4] C.-L. Chen, L. J. Mahoney, M. J. Manfra, F. W. Smith, D. H. Temme, and A. R. Calawa, “High-breakdown-voltage MESFET with a lowtemperature-grown GaAs passivation layer and overlapping gate structure,” IEEE Electron Device Lett., vol. 13, no. 6, pp. 335–337, Jun. 1992. [5] J. Li, S. Cai, G. Z. Pan, Y. L. Chen, C. Wen, and K. L. Wang, “High breakdown voltage GaN HFET with field-plate,” Electron. Lett., vol. 37, no. 3, pp. 196–197, Feb. 2001. [6] W. Saito, M. Kuraguchi, Y. Takada, K. Tsuda, I. Omura, and T. Ogura, “Influence of surface defect charge at AlGaN-GaN-HEMT upon Schottky gate leakage current and breakdown voltage,” IEEE Trans. Electron Devices, vol. 52, no. 2, pp. 159–164, Feb. 2005. [7] H.-Y. Cha, Y. C. Choi, L. F. Eastman, and M. G. Spencer, “Simulation study on breakdown behavior of field-plate SiC MESFETs,” Int. J. High Speed Electron. Syst., vol. 14, no. 3, pp. 884–889, Sep. 2004. [8] N. Rorsman, P. Nilsson, J. Eriksson, K. Andersson, and H. Zirath, “Investigation of the scalability of 4H-SiC MESFETs for high frequency applications,” Mater. Sci. Forum, vol. 457–460, no. 2, pp. 1229–1232, 2004.
