Fabrication and Characterization of Tungsten-OxideBased Memristors for Neuromorphic Circuits Dana Wheeler*, Ivan Alvarado-Rodriguez, Ken Elliott, James Kally, John Hermiz, Heather Hunt, Tahir Hussain, and Narayan Srinivasa† Microelectronics Laboratory, †Information and Systems Sciences Laboratory HRL Laboratories, LLC Malibu, CA 90265, USA *
[email protected] Abstract—We report a fabrication process and electrical results for tungsten-oxide-based memristors compatible with CMOSbased neuromorphic circuits. Memristor crossbar arrays are fabricated on partially-processed wafers from a CMOS foundry to form hybrid FET-memristor circuits that can serve as analog memory elements for synaptic weight storage. Successful integration is demonstrated through the programming and reading of memristor crossbar array elements addressed through a CMOS multiplexer/demultiplexer.
nitride layer that caps a “2×” interconnect metal layer. The result is a planar substrate that features contact points through which CMOS electronics are connected to the subsequentlyintegrated memristor crossbar array; Fig. 1 is a flow diagram of this process.
I. INTRODUCTION Since the identification of certain classes of nanoelectronic devices featuring hysteretic current-voltage behavior as memristors, research in materials, fabrication processes, and applications for such devices has met with renewed interest [1,2]. Functionally, the memristor behaves much like a biological synapse; this similarity has led to the employ of memristors in neuromorphic (brain-like) architectures [3,4]. While several different implementations of neuromorphic circuits have been proposed [4–6], all share the goal of drawing inspiration from biology to establish a new paradigm of information processing. Thus, the ability to combine memristors with conventional transistors in a monolithic IC process flow is a powerful tool for the creation of new computing platforms. Among the many candidate materials, tungsten oxide formed by thermal oxidation is attractive for memristors due to tungsten’s wide-spread use in foundries and an oxidation temperature that is compatible with CMOS processing (≤ 400 °C). This work leverages these features to produce circuit components of utility for neuromorphic architectures. II. DEVICE FABRICATION AND CMOS INTEGRATION The memristor arrays are based on the work described in [7,8] and fabricated on 90-nm-node CMOS substrates which feature a copper-based back-end-of-line stack. To facilitate heterogeneous integration, the CMOS process is only partially completed by the foundry, finishing with a passivating silicon A portion of this work was performed under DARPA SyNAPSE. This work is approved for public release and distribution is unlimited. The views expressed are those of the author and do not reflect the official policy or position of the Department of Defense or the U.S. Government. 978-1-4799-6007-1/14/$31.00 ©2014 IEEE
Fig. 1. Cross-sections and plan views of memristor-on-CMOS process. (a) Partially-processed 90-nm-node CMOS wafers capped with silicon nitride constitute the starting substrate. (b-e) A dual damascene process forms the bottom array electrodes and vias to CMOS. (e) Thermal oxidation in atmosphere produces a tungsten oxide layer on top of exposed tungsten surfaces. (f-g) Photolithographic patterning is used to selectively etch tungsten oxide from top-electrode-CMOS vias. (h) A lift-off process forms the Pd/Au top electrodes.
Individual devices consist of a 600×600-nm2 overlap area of bottom electrode (BE) and top electrode (TE) crossbars with 30 nm of tungsten oxide in between. X-ray diffraction measurements on blanket monitor films reveal peaks (of roughly equal magnitude) consistent with WO2 and WO3 phases. Arrays contain eight BEs and sixteen TEs, producing 128 devices per array. Depending on purpose, electrodes are directly connected to probe pads or a CMOS multiplexer/ demultiplexer (MUX/DeMUX) for simplified array testing, or to a neuromorphic CMOS circuit, the most complex of which includes 576 16×8 arrays (73,728 memristors), for more sophisticated evaluation. Following fabrication, focused-ion beam milling reveals the cross-section of array devices and vias to the CMOS foundry metals, Fig. 2. Electrical measurements of chains of vias between the foundry (Cu) and heterogeneously-integrated (Ti/W/Pd/Au) metals show contact resistance ~2 Ω-µm2, which has negligible impact on performance as devices at this scale (0.36 µm2) typically exhibit resistances in the range of kΩ-MΩ, depending on oxide thickness and programming history.
Fig. 2. Scanning electron micrographs (SEMs) of a 16×8 memristor crossbar array on 90-nm CMOS. Cross-sections were prepared by focus-ion beam (FIB) milling along a top electrode.
III. DEVICE CHARACTERIZATION The primary verification of successful device fabrication is production of the “pinched-hysteresis” curve that is characteristic of all memristive devices. As shown in Fig. 3, repeated voltage ramps from 0 to + (-) 1.2 V and back result in increased (decreased) conduction through the device. This is also observed within a given sweep, as currents are higher (lower) on return sweeps for positive (negative) bias. Memristor behavior is also exhibited in pulse-mode operation, with incremental increases (decreases) observed during repeated 10-µs, + (-) 1.2-V pulses.
Fig. 4. Test schematic and results of crossbar array programming. (a) An arbitrary waveform generator (AWG) provides pulse stimulus to top and bottom electrodes (TE/BE) selected by an on-chip CMOS multiplexer (MUX). (b) SEM of 16×8 crossbar array. (c) Histogram of read pulse currents measured through each of the 128 memristors after programming “HRL” pattern into array (inset).
IV. CONCLUSION A CMOS-compatible process integrating tungsten-oxide memristors with silicon transistors enables hybrid circuits that can serve as building blocks for neuromorphic architectures. Initial results have demonstrated characteristic memristive behavior and interoperability with silicon electronics. Additional characterizations, such as state retention time and device lifetime measurements, will further evaluate the efficacy of tungsten oxide memristors in neuromorphics. REFERENCES [1] [2]
Fig. 3. DC and pulse-mode characteristics of tungsten oxide memristor measured through CMOS interconnects. Successive positive (negative) voltage sweeps produce increasing (decreasing) currents; corresponding behavior is observed when voltage pulses are applied (inset).
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Verifiation of a successful, CMOS-compatible integration process is achieved through the simultaneous operation of memristors and transistors in a hybrid circuit in which a MUX/DeMUX selects BEs and TEs for individual device programming. Using a computer-controlled switch matrix to supply digital address inputs, an arbitrary bit pattern was progammed into a 16×8 array by stimulating select devices with a programming pulse. Approximatley five seconds after programming, the state of the memristor is assessed with a read pulse, which is typically half the magnitude of the programming pulse. Figure 4 depicts the test setup and programming results.
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