Factors Affecting Electromigration and Current ... - Amkor Technology

12th Electronic Packaging and Technology Conference Singapore, Dec 8 - 11, 2010

Factors Affecting Electromigration and Current Carrying Capacity of FC and 3D IC Interconnects Ahmer Syed Amkor Technology 1900 S Price Road Chandler, AZ 85286 Abstract Electromigration (EM) failure in flip-chip bumps has emerged as a major reliability concern due to potential elimination of Pb from flip-chip bumps and a continuous drive to increased IO density resulting in a reduction of bump pitch and size. Additionally, the rapid development and implementation of 3D IC structures is introducing new interconnects (u-bumps, RDL, microvias, and TSVs) at a much finer geometries, raising concerns about electromigration and current carrying capacity of these interconnects. In order to estimate the current carrying capacity of these interconnect structures, electromigration tests need to be conducted. However, conducting an EM test is not a trivial task as factors such as test structure, resistance and joule heating measurement, and failure criteria have a direct impact on the estimated current carrying capacity. In addition, metallurgical features such as solder alloy used, UBM stackup and materials, and surface finish on the substrate side have a significant impact on EM reliability. This paper discusses some of the factors affecting the EM reliability of fine pitch interconnects and how test design, data collection and interconnect metallurgies affect the EM performance. Introduction While electromigration behaviour of interconnects within a chip has remained a major reliability concern due to continuous reduction in feature size [1, 2], the emphasis on package level interconnects has seen a renewed interest more recently [3, 4, 5, 6, 7, 8 ] due to multiple factors. These factors include the potential elimination of Pb from flip chip bumps, increased IO density resulting in smaller and finer pitch bumps, and the introduction of 3D IC structures such as ubumps, TSVs, RDL, and microvias. At the same time, the increase in power density and higher power applications are requiring chip-to-package interconnects to carry more current per interconnect. Since electromigration reliability is a direct function of interconnect sizes and metallurgies, all of these new interconnect developments on the packaging side need to be characterized for electromigration reliability. The primary purpose of electromigration (EM) reliability characterization of an interconnect type is to determine its current carrying capacity under operating conditions for the designed useful life and an acceptable failure rate. The estimation of this current carrying capacity requires testing these interconnects under accelerated test conditions with higher levels of current and temperatures than these interconnects will usually experience in actual operating conditions. Like any other accelerated test, the underlying

assumption in accelerated EM tests is that the failure modes remain the same in accelerated and use level conditions. While the selection of accelerated levels is obviously important from failure mode consideration, other test related items such as test structures, resistance measurements, joule heating, and failure criteria can also have a significant impact on current carrying capacity estimation. Hence, in order to estimate the current carrying capacity and the reliability of these interconnects for a given use condition with confidence, one must consider all factors related to test design and interconnect geometries and metallurgies that may have an influence. While industry standard test method for bump electromigration exists [9], and provides guidance for a proper test design, it lacks real examples to show the impact of wrong choice on the results. Similarly, a gap exists in performance comparison of different bump metallurgies because of differences in test structures and geometries [3 - 8]. In addition, not all published data provides the essential parameters of Black’s equation and failure distribution to determine the performance and reliability for actual use conditions. This paper highlights the effect of test design and the bump metallurgies on electromigration reliability and current carrying capacity estimation. First, the impact of test parameters and methods are discussed to show their significance on current carrying capacity estimation. This is followed by test data on four different bump metallurgies and show how a common assumption on bump alloy behavior can be misleading if other factors such as UBM stack and surface finish are not are considered. Test Design and Data Collection Considerations Since the final aim of an electromigration test is to determine the current carrying capacity of an interconnect circuit, care must be taken to ensure a proper test vehicle design and test data collection method. In a typical EM test, special test structures are designed and tested under accelerated levels of current and temperature. The resistance of these structures is monitored throughout the test and failure data is collected using either absolute or percent increase in resistance. The tests are done for multiple stress conditions (combinations of current and temperature) and the failure data from each test is used to determine the parameters of Black’s Equation (Eq. 1), which relates mean time to failure (MTTF) to current density and temperature.

E  MTTF = A J − n exp  a  KT  

(1)

Where, MTTF = Mean Time to Failure (Hours)

978-1-4244-8561-1/10/$26.00 ©2010 IEEE

2010 12th Electronics Packaging Technology Conference

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J = Current Density (Amps/cm2) T = Temperature (K) n = Current density exponent Ea = Activation Energy, eV K = Boltzmann’s constant, 8.62e-5 eV/K, and A = a constant Once the mean life is determined from the test, the currant carrying capacity for a certain operating life and failure rate is estimated using lognormal distribution and Black Equation’s parameters. Typically this estimate is done for 0.1% failure rate for 10 years of continuous operation using Equation 2

t 0.1% = MTTF exp(−3.09σ )

(2)

Where, σ is the standard deviation from lognormal distribution. Thus, the accuracy of this estimate is directly dependent on the accuracy of n and Ea estimation in Black’s equation, which in turn are dependent on correct temperature and life measurements. The life measurement is itself dependent on the accuracy of resistance measurement and the choice of failure criteria. Thus, factors such as EM structure, proper accounting for joule heating, resistance measurement, and failure criteria have a direct influence on current carrying capacity calculation. EM Test structure: The two most common approaches for EM test structure are a) multiple bumps in a single daisy chain, and b) multiple bumps feeding current to one bump of interests. These structures are discussed in JEDEC Standard JEP154 [9] in more detail and are depicted in Figure 1 below. Both of these approaches have advantages and disadvantages in terms of testing but also have implications on failure criteria and failure mode.

criterion, this increment can be either due to a large increase in one bump or due to accumulation of smaller increases in resistance in multiple bumps. One the other hand, using % increase in resistance as a criterion can possibly lead to over estimation of life if this increase occurred primarily due to degradation in one bump. For both of these cases, detailed failure analysis on all bumps within a chain is required on multiple samples to ascertain the reason for resistance increase. To avoid this issue, another EM structure is commonly used where multiple bumps feed current into one bump of interest, Figure 1b. This typically guarantees the failure in one bump but has other complication associated with it. Because the full current is fed from only one side (die or substrate side) for the bump of interest, only that interface fails as the other interface is tested at a much lower current. Although the failure data for the other interface can be gathered by repeating the test and reversing the current flow direction, the total test matrix doubles requiring more test resources/time to gather full data. Also, since multiple bumps and traces from these bumps are feeding the current to the bump of interest, current crowding is reduced and failure data may not be representative of actual applications where current is fed through one directional traces only. A better EM structure is a two bump daisy chain as shown in Figure 2. This structure tests both directions of current flow for the same level of current in one test and failure analysis is simplified. Since the overall daisy chain length is reduced, this structure also provides the benefit of higher contribution of bump resistance in the total resistance of the net. This also has the benefit of using absolute resistance increase as a failure criteria as the degradation due to EM is pre-dominantly in one bump. Cathode

Die

e-

e-

Anode

(a) Multiple bumps in a single daisy chain.

Anode

Cathode

Substrate Figure 2: Two bump daisy chain with same current in each direction.

(b) Multiple bumps feed current to one bump of interest Figure 1: Typical EM structures used for bump testing. In the case of multiple bumps in one daisy chain, Figure 1a, alternate bumps are stressed in opposite direction with the same level of current. There are two main disadvantages of this approach; the overall chain resistance is much larger than a single bump resistance, and multiple bumps may degrade due to EM stressing making failure analysis difficult. The overall chain resistance has also implication on the failure criteria used. If absolute resistance increase is used as a

Test Structure Resistance Measurement: Since the resistance of a typical flip chip bump is very low - in the range of 5 to 20milliohm - measuring the resistance of the EM structure as close as possible to the bump of interest using 4point Kelvin measurement is very important. This is especially true of multiple bump chains as locating the voltage taps away from the EM structure results in reduction in the contribution of bump resistance to the overall circuit and 5 to 10 milliohm change in bump resistance due to current stressing may not show up as a significant in the overall resistance. This has an implication on failure criteria and failure data as discussed later. For accurate resistance measurement in milliohms range, extremely sensitive voltage measurement system is required. Joule Heating Effect: The localized temperature increase of EM structure due to current stressing can be a significant factor in determining Black’s equation parameters accurately. 2010 12th Electronics Packaging Technology Conference

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time, in which case the failure criterion becomes important. This is shown in Figure 5 where two different failure criteria are used on the same data. The failure criteria of 20% increase in resistance results in much higher estimation of current carrying capacity than a criterion of 3.3milliohm resistance increase. 0.1% failure rate at 100K hours 600 Max Current (mA)

The best way to measure the localized temperature is through the use of temperature sensing element (resistor or diode) directly above or underneath the bump of interest. The other method is to determine the Temperature Co-efficient of Resistance (TCR) of the EM structure, which is possible with some electromigration test systems. However, this value is typically an average temperature increase of the whole EM structure and depends on the designed EM structure and location of voltage taps for 4-point Kelvin measurements. The localized maximum can be a few degrees higher than this number. Figure 3 shows this effect clearly on the n value of Black’s equation as well as on maximum current carrying capacity estimation. The n value is 73% higher if temperature increase due to joule heating (5 to 11oC in this case) is not accounted for. Similarly the estimated n value is 33% higher if average temperature increase (2 to 5oC) is used instead of localized maximum. This translated into 2 to 3X higher estimation of current carrying capacity at 110oC in this particular case.

500

3.3mohm resistance increase

400

20% resistance increase

300 200 100 0 80

90

100

110

120

Temperature (deg C)

Figure 5: Effect of failure criteria on current carrying capacity estimation.

t0.1% failure rate, 100,000 hrs

Maximum Current (mA)

180 160

Maximum Localized Temp, n = 1.5

140

Average Localized Temp, n = 2.0

120

Oven Temperature, n = 2.6

100 80 60 40 20 0 80

90

100

110

120

Temperature (deg C)

Figure 3: Effect of joule heating on ‘n’ value and maximum current carrying capacity estimation. Effect of Failure Criteria: There are two failure criteria commonly in use for EM testing; % increase in resistance and absolute increase in resistance. Depending on the EM structure and interconnect structure, failure criteria used may have a significant influence on current carrying capacity estimation. Figure 4 shows two typical plots of resistance vs. time data from EM testing. Resistance (Ohms)

0.1 0.09 Gradual Increase

0.08

Sudden Open

0.07 0.06 0.05 0.04 0

500

1000 1500 2000 Time (hours)

2500

3000

Figure 4: Typical Resistance vs. Time plots from EM testing. In one case, the bump becomes suddenly open and failure time becomes independent of failure criteria. However, the more common case is the gradual increase in resistance with

Both percentage increase and absolute increase in resistance are also dependent on the EM test structure used. For example, for a long daisy chain with multiple bumps and initial resistance of 200milliohm, a 20 milliohm increase (or 10%) might be only in one bump or it might be an accumulation of smaller resistance increases in multiple bumps. It is also common to observe small resistance increase of the bump as the solder alloy material converts into IMC. In this case, setting a failure criterion which does not account for this natural increase in resistance might lead to false conclusions. This factor is bound to become more important for u-bump structures and has been observed in internal testing as well as reported in the literature [10]. With all these complications, a better way is to continue testing until complete open or very large increase in resistance and comparing different failure criteria after ascertaining the failure mode. Bump Metallurgy and Interface Considerations Flip chip bump electromigration reliability is also dependent on a number of factors specific to the actual bump structure. These include UBM and passivation opening, UBM stack and material, bump size, bump solder alloy, and substrate pad finish and pad size. Most of the studies published focus on the UBM side of the joint as this is considered as the failure interface. Sometimes the conclusions are also drawn irrespective of changes in bump and interface metallurgy. For example, it is commonly assumed that high Pb bump performs the best from EM standpoint and all recent developments (e.g., SnPb bump, Pb free bump, and Cu Pillar) are focused on finding the metallurgy and structure which has equal or better current carrying capacity than high Pb bump. Most of these studies are based on test vehicles using ENIG surface finish on the substrate. Also, EM structures are employed which do not stress substrate to bump interface with the same amount of current as die to bump interface. It is not clear from these studies if the same conclusions will hold if the substrate pad finish is changed to Cu+SOP. 2010 12th Electronics Packaging Technology Conference

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here for this comparison between SnPb and SnAg bump performance. Besides no significant difference in EM performance for two surface finishes for SnPb bump, it was also observed that the failure primarily occurred on the die side with ENIG substrate finish and on the substrate side for Cu finish. This is shown in Figure 9. With Cu surface finish, current and temperature stressing resulted in Cu3Sn and Cu6Sn5 IMC formation on the substrate side along with significant Cu consumption. The failure was observed at the interface of these two IMC phases. For SnAg with Cu finish, failure was observed on both sides of the joint but only on the UBM side for ENIG finish.

0.1% failure rate at 100K hours

250

ENIG+SOP

Max Current

300

Cu+SOP

0.1% failure rate at 100K hours 800

Max Current

To understand if surface finish and the current level from the substrate side matters, a number of studies were conducted on Flip Chip bump structure. These include testing eutectic SnPb and SnAg bumps using both ENIG and Cu finish and comparing three different bump alloys and Cu pillar for the same surface finish on the substrate. Effect of Substrate Finish Eutectic SnPb bump: Test were conducted on SnPb bump using two different surface finishes on the substrate; Cu+SOP and ENIG+SOP. For both cases the UBM stack of Ti/Cu/Ni was used on the die side with UBM diameter of 110um. The devices were stressed at three different current levels (0.39, 0.47, and 0.61Amps) and two to three device temperatures (125oC, 134oC, and 147oC) with a total of 4 to 5 combinations of current and temperatures. A 12 bump daisy chain EM structure was used for testing with a room temperature resistance of 210mA. Figure 6 shows a comparison of current carrying capacity for two different surface finishes, showing no major difference.

700

ENIG+SOP

600

Cu+SOP

500 400 300 200 100

200

0 100

150

120

130

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150

Temperature (deg C)

100

Figure 7: Comparison of estimated current carrying capacity for SnAg bump with ENIG and Cu surface finish on the substrate.

50 0 100

110

110

120

130

140

150

Temperature (deg C)

0.1% Failure Rate, 100K Hours

Figure 6: Comparison of estimated current carrying capacity for eutectic SnPb bump with ENIG and Cu surface finish on the substrate.

800

SnAg bump: For SnAg bump, tests were conducted on a different device with the same UBM stack-up and diameter as SnPb bump test above. The substrate pad diameter also remained the same as 100um. In this case, the EM structure consisted of 6 bump chain. The tests were performed using 4 combinations of current (0.4 and 0.61Amps) and temperature (130 and 160oC). The effect of substrate surface finish was found to be completely different for SnAg bump with Cu+SOP substrate finish resulting in much better EM performance and much higher current carrying capacity. This is shown in Figure 7. In fact, bumps with Cu+SOP finish on substrate performed so well that the failures were only observed for this combination at the most severe condition even after 10000 hours of testing. On the other hand, bumps with ENIG finish on substrate failed within 5000 hours for all test conditions. Comparing SnAg and SnPb bump for these two substrate surface finishes, SnAg performed much better than SnPb for Cu+SOP finish on the substrate but performed similarly for ENIG finish. This is shown in Figure 8, where maximum current carrying capacity is compared for all four (4) combinations. It should be noted that a similar percent increase in resistance (but different absolute increase) is used

500

SnPb+Cu

700

SnPb+ENIG

600 Max Current

SnAg+Cu SnAg=ENIG

400 300 200 100 0 100 105 110 115 120 125 130 135 140 145 150 Temperature (deg C)

Figure 8: Comparison of estimated current carrying capacity for eutectic SnPb and SnAg bump for ENIG and Cu surface finish on the substrate.

Figure 9: UBM side failure for ENIG (left) and substrate side failure for Cu (right) for SnPb bump. 2010 12th Electronics Packaging Technology Conference

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Effect of Solder Alloy and Cu Pillar To study the bump alloy and copper pillar on EM performance, a head-to-head comparison is being conducted using the same test vehicle. The test vehicle employed a 14.7x14.7mm die with TiW/Cu/Ni UBM of 90um diameter at 150um pitch for solder bumps. For Cu pillar, 50um Cu pillars were plated on TiW/Cu with a base diameter of 90um. The Cu pillars were then plated with 20um SnAg solder to form solder caps. The dice were assembled on 4+2+4 substrate with Cu+SOP finish and 85um solder mask opening. Finally, SAC305 solder balls were attached on the bottom side of the substrate. The complete metallurgy of test structures are shown in Table 1. The test vehicle used for EM testing has multiple EM structures but a 2-bump daisy chain, as shown in Figure 2, was used in this particular case

and to keep the average device temperature as per listed in Table 2. The initial resistance of EM structures for different bumps ranged from 48 to 51milliohms. The failure data reported below is processed using 20% increase in resistance (about 10 milliohm) criteria. At the time of this writing, 5300 – 6300 hours of testing has been completed with failures observed in high Pb, SnPb, SnAg bumps for different stress conditions. Some failures were also observed in Cu pillar but FA on those units show no EM damage on Cu pillar bump structure. A summary of failure data in provided in Table 3. Table 3: Summary of failure data for different bump configurations. Bump Configuration

Table 1: Metallurgical details of 4 flip chip bump configurations used for EM testing Cu Pillar Test Eutectic Pb Free High Pb SnPb SMD Vehicle Cu Pillar + 95/5 63/37 Solder SnAg2.3 20 um Pb/Sn Sn/Pb Bump SnAg Cap 63/37 63/37 SAC305 SAC305 SOP Alloy Sn/Pb Sn/Pb Substrate Cu+SOP Cu+SOP Cu+SOP Pad Finish Substrate Pad Type

SMD

SMD

SMD

BGA Balls SAC305 SAC305 SAC305

SMD

Temperature # Samples # Failed (deg C )

Test Hours Completed

150

8

0

6300

550 700

150 135

8 10

0* 0*

6300 5300

Cu Pillar

700

150

8

0*

6300

SnAg SnAg SnAg

400 400 700

135 150 135

7 8 7

1 2 2

5300 6300 5300

Cu Pillar Cu Pillar Cu Pillar

Cu+SOP

Stress Current (mA) 400

SnAg

700

150

8

8

4050

Eut SnPb Eut SnPb Eut SnPb

400 400 700

135 150 135

8 8 8

2 8 8

5300 2167 1992

Eut SnPb

700

150

8

8

1240

High Pb High Pb

400 400

135 150

8 8

6 8

5300 2200

High Pb High Pb

550 700

135 135

7 8

7 7

2267 3550

High Pb

700

150

8

8

799

SAC305

In order to estimate Black’s equation parameters (n and Ea), a combination of 5 temperature and current conditions were used in this study for Cu Pillar SMD, High Pb, and SnPb bumps and 4 stress conditions were used for SnAg bump test vehicle. The stress conditions are shown in Table 2. Eight (8) samples are on test for each stress condition.

Figure 10 shows a failure distribution comparison for 700mA, 150C condition using lognormal distribution. Other stress conditions show the same trend that high Pb failed first followed by SnPb and SnAg bump. Since no Cu pillar EM failure have occurred so far, the data shows Cu pillar bump performing much better than solder bump options tested here. 99.0 Lognormal High Pb

SnAg

Table 2: Test matrix for EM testing

135 C

0.4 A mps

0.55 Amps

0.7 Amps

SnAg

Cu Pillar SMD SnAg

High Pb Eut SnPb

H igh Pb Eut SnPb

Cumulative % Failed

Temp (deg C) / Current (Amps)

Cu Pillar N SMD

150 C

165 C

Cu Pillar SMD SnAg High Pb

Cu Pillar SMD

Cu Pillar SMD SnAg H igh Pb

Eut SnPb

Eut SnPb

High Pb Eut SnPb

Cu Pillar SMD

L2 RR X - SRM MED

F=8 / S=0

Hi Pb

SnAg L2 RR X - SRM MED

50.0

F=7 / S=1 SnPb

SnPb

L2 RR X - SRM MED

F=8 / S=0

10.0 5.0

1.0 100.0

1000.0

10000.0

Hours to Failure

The resistance of the bump electromigration structure (EM device) is measured using a 4-point measurement technique. The effect of joule heating is also quantified and the oven temperature is set lower to account for joule heating

Figure 10: Failure distribution of High Pb, SnPb, and SnAg bump for 700mA, 150C condition. Surprisingly, high Pb bumps failed significantly earlier than expected. High Pb bumps are in use for a long time now


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and are considered as very robust in terms of electromigration performance. Published data [8] also shows high Pb bump to be performing 12X better than eutectic SnPb bumps.

e-

e-

Figure 11: Failure mode for High Pb bump. Failure on substrate (cathode) side. Failure analysis showed that the failures primarily occurred on the substrate side with electron flow out of substrate (cathode) with crack between the large chunks of Cu-Sn intermetallic and substrate Cu pad, as shown in Figure 11. This was also surprising as published data [8] shows failures on the UBM side. However, there is one big difference in the present study vs. previous experience on high Pb bump, i.e., the surface finish on the substrate. This study was done using Cu SOP substrate finish whereas published data is based on ENIG finish. The UBM stack-up was also different; Ti/Cu/Ni in this study vs. Ti/Ni(V)/Cu in [8]. Further SEM analysis and element mapping revealed the possible reason and failure mechanism for earlier than expected failures on High Pb bump with Cu SOP finish on the substrate. During current/temperature stressing, Pb migrates to anode side and Sn accumulates on the cathode side. This accumulated Sn forms Cu3Sn intermetallic along with Cu consumption, if the finish is thick Cu on the cathode side. Further stressing results in the formation and growth of Cu6Sn5 IMC with additional Cu consumption and all Sn is used up in IMC formation. Finally, voids are formed at Cu6Sn5 and Cu3Sn interface and grow with further current stressing. The same failure mechanism is also observed even with ENIG finish on the substrate if the Cu is too thick on the UBM side. In one study [11], catastrophic failures are reported for high Pb bump soldered to TiW(0.2um)/Cu (0.4um)/ Cu (5um) UBM. The failures primarily occurred on the UBM side in that case due to formation of Cu6Sn5 and Cu3Sn intermetallics. Since only limited amount of Sn is available for a high Pb bump, exposure of this Sn to Cu results in rapid formation and growth of these two intermetallics and complete depletion of Sn from solder. Cathode

e-

Cu6Sn5

eCathode

Figure 12: Failure mode for SnAg bump. Failures on both substrate and UBM side. For SnPb and SnAg bumps in this study, the failures were primarily observed on the substrate side (cathode) for SnPb

and on both sides for SnAg, respectively. The dominant cracking for SnAg, however, was observed on the UBM side, as shown in Figure 12. The data presented here clearly show that EM reliability for a particular solder alloy is a strong function of the type of surface finish on the substrate and UBM stack on the die side. While ENIG finish on the substrate might be better for high Pb bump, it has no significant effect for SnPb eutectic bump and a worse effect for SnAg bump. The trend, however, completely reverses when Cu finish is used on the substrate. Conclusions This paper discusses the factors specific to electromigration testing and flip chip bump & interface metallurgy that can have a significant influence on current carrying capacity estimation. It is shown that joule heating if not accounted accurately can lead to 2 to 3X higher estimation. Similarly, failure criteria selected to analyze EM failure data can have significant influence on current carrying capacity estimation. Data collected on different substrate finishes and solder bump alloys shows that while high Pb solder might perform best for ENIG finish, it performs worst for Cu OSP finish when compared to SnPb and SnAg bump. The surface finish on the substrate also has a significant effect of SnAg solder bump with ENIG showing much worse performance than Cu OSP. Acknowledgments The authors would like to acknowledge Karthikeyan Dhandapani collecting some of the test data reported here and Robert Moody for failure analysis support. Thanks are also due to Shane Loo, Tong Yan Tee, and Bill Batchlor, previously employed at Amkor, in collecting some of the data reported here. References 1. Baozhen Li, Timothy D. Sullivan, Tom C. Lee, Dinesh Badami, “Reliability challenges for copper interconnects,” Microelectronics Reliability 44 (2004) 365–380 2. Christine S. Hau-Riege, “An introduction to Cu electromigration,” Microelectronics Reliability 44 (2004) 195–205 3. Lou Nicholls, Robert Darveaux, Ahmer Syed, Shane Loo, Tong Yan Tee, Thomas A. Wassick, & Bill Batchelor, “Comparative Electromigration Performance of Pb Free Flip Chip Joints with Varying Board Surface Condition,” Proc 59th Electronic Components and Technology Conf, 2009, pp 914-921 4. S. Brandenburg, and S. Yeh, “Electromigration Studies of Flip Chip Bump Solder Joints,” Proc Surface Mount International Conference & Exhibition, San Jose, CA, Aug. 1998, pp. 337-344 5. B. Ebersberger, R. Bauer, and L. Alexa, “Reliability of Lead-Free SnAg Solder Bumps: Influence of Electromigration and Temperature,” Proc 55th Electronic Components and Technology Conf, Lake Buena Vista, FL, May-June. 2005, pp. 1407-1415. 6. B. Ebersberger, and C. Lee, “Cu Pillar Bumps as a LeadFree Drop-In Replacement for Solder-Bumped, Flip-Chip Interconnects,” Proc 58th Electronic Components and 2010 12th Electronics Packaging Technology Conference

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Technology Conf, Lake Buena Vista, FL, May. 2008, pp. 59-66. 7. Yi-Shao Lai, Kuo-Ming Chen, Chin-Li Kao, Chiu-Wen Lee, Ying-Ta Chiu, “Electromigration of Sn–37Pb and Sn–3Ag–1.5Cu/Sn–3Ag–0.5Cu composite flip–chip solder bumps withTi/Ni(V)/Cu under bump metallurgy,” Microelectronics Reliability 47 (2007) 1273–1279 8. J.D. Wu, P.J. Zheng, C.W. Lee, S.C. Hung, J.J. Lee,“A study in flip-chip UBM/bump reliability with effects of SnPb solder composition,” Microelectronics Reliability 46 (2006) 41–52 9. JEP154, “Guideline for Characterizing Solder Bump Electromigration under Constant Current and Temperature Stress,” JEDEC, 2008 10. L. D. Chen, M. L. Huang, S. M. Zhou,“ Effect of Electromigration on Intermetallic Compound Formation in Line-Type Cu/Sn/Cu and Cu/Sn/Ni Interconnects,” Proc 60th Electronic Components and Technology Conf, 2009, pp 176-182 11. J. W. Nah and K. W. Paik, “Mechanism of electromigration-induced failure in the 97Pb–3Snand 37Pb–63Sn composite solder joints,” Journal of Applied Physics, vol 94, number 12, 2003, pp 7560 - 7566


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