Factors Influencing the Leakage Current in Embedded ... - IEEE Xplore

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 3, MARCH 2008

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Factors Influencing the Leakage Current in Embedded SiGe Source/Drain Junctions Eddy Simoen, Mireia Bargallo Gonzalez, Bertrand Vissouvanadin, M. K. Chowdhury, Peter Verheyen, Andriy Hikavyy, H. Bender, Roger Loo, Cor Claeys, Senior Member, IEEE, Vladimir Machkaoutsan, P. Tomasini, S. Thomas, J. P. Lu, J. W. Weijtmans, and R. Wise

Abstract—This paper studies the leakage current components in embedded Si1 −x Gex source/drain (S/D) p+-n junctions, with different Ge contents, varying between 20% and 35%. In addition, the impact of performing a highly doped drain (HDD) implantation before or after the selective epitaxial deposition of in situ highly B-doped S/D layers is investigated. It is shown that the lowest junction leakage is obtained for the post-epi HDD condition, and moreover, for the smallest active area size. As pointed out, this dependence is related with a window-size-dependent strain relaxation, induced by the ion-implantation-related defects. Index Terms—Embedded source/drain (S/D) junctions, ionimplantation-induced defect formation, leakage current, SiGe, strain engineering, strain relaxation.

I. INTRODUCTION TRAIN engineering is nowadays one of the unavoidable enablers for deep-submicrometer CMOS, providing the necessary performance enhancement through the increase of the low-field mobility with strain [1]. In the case of p-channel transistors, the use of embedded Si1−x Gex source/drain (S/D) regions is a viable way to create uniaxial compressive strain in the channel, thereby enhancing the hole mobility [2], [3]. The scalability of this method down to the 22 nm node has been demonstrated [4], but will require an increase of the Ge content (x, in percent) of the S/D regions, which are made by dry etching of the silicon source/drains, a pre-epi cleaning and the selective epitaxial deposition of in situ highly B-doped layers. The higher Ge content should compensate for the shallower junctions necessary for scaled devices and corresponds with a larger lattice parameter, and hence, larger compressive strain in the silicon channel adjacent to it. However, this requires that the epitaxial

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Manuscript received September 12, 2007; revised November 16, 2007. This work was supported in part by the European Union (EU) PULLNANO Project. The review of this paper was arranged by Editor V. Ramgopal Rao. E. Simoen, B. Vissouvanadin, M. K. Chowdhury, P. Verheyen, A. Hikavyy, H. Bender, and R. Loo are with the Interuniversity Microelectronics Centre (IMEC), Leuven B-3001, Belgium (e-mail: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]). M. B. Gonzalez and C. Claeys are with the Interuniversity Microelectronics Centre (IMEC), Leuven B-3001, Belgium. They are also with the Electrical Engineering (EE) Department, Katholieke Universiteit Leuven, Leuven B-3001, Belgium (e-mail: [email protected]; [email protected]). V. Machkaoutsan is with the Advanced Semiconductor Materials (ASM) Belgium, Leuven B-3001, Belgium (e-mail: [email protected]). P. Tomasini and S. Thomas are with the Advanced Semiconductor Materials (ASM) America, Phoenix, AZ 85034 USA (e-mail: [email protected]). J. P. Lu, J. W. Weijtmans, and R. Wise are with the Texas Instruments, Dallas, TX 75243 USA (e-mail: [email protected]). Digital Object Identifier 10.1109/TED.2007.914843

S/D regions remain strained during the complete processing, in order to maintain the performance enhancement. Particularly for S/D regions implanted after selective epitaxy, implantation damage can induce a partial relaxation of the strain [5]–[7]. One concern related with embedded S/D processing is the junction leakage, which is affected by different processing parameters [6]. It has been shown recently that both the area (JA ) and the perimeter (JP ) leakage current increase exponentially with the Ge content [8], [9]. Also, the etch depth and the total epilayer thickness play a role, whereby, usually a higher leakage current is observed for a higher thickness [8], [9]. Another parameter that may impact on the electrical quality of the S/D junctions is the use of a highly doped drain (HDD) implantation, either before or after the epitaxial deposition [10], which gives more flexibility in defining the junction depth. Without HDD, the junction is more or less set by the etch depth, resulting in a SiGe–Si heterojunction, which was shown to have the highest leakage current [8]. On the other hand, especially for the case of HDD after selective epitaxy, one may be concerned with the formation of ion-implantationrelated extended defects [5]–[7], [11]–[15], which can affect the electrical junction properties, when present in the depletion region. The aim of the research is to investigate in more detail the impact of certain process parameters on the leakage current of embedded Si1−x Gex S/D junctions. Particular emphasis is on the implementation of an HDD, while Ge contents in the range of 20–35% are under investigation. It will be shown that the lowest junction leakage is obtained for the post-epi HDD diodes, which, at the same time, exhibit an unusual windowsize dependence, not observed for the no HDD or pre-epi HDD cases. This result is tentatively interpreted in terms of a windowsize-dependent strain relaxation in small active areas, which is related with the HDD ion-implantation-induced extended defects [5]–[7]. II. EXPERIMENTAL Recessed p+-n S/D junctions have been fabricated on 200 mm n-type Cz silicon wafers. Active areas were defined by shallow trench isolation (STI), followed by an n-well implantation. Extension and halo implantations have been performed in all cases. For the pre-epi HDD splits, an implantation of 3 keV B ions at a dose of 3 × 1015 cm−2 was carried out. Dopant activation was achieved before epi growth by a 1050 ◦ C spike anneal. The same conditions were applied for the HDD after epi fabrication. Trenches with a depth of nominally 40 nm

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TABLE I GEOMETRY OF THE STUDIED p +-n JUNCTIONS

Fig. 2. Current density versus P /A ratio at V R = –1 V and 300 K for embedded Si1 −x Gex p +-n junctions with different Ge content. Ref. is a silicon reference wafer. The wafers received an HDD implantation before selective epitaxy and correspond to an etch depth of 40 nm nominally.

III. RESULTS AND DISCUSSION

Fig. 1. Current density versus P /A ratio at V R = –1 V and 300 K for embedded Si1 −x Gex p +-n junctions with different Ge content. The epitaxial layers are in situ highly B-doped and were observed to be strained by Nomarski inspection.

have been etched and refilled selectively with in situ B-doped epitaxial layers with a Ge content of 20%, 30%, or 35% (evaluated by secondary ion mass spectrometry) using an Advanced Semiconductor Materials (ASM) 2000 Epsilon reactor. The layers were capped with a 25 nm Si0.8 Ge0.2 top layer in order to achieve successful nickel-silicidation. In case of the implanted HDD diodes, the junction depth was estimated to be around 80 nm from process simulations. It should be remarked that the no HDD wafers received the 1050 ◦ C spike anneal after epi in order to reactivate the B dopants in the polysilicon gate of the pMOSFETs fabricated on the same wafers, which were passivated during the epitaxial deposition. This yields an improvement of the ION /IOFF characteristics compared with the pre-epi HDD devices. Current–voltage (I–V ) measurements have been performed from −2 to +1 V by an Agilent 4156 Parameter Analyzer at room temperature on devices with different geometry, i.e., area (A) and perimeter (P ) as detailed in Table I. The results shown here are average values from five diodes across the diameter of the wafer, showing a tight distribution (within 20%). The JA and JP are extracted from a graphical representation of I/A versus the P /A ratio, as shown in Fig. 1. The slope yields JP and the intercept JA provided that the leakage current sources are uniformly distributed over the perimeter and area, respectively. It should be remarked that initial results on the pre-epi HDD devices have been published elsewhere [10].

The no HDD diodes exhibit the trends reported in Fig. 1, which are in line with previous results, namely, an increase of both JA and JP with about 2 dec from ∼5.3 × 10−7 to 4.4 × 10−5 A/cm2 and from 4.5 × 10−9 to 1.1 × 10−7 A/cm, respectively. This is in good agreement with the ∼1 dec increase for every 5% increase in Ge content reported earlier [8]. Note, however, that for the 20% 80 nm case, there is a clue of a leakage current density below the straight line fit for the largest P /A ratio, which could point to a window-size effect. A final observation is that from Nomarski inspection after preferential etching, no dislocations were observed, showing that the no HDD films are fully strained. In fact, recent high-resolution X-ray diffraction (HRXRD) investigations of asdeposited selective epitaxial Si0.775 Ge0.225 layers have demonstrated such a window-size effect [16], whereby the relaxation of the strain can increase to 40% for a window size of 0.3 µm2 . Since no dislocations are observed, other relaxation mechanisms should occur: it is suggested that a combination of elastic relaxation and loading effects lead to a strain relaxation and possibly a reduction in the Ge content for smaller window sizes [16]. For the pre-epi HDD junctions, good linearity of the I/A versus P /A characteristics is found in Fig. 2, irrespective of the Ge content. In this case, partial relaxation was revealed by Nomarski microscopy for the 30% and 35% layers (indicated by R in the figure), while only the 20% junctions were fully strained (S). It is clear that the exponential increase of JA or JP with Ge content reported before [8] and also obvious, for the no HDD junctions of Fig. 1 is not retrieved here. This is detailed in Fig. 3, representing the current densities at –1 V in function of the Ge content. Both components reduce when the layer becomes relaxed, going from 20% to 30% Ge. In the case of JA , this suggests that either the misfit dislocations and stacking faults associated with the relaxation are contained in the SiGe layer or do not penetrate in the depletion region at a distance of at least 40 nm [8], [9]. This has been verified by cross-sectional transmission electron microscopy (TEM). The reduction of the area leakage current density with relaxation

SIMOEN et al.: FACTORS INFLUENCING THE LEAKAGE CURRENT IN EMBEDDED SiGe S/D JUNCTIONS

Fig. 3. Area and perimeter current density versus Ge content at V R = −1 V and 300 K for embedded Si1 −x Gex S/D junctions that received a pre-epi HDD. The etch depth is 40 nm nominally.

can then be understood from the fact that not only the compressive stress in the SiGe layer, but also, the tensile strain in the underlying silicon substrate is reduced upon relaxation, as demonstrated by TSUPREM4 simulations. This results in a larger silicon bandgap compared with the fully strained case, and hence, a lower intrinsic carrier concentration ni and a smaller JA , proportional with ni at 300 K [17]. Remark that the increase of JA with the amount of relaxation from 30% to 35% is merely a factor of 2, which is much less than for the strained 20% and 30% Ge layers in Fig. 1. More interestingly, JP also reduces upon strain relaxation. The dominant contribution to JP usually comes from surface state generation, in this case, at the STI (SiO2 )/Si interface. It is well known that strain affects the peripheral leakage component [18]. In fact, it has recently been demonstrated that the density of interface states (or dangling bonds, Ddb ) of p-channel devices increases when approaching the embedded SiGe S/D region [19], [20]. In other words, it is assumed that a higher local compressive stress leads to more broken bonds, and hence, a higher Ddb (and JP ). Strain relaxation should yield the opposite trend. Also note that the ni will be affected in the same way. The order of magnitude of the density of STI/Si interface traps can be estimated from JP as [21], [22] JP = qni W

π 2

σit vth Nit

(1)

where q is the elementary charge, ni the intrinsic carrier concentration, W the depletion width, σit the capture cross section of the interface states, and Nit the corresponding density (in per square centimeter). Assuming reasonable values for the parameters, i.e., W ∼ 100 nm, σit = 10−15 cm2 , Vth = 107 cm/s, and ni = 1012 cm−3 (including the strain-induced bandgap narrowing effect at the silicon interface [17]), we arrive at a value of ∼4 × 1011 cm−2 , corresponding with a JP = 10−8 A/cm for the STI/Si interface. Although this may appear rather large, it is in good agreement with recent literature data [20], extracted from charge pumping for a gate oxide SiO2 /Si interface. The origin of this high interface trap density is the presence of the stress, which can break weak Si–Si bonds at the interface, especially during the thermal budget of the HDD activation anneal. In addition, the presence of implantation-induced point defects may

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Fig. 4. Current density versus P /A ratio at V R = −1 V and 300 K for embedded Si1 −x Gex embedded p +-n junctions with 30% or 35% Ge. The wafers received an HDD implantation after selective epitaxy and correspond to an etch depth of 40 nm nominally.

Fig. 5. TEM cross section of a Si0 . 7 Ge0 . 3 S/D region for a 40 nm etch depth and the HDD implantation performed after the epitaxial deposition. Some {1 1 1} stacking faults are observed near the edges of the epitaxial source/drain regions in the SiGe.

also cause a further creation of dangling bonds at the interface during annealing. Finally, the post-epi HDD results of Fig. 4 demonstrate not only the lowest I/A values for 30% Ge, but also a windowsize effect, whereby lower values are obtained for the smallest active areas, corresponding with the highest P /A ratio (Table I). There is no longer a linear trend, indicating a JA and/or JP that is active area dependent. Since, it is the diode with the largest perimeter deviating from the linear trend, it is believed that the window-size effect in the first instance plays in JP . In analogy to Fig. 3, we postulate that the size effect stems from an active area-dependent relaxation, occurring predominantly for the smaller windows. Note that apparently this occurs for both a relaxed (35%) and a strained case (30%) as judged from Nomarski inspection. It should be mentioned that relaxation in

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[6]

[7] Fig. 6. TEM cross section of a Si0 . 7 Ge0 . 3 S/D region for a 40 nm etch depth and no HDD implantation. No evidence of processing-induced defects is observed in the SiGe.

the smallest active windows (3 µm × 1 µm) cannot be studied by optical inspection. The question rises what the origin could be of this sizedependent relaxation. It is most likely not the epitaxial deposition itself, as it is not clearly found for the no HDD junctions (Fig. 1) [23]. This leaves the HDD implantation as the usual suspect, whereby the strain relaxation could be originating from the less compressive stress levels on the edge of the pattern due to the interaction with the ion-implantation-induced point defects [11]–[15]. TEM investigations have been performed revealing the presence of {1 1 1} stacking faults near the edges of the epitaxial S/D regions of a post-epi HDD pMOSFET (Fig. 5) [23]. On the other hand, no evidence of stacking faults was observed for the no HDD case (Fig. 6). This observation points to the fact that the HDD implantation damage has a marked impact on the windows size dependence of the junction leakage current in small active areas.

[8]

[9]

[10]

[11]

[12] [13]

[14]

IV. CONCLUSION It has been shown that the lowest leakage current for a fixed Ge content can be achieved for embedded Si1−x Gex S/D junctions with a post-epi HDD implantation. Moreover, the leakage current density becomes smaller for window sizes comparable with actual S/D junctions, which is favorable from a transistor OFF-state leakage point of view.

[15] [16]

[17]

REFERENCES [1] M. L. Lee, E. A. Fitzgerald, M. T. Bulsara, M. T. Currie, and A. Lochtefeld, “Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors,” J. Appl. Phys., vol. 97, no. 1, pp. 011101-1–011101-27, Jan. 2005. ¨ urk, “Low temperature [2] S. Gannavaram, N. Pesovic, and M. C. Ozt¨ (≤800 ◦ C) recessed junction selective silicon–germanium source/drain technology for sub-70 nm CMOS,” in IEDM Tech. Dig., Dec. 2000, pp. 437–440. [3] L. Washington, F. Nouri, S. Thirupapuliyur, G. Eneman, P. Verheyen, V. Moroz, L. Smith, X. Xu, M. Kawaguchi, T. Huang, K. Ahmed, M. Balseanu, L.-Q. Xia, M. Shen, Y. Kim, R. Rooyackers, K. De Meyer, and R. Schreutelkamp, “pMOSFET with 200% mobility enhancement induced by multiple stressors,” IEEE Electron Device Lett., vol. 27, no. 6, pp. 511–513, Jun. 2006. [4] G. Eneman, P. Verheyen, R. Rooyackers, F. Nouri, L. Washington, R. Schreutelkamp, V. Moroz, L. Smith, A. De Keersgieter, M. Jurczak, and K. De Meyer, “Scalability of the Si1 −x Gex source/drain technology for the 45-nm technology node and beyond,” IEEE Trans. Electron Devices, vol. 53, no. 7, pp. 1647–1656, Jul. 2006. [5] Y. S. Kim, Y. Shimamune, M. Fukuda, A. Katakami, A. Hatada, K. Kawamura, H. Ohta, T. Sakuma, Y. Hayami, H. Morioka, J. Ogura, T. Minami, N. Tamura, T. Mori, M. Kojima, K. Sukegawa, K. Hashimoto,

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M. Miyajima, S. Satoh, and T. Sugii, “Suppression of defect formation and their impact on short channel effects and drivability of pMOSFET with SiGe source/drain,” in IEDM Tech. Dig., Dec. 2006, pp. 871–874. M. H. Yu, J. H. Li, H. H. Lin, C. H. Chen, K. C. Fu, C. F. Nieh, H. Hisa, Y. M. Sheu, C. W. Tsai, Y. L. Wang, H. Y. Chu, H. C. Cheng, T. L. Lee, S. C. Chen, and M. S. Liang, “Relaxation-free strained SiGe with super anneal for 32 nm high performance PMOS and beyond,” in IEDM Tech. Dig., Dec. 2006, pp. 867–870. J. P. Liu, J. Li, A. See, M. S. Zhou, and L. C. Hsia, “Implant damage and strain relaxation of embedded epitaxial silicon germanium layer on silicon,” Appl. Phys. Lett., vol. 90, pp. 261915-1–261915-3, 2007. E. Simoen, M. B. Gonzalez, G. Eneman, P. Verheyen, A. Benedetti, H. Bender, R. Loo, and C. Claeys, “Germanium content dependence of the leakage current of recessed SiGe source/drain junctions,” J. Mater. Sci.: Mater. Electron., vol. 18, pp. 787–779, 2007. C. Claeys, M. B. Gonzalez, G. Eneman, P. Verheyen, H. Bender, R. Schreutelkamp, L. Washington, F. Nouri, and E. Simoen, “Leakage current control in recessed SiGe source/drain junctions,” J. Electrochem. Soc., vol. 154, no. 9, pp. H814–H821, Sep. 2007. M. B. Gonzalez, M. K. Chowdhury, N. Bhouri, P. Verheyen, F. Leys, O. Richard, R. Loo, C. Claeys, E. Simoen, V. Machkaoutsan, P. Tomasini, S. G. Thomas, J. P. Lu, J. W. Weijtmans, and R. Wise, “Relaxation induced excess leakage current in recessed Si1 −x Gex source/drain junctions,” Electrochem. Soc. Trans., vol. 6, no. 1, pp. 389–396, 2007. R. Hull, J. C. Bean, J. M. Bonar, G. S. Higashi, K. T. Short, H. Temkin, and A. E. White, “Enhanced strain relaxation in Si/Gex Si1 −x /Si heterostructures via point-defect concentrations introduced by ion implantation,” Appl. Phys. Lett., vol. 56, no. 24, pp. 2445–2447, Jun. 1990. N. G. Rudawski, K. N. Siebein, and K. S. Jones, “Effect of uniaxial stress on solid phase epitaxy in patterned Si wafers,” Appl. Phys. Lett., vol. 89, no. 8, pp. 082107-1–082107-3, 2006. C. R. Olson, E. Kuryliw, B. E. Jones, and K. S. Jones, “Effect of stress on the evolution of mask-edge defects in ion-implanted silicon,” J. Vac. Sci. Technol. B, vol. 24, no. 1, pp. 446–449, Jan./Feb. 2006. K. L. Saenger, J. P. de Souza, K. E. Fogel, J. A. Ott, C. Y. Sung, and D. K. Sadana, “A study of trench-edge defect formation in (001) and (011) silicon recrystallized by solid phase epitaxy,” J. Appl. Phys., vol. 101, pp. 024908-1–024908-3, Jan. 2007. N. Burbure, N. G. Rudawski, and K. S. Jones, “Effect of oxide on trench edge defect formation in ion-implanted silicon,” Electrochem. Solid-State Lett., vol. 10, no. 6, pp. H184–H185, Jun. 2007. A. Hikavyy, N. Bhouri, R. Loo, P. Verheyen, F. Clemente, J. Hopkins, R. Trussell, and M. Caymax, “pMOS transistor with embedded SiGe: Elastic and plastic relaxation issues,” presented at the ICSI-5 2007. Marseille, France, May, 20–24. M. B. Gonzalez, E. Simoen, B. Vissouvanadin, N. Thomas, N. Taleb, P. Verheyen, A Hikavyy, F. Leys, O. Richard, R. Loo, C. Claeys, V. Machkaoutsan, P. Tomasini, S. G. Thomas, J. P. Lu, and R. Wise, “Impact of the Ge content and the epitaxial thickness on the bandgap shrinkage induced leakage current of recessed Si1 −x Gex source/drain junctions,” presented at the SAFE. Veldwijk, The Netherlands, Nov. 28– 29, 2007. P. Smeys, P. B. Griffin, Z. U. Rek, I. De Wolf, and K. C. Saraswat, “Influence of process-induced stress on device characteristics and its impact on scaled device performance,” IEEE Trans. Electron Devices, vol. 46, no. 6, pp. 1245–1252, Jun. 1999. C. Y. Cheng, Y. K. Fang, J. C. Hsieh, H. Hsia, Y. M. Sheu, W. T. Lu, W. M. Chen, and S. S. Lin, “Investigation and localization of the SiGe source/drain (S/D) strain-induced defects in pMOSFETs with 45-nm CMOS technology,” IEEE Electron Device Lett., vol. 28, no. 5, pp. 408– 411, May 2007. K. M. Wong, W. K. Chim, K. W. Ang, and Y.-C. Yeo, “Spatial distribution of interface trap density in strained channel transistors using the spread of the differential capacitance characteristics in scanning capacitance microscopy measurements,” Appl. Phys. Lett., vol. 90, no. 15, pp. 153507-1–153507-3, 2007. A. S. Grove and D. J. Fitzgerald, “Surface effects on p-n junctions: Characteristics of surface space–charge regions under non-equilibrium conditions,” Solid-State Electron., no. 9, pp. 783–806, 1966. D. J. Fitzgerald and A. S. Grove, “Surface recombination in semiconductors,” Surf. Sci., vol. 9, pp. 347–369, 1968.

SIMOEN et al.: FACTORS INFLUENCING THE LEAKAGE CURRENT IN EMBEDDED SiGe S/D JUNCTIONS

[23] M. K. Chowdhury, B. Vissouvanadin, M. B. Gonzalez, N. Bhouri, P. Verheyen, A. Hikavyy, O. Richard, J. Geypen, H. Bender, R. Loo, C. Claeys, E. Simoen, V. Machkaoutsan, P. Tomasini, S. G. Thomas, J. P. Lu, J. W. Weijtmans, and R. Wise, “Influence of the window size on the strain relaxation induced leakage current of recessed SiGe source/drain junctions,” Solid State Phenom., vol. 131–133, pp. 95–100, 2008 (presented at the GADEST 2007, Erice, Sicily, Oct.).

Eddy Simoen received the Master’s and Ph.D. degrees in engineering from the University of Gent, Gent, Belgium, in 1980 and 1985, respectively. Since 1986, he has been with the Interuniversity Microelectronics Centre (IMEC), where he is currently a Scientist, and is engaged in the field of low-temperature electronics, and the study of defect and strain engineering in high-mobility and epitaxial substrates and defect studies in germanium. He is the author or coauthor of over 900 papers published in various international journals and conferences, 11 book chapters, and a monograph Radiation Effects in Advanced Semiconductor Devices and Materials (Springer-Verlag, 2002). He was also a coeditor of the book Germanium-Based Technologies: From Materials to Devices (Elsevier, March 2007). His current research interests include the field of device physics and defect engineering in general, with special emphasis on the study of low-frequency noise, low-temperature behavior, and radiation defects in semiconductor components and materials. Dr. Simoen was a coeditor of four International Conference Proceedings and a lecturer at the International Noise School, IMEC, in 1993; at the ENDEASD Workshop in Santorini, Greece, in April 1999; and Stockholm, Sweden, June 2000; and at the EUROSOI Workshop, Leuven, January 2007. Mireia Bargallo Gonzalez received the M.S. degree in physics from the University of Barcelona (UB), Barcelona, Spain. She is currently working toward the Ph.D. degree in defect assessment in semiconductor materials and devices at the Electrical Engineering Department (ESAT), Katholieke Universiteit Leuven (KUL), Leuven, Belgium.

Bertrand Vissouvanadin was born on September 6, 1982, in Port-Bergé, Madagascar. He received the Bachelor’s degree in physics and chemistry and the Master’s degree in applied physics from Reunion Science University, Reunion, France, in 2004 and 2005, respectively, and the Diploma in physics engineering from the National Institute of Applied Sciences (INSA), Toulouse, France, in July 2007. He is currently with the Interuniversity Microelectronics Centre (IMEC), Leuven, Belgium, where he is engaged in electrical characterization of defects in embedded silicon–germanium source/drain junctions. M. K. Chowdhury, photograph and biography not available at the time of publication. Peter Verheyen received the Electr. Eng. degree and the Ph.D. degree from Katholieke Universiteit Leuven, Leuven, Belgium, in 1996 and 2003, respectively. He was a Doctoral Researcher at the Interuniversity Microelectronics Center (IMEC), Leuven, where he is currently a member of the Silicon Process and Device Technology/CMOS Device Research Group. His Ph.D. Topic was: Advanced device architectures based on Strained SiGe layers: physics and technology. He has been engaged in the effect of strain on device performance from a processing and electrical characterization point of view.

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Andriy Hikavyy was born in Chernivtsi, Ukraine. He received the M.S. degree in physical electronics from Chernivtsi State University, Chernivtsi, in 1998, and the Ph.D. degree in applied electronics from Ghent University, Ghent, Belgium, in 2003. From 2003 to 2006, he was a Researcher in the Department of Solid-State Physics, Ghent University. In 2006, he joined the Epitaxy Group of Interuniversity Microelectronics Center (IMEC), and where he is currently working on selective epitaxial growth of Si and SiGe. H. Bender, photograph and biography not available at the time of publication. Roger Loo received the degree in experimental physics and the Ph.D. degree from the RheinischWestfälische technische Hochschule (RWTH) Aachen, Aachen, Germany, in 1993 and 1997, respectively. From November 1991 to March 1993, he was a Scientific Fellow Worker, and from December 1993 to December 1996, as a Research Assistant at the Institute of Thin Films and Ion Technology, Research Centre of Jülich, Jülich, Germany. In January 1997, he joined the Interuniversity Microelectronics Center (IMEC), Leuven, Belgium, where, as a Senior Scientist, he is currently the Head of the Epitaxial deposition (EPI) Group engaged in advanced epitaxial Si/SiGe and III/V processing. He is the author or coauthor of more than 150 papers published in international scientific journals and conference proceedings. Dr. Loo was the recipient of a fellowship from SIEMENS A.G. in Munich, Germany, during December 1993–November 1996. Cor Claeys (M’94–SM’95) was born in Antwerp, Belgium. He received the Electr.-Mech. Eng. masters degree and the Ph.D. degree from Katholieke Universiteit Leuven (KU Leuven), Leuven, Belgium, in 1974 and 1979, respectively. From 1974 to 1984, he was a Research Assistant and a Staff Member of the Electrical Engineering Department (ESAT) Laboratory, KU Leuven, where, since 1990, he has been a Professor. In 1984, he joined the Interuniversity Microelectronics Center (IMEC), Leuven, Belgium, as the Head of the Silicon Processing Group. Since 1990, he has been the Head of the Research Group on radiation effects, cryogenic electronics, and noise studies. He is on the management board of several projects funded by the European Commission. He is also responsible for strategic relations. Since 2000, he has been an electron devices society (EDS) Distinguished Lecture. His current research interests include general silicon technology for ultra-large-scale integration (ULSI), device physics, including low-temperature operation, low-frequency noise phenomena, and radiation effects, and defect engineering and material characterization. He is an Associated Editor for the Journal of the Electrochemical Society. He was a Visiting Professor at Queens University, Belfast, Ireland, U.K., and the University of Calabria, Calabria, Italy. He is the coeditor of a book Low Temperature Electronics and Germanium-Based Technologies: From Materials to Devices and wrote a monograph Radiation Effects in Advanced Semiconductor Materials and Devices. He is the author or coauthor of eight book chapters and more than 700 technical papers and conference contributions related to the aforementioned fields. Prof. Claeys is a Member of the European Material Research Society and a Fellow of the Electrochemical Society. He is also a Member of the European Expert Group on Nanosciences. He was the founder of the IEEE Electron Devices Benelux Chapter, the Chair of the IEEE Benelux Section, an elected AdCom Member of the Electron Devices Society (EDS) during 1999–2005, and the EDS Vice President for Chapters and Regions during 2000–2006. In 2006, he was elected as the EDS President-Elect and become President in 2008. He is the recipient of the IEEE Third Millennium Medal. Within the Electrochemical Society, he has been serving on different committees and was the Chair of the Electronics Division from 2001 to 2003. In 1999, he was elected as an Academician and a Professor of the International Information Academy. In 2004, he received the Electronics Division Award of the Electrochemical Society. He has been involved in the organization of a large number of international conferences and has edited more than 35 proceedings volumes.

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Vladimir Machkaoutsan was born in Ekaterinburg, Russia. He received the M.S. degree from the Ural State University, Ekaterinburg, Russia, in 1998, and the Ph.D. degree from the Institute of Metal Physics, Ekaterinburg, in 2001, both in solid-state physics. Since 2005, he has been a Process Engineer with the Advanced Semiconductor Materials (ASM) Belgium, Leuven, Belgium. His current research interests include SiGe and SiC epitaxial stressors integration in CMOS devices.

S. Thomas, photograph and biography not available at the time of publication.

J. P. Lu, photograph and biography not available at the time of publication.

J. W. Weijtmans, photograph and biography not available at the time of publication.

P. Tomasini, photograph and biography not available at the time of publication.

R. Wise, photograph and biography not available at the time of publication.