We introduce an analytical physics-based model for the transient simulation of anomalous charge loss in flash memo- ries. This model is applied to determine ...
Jpn. J. Appl. Phys. Vol. 41 (2002) pp. 2650–2653 Part 1, No. 4B, April 2002 c 2002 The Japan Society of Applied Physics
Failure Rate Prediction and Accelerated Detection of Anomalous Charge Loss in Flash Memories by Using an Analytical Transient Physics-Based Charge Loss Model Franz S CHULER, Georg T EMPEL, Hanno M ELZNER1 , Michael JACOB2 , Paul H ENDRICKX3 , Dirk W ELLEKENS3 and Jan VAN H OUDT3 Infineon Technologies, affiliated to IMEC, Kapeldreef 75, 3001 Leuven, Belgium 1 Infineon Technologies, Otto-Hahn-Ring, P.O. Box 80 17 60, 81617 Munich, Germany 2 Infineon Technologies, FDA 2-5-1, Toshiba Design Square#201, 247-8585 Sakae-ku, Yokohama, Japan 3 IMEC, Kapeldreef 75, 3001 Leuven, Belgium (Received October 2, 2001; accepted for publication October 29, 2001)
We introduce an analytical physics-based model for the transient simulation of anomalous charge loss in flash memories. This model is applied to determine the bit failure rate and the time-to-failure due to anomalous charge loss. This model can also be used to introduce an accelerated method for the detection of bits suffering from anomalous charge loss. [DOI: 10.1143/JJAP.41.2650] KEYWORDS: anomalous charge loss, SILC, moving bit, data retention, modeling, flash, nonvolatile memory, NVM
1. Introduction
of charge from the floating gate.
It is a well-known problem that floating gate-based nonvolatile memory cells suffer from anomalous charge loss. Various groups and companies have already identified this problem. Different models have been developed to understand and describe this charge loss effect.1–10) In this paper we develop an analytical physical model to describe the transient behavior of anomalous charge loss. The main focus of this model is the application to failure rate prediction and its use for accelerated detection of the bits showing anomalous charge loss.
3. Theory and Modeling
2. Device and Experiments For investigating anomalous charge loss we used uncycled cells of 1 Mb demonstrator circuits based on the High Injection efficiency MOS (HIMOS11) ) approach12) (Fig. 1) and manufactured in a 0.35 µm complementary MOS (CMOS) process at IMEC. The cells are programmed by source-side injection and erased by Fowler-Nordheim (FN) tunneling. Due to the thin tunnel oxide of only 6.5 nm thickness, sufficient numbers of bits showing anomalous charge loss can be obtained. With respect to anomalous charge loss, the critical state of HIMOS11) cells is the low VT (erased) state of around VT ≈ −2.5 V. All cells of the 1 Mb circuits were erased and the devices were stored at room temperature for up to three months. Within this time, the VT ’s were measured several times. Some of the cells showed VT shifts indicating a loss
CG
Write: SSI
x y aligned leakage path
PG FG
S
Most of the existing models assume that anomalous charge loss results from chains of two or more oxide traps—more or less aligned—in the tunnel oxide. Figure 2(a) shows the schematic view of a three-dimensional chain of two traps. Electrons tunnel from the interface to the first trap, then from trap to trap, and finally from the last trap of the chain to the opposite interface. Normally the trap-trap transitions are not in the direction of the field, resulting in a reduced effective field as well as in a tunneling path length longer than the oxide thickness (Fig. 2(b)). In ref. 13 it is shown that the field effect of the nonalignment of the traps can be neglected for all reasonable cases. The complete tunneling path consists of several tunneling steps. According to the WKB approximation the tunnel probability results from the height φt as well as from the width x t of the potential barrier through which electrons have to tunnel. In ref. 13 it is also shown, that the barrier height φt of all traps can be set to be constant (about 2.6 eV) resulting in only an x t dependence of the tunnel probability. A further simplification is considering only the most limiting tunnel step, which is the step with the largest trap-to-trap distance. This results in a very simplified description of the
Erase: FN
z (a)
D
Fig. 1. Schematic view of the HIMOS11) cell approach with source-side injection (SSI) programming and FN erasing. The additional program gate (PG) is characteristic of this type of split gate cell.
xt nonaligned leakage path
dxy
t
neglected steps limiting (b) step
Fig. 2. (a) Schematic view of a three-dimensional distribution of oxide defects. In this diagram two defects form a nonaligned chain, which can be approximated by an aligned chain of two traps. (b) The calculation of the complete tunneling path can be approximated by taking only the tunneling step into account, which limits the leakage current.
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leakage current associated with direct tunneling (DT): Ileak = σ AFN F 3/2 4 3 1 − (1 − F x t /φt ) ∗ , (1) × exp − 2qm φt 3h¯ F 2
where σ denotes the effective cross section (in ref. 13 determined as 10−17 cm2 ), AFN describes the first FN parameter, F(Q FG ) is the vertical field in the tunnel oxide, Q FG is the amount of charge on the floating gate (FG), φt denotes the trap depth, and x t is the trap-trap distance of the limiting tunnel step. The transient behavior of the charge loss can be modeled by Ileak = −
dQ FG dt
(2)
with Q FG F(Q FG ) ≈ . C tot tox
(3)
(4) Ileak = σ AFN F 2 (Q FG ) 3 xt 3 F(Q FG )x t2 4 . 2qm ∗ φt3 − × exp − 3h¯ 2 φt 8 φt2 Thus, using this Taylor expansion, eq. (2) can be written as:
with
σ · AFN · q 2 x ∗φ3 · t exp − 2qm t 2 2 h¯ φt C tot · tox 1 x t2 q c2 = 2qm ∗ φt3 · , 2h¯ C tot tox φt2
c1 =
eq. (7) gives the physical meaning of these parameters. q · n e0 (8a) VT 0 = C tot q VT 1 = − (8b) c2 · C tot t1 =
c2 · exp {−c2 · n e0 } c1
(8c)
3.2 Low field approximation In the case of less charges n e than n et = 1/c2 on the FG, n 2e dominates the charge dependence in eq. (5). The exponential term can be approximated by a linear expansion with respect to n et = 1/c2 : exp {c2 · n e } ≈ exp {c2 · n et } + exp {c2 · n et } (c2 · n e − c2 · n et ) = e · c2 · n e
C tot denotes the total capacitance of the FG and tox is the tunnel oxide thickness. The system of eq. (1) and the differential eq. (2) cannot be solved analytically. However, after Taylor expansion of the exponent in eq. (1), this equation can be rewritten as:
dn e = −c1 · n 2e exp {c2 · n e } dt
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(5)
(6a) (6b)
where n e = Q FG /q describes the number of charges on the FG. To be able to solve this differential equation analytically in the following sections the two cases of high and low fields in the tunnel oxide will be distinguished. 3.1 High field approximation In the case of many charges on the FG, the charge dependence of eq. (5) will be dominated by the exponential term exp {c2 · n e } and n 2e can approximately be assumed as constant n 2et , where n e = 1/c2 denotes the amount of charges on the FG at the transition from the high to the low field case. Using this simplification, eq. (5) can be solved analytically, resulting in 1 c1 high · ln 1 + n e (t) = n e0 − · t , (7) c2 c2 · exp {−c2 · n e0 } with the initial FG charge n e0 = n e (0). In ref. 13 the transient behavior of the threshold voltage VT was approximately described by VT (t) = VT 0 + VT 1 · ln(1 + t/t1 ). Comparison with
(9)
Using eq. (9) the differential eq. (5) can be replaced by dn e = −c1 · c2 · e · n 3e , dt resulting in n low e (t) =
c22
1 , + 2 · c1 · c2 · e · (t − tt )
(10)
(11)
with the transition time tt corresponding to FG charge n et . 3.3 Transition time tt and transition function The transition time tt is defined as the storage time at which the transition value n et = 1/c2 of the FG charge is reached. Using eq. (7), tt can easily be obtained: 1 c1 n et = n e0 − (12) · ln 1 + · tt c2 c2 · exp {−c2 · n e0 } c2 tt = (13) (1 − exp {−c2 · n e0 − 1}) . c1 · e Transition functions such as arctan or tanh can be used to high achieve a smooth transition from n e (t) to n low e (t). 4. Discussion Figure 3 shows transient charge loss data measured at IMEC using cells with a tunnel oxide thickness of only 6.5 nm. The analytical solution is the combination of the high and low field approximations (eqs. (7) and (11), respectively). For the numerical solution the DT equation was solved (eqs. (1) and (2)). Obviously, the numerical solution of the DT formula as well as the analytical description fit the experimental data very well in both the high field and low field regimes. The high field approximation can be used for a worst-case estimation. 5. Failure Rate and Time-to-Failure Prediction After adapting the only free parameter x t for every leaky bit one can use the analytical model for inter- and extrapolation (inset of Fig. 4). In this way, the storage time in which a certain charge loss occurs can be determined for every bit, resulting in the time-to-failure (ttf) for this certain given charge loss. Figure 4 shows the ttf distributions of the most leaky
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high field approximation
-0.5
numerical solution
VT [V]
-1 -1.5 analytical solution
-2 -2.5 10 2
10 6 10 4 Storage Time [s]
10 8
Fig. 3. Measurement and simulation of transient charge loss for the 1st , 10th and 100th most leaky bit of a 1 Mb demonstrator device. Both the analytical solutions (combinations of high and low field solutions) (dashed lines) as well as the numerical solutions of eq. (1) and eq. (2) (solid lines) fit the experimental data nearly perfectly. The high field approximation (dotted lines) can be used for a worst-case estimation.
0 0
Bit Failure Rate
VT [V]
failure rate prediction
-1 -1 -2 -2 -3
10-5 20% 40% 60% charge loss 80%
2 4 10 6 10 8 -3 10 10 6 4 10 8 Sto Storage Tim 10 e [s] 10ra2 ge10Time Sto ra ge Tim e [s]
ttf prediction
Fig. 5. Insufficient correlation between disturb and anomalous charge loss bits.15)
#MB (accumulated)
-3 10 0
10
5
drain disturb retention
10
10
10
4
3
2
10
10-6 105
106
107 ttf [s]
108
109
Fig. 4. After transient simulation of every leaky bit, the time-to-failure (ttf) for every bit can be obtained. The resulting ttf distribution can be used for failure rate prediction as well as for ttf prediction.
bits in a 1 Mb demonstrator device for different charge losses. These distributions can be used either for determining the mean time until a bit failure occurs (ttf prediction) or for determining the bit failure rate for a given guarantee time, normally 10 years for automotive specifications (failure rate prediction). 6. Accelerated Detection of Anomalous Charge Loss Since for commercial products thick (tox ≈ 10 nm) high quality oxides (Dot < 10−15 cm−3 ) are used, the resulting leakage currents are very low (< 10−22 A), which results in the need for extremely long storage times to detect leaky bits which could fail within 10 years. Thus, we attempted to accelerate the charge loss by applying external voltages (disturb) and increasing the internal field by over-erasing. 6.1 Acceleration by disturb For acceleration of the charge loss we increased the internal field in the tunnel oxide by applying an external drain voltage Vd . During a short storage time we measured the VT shift of all cells of a 1 Mb demonstrator, which had already been in-
0
10
1
10
2
10
3
10
4
10
5
#P/E cycles Fig. 6. Different cycling behaviors of disturb and anomalous charge loss bits.15)
vestigated with respect to anomalous charge loss. Figure 5 shows that there is no correlation of the VT shifts resulting from unbiased storage for a long time (x-axis) and those resulting from short-time disturb experiments (y-axis). Thus, disturb experiments involving the application of external voltages cannot be used for a reliable acceleration of anomalous charge loss. A further indication of the different natures of disturb bits and anomalous charge loss bits is given in Fig. 6. Comparing the number of leaky bits in the cases of the disturb condition and the unbiased retention condition depending on the number of program and erase cycles, completely different cycle dependences of disturb bits and anomalous charge loss bits become obvious. Thus, an accelerated determination of anomalous charge loss bits after cycling by disturb experiments would significantly overestimate the number of leaky bits. Thus, disturb measurements cannot be used for accelerated anomalous charge loss detection. 6.2 Acceleration by over-erasing To reduce the increase in field, we replaced the disturb conditions by over-erasure of the cells (upper inset of Fig. 7), resulting in VT ’s in the range of −4 V to −5 V instead of ap-
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VT
40%
60%
80%
0
10-6
VT [V]
Bit Failure Rate
20% charge loss
-2
-4
10-7 104
7. Conclusions
6 -6
105
10 ttf[s]
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steeper ttf distributions in the case of the accelerated measurement, we lose accuracy and this results in a correlation band. This band can be used to transfer the ttf’s determined by the accelerated test into the expected ttf’s for normal storage conditions. From the numerical point of view, eq. (8c) can be used to estimate the acceleration which is determined by the parameter t1 , depending on the initial amount of charge n e0 on the FG.
#
erased erasedVT: VT: normal: -2.5V normal: -2.5V overerased overerased: : -4V -4V- --5V -5V
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1
10 2
10 4
10 6
10 8
Storage Time [s]
Fig. 7. Transient simulation of over-erased cells (inset) and their time-to-failure distributions.
Fig. 8. Correlation of normally and accelerated measured anomalous charge loss bits. An acceleration of factor of about 10–30 can be obtained by over-erasing.
proximately −2.5 V. If we apply the same procedure to determine the time-to-failure as explained before, we obtain the ttf distributions plotted in Fig. 7. Using the same demonstrator device, we first determined the time-to-failure distributions starting with normal erased VT ’s. After that we over-erased all cells and determined the ttf distribution again. Figure 8 shows the correlation of the timeto-failure determined by normal unbiased retention tests (xaxis) and the time-to-failure determined by accelerated testing by over-erasing (y-axis). Obviously, an acceleration of a factor of about 10–30 can be achieved. However, due to the
We introduced a new analytical transient charge loss model which can be used for failure rate prediction as well as for the evaluation of accelerated anomalous charge loss detection by over-erasing. We further demonstrated that disturb experiments cannot be used for accelerated detection of bits which show anomalous charge loss.
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