floating-island thin film transistor leakage caused by ...

FLOATING-ISLAND THIN FILM TRANSISTOR LEAKAGE CAUSED BY PROCESS STEP REDUCTION *Takatoshi Tsujimura, *Osamu Tokuhiro, *Mitsuo Morooka, *Takashi Miyamoto, Kohichi Miwa, *Yuhsuke Yoshimura, **Paul Andry and **Frank Libsch

ABSTRACT The leakage mechanism for a top gate TFT (thin film transistor) produced using the fewest process steps in the industry is analyzed in order to achieve a high contrast LCD (liquid crystal display). Using a T-shaped TFT structure, the OFF and ON channel lengths are defined independently, so that the leakage can be reduced with no ON current decrease. Index Terms—

Liquid crystal displays, Thin film transistors, Leakage currents I. INTRODUCTION Because LCDs (liquid crystal displays) are used almost exclusively for notebook computer screens, and because of their reduced footprint compared with CRT desktop monitors, the overall demand for LCDs is increasing rapidly. Due to the large number of process steps, typically ranging from 50 to 70, the price of TFT LCD panels is still too high to replace all CRTs. Bottom gate TFTs are usually used as the switching elements in active-matrix TFT LCD fabrication. The bottom gate structure has the gate electrode under gate insulator, and has the advantage of larger ON current than top gate TFT, because the a-Si (amorphous silicon) channel is not damaged by the plasma radiation during gate insulator deposition, but the structure has the disadvantage of a more complicated process requiring 5 to 7 PEP (photo-engraving process) steps. [1][2] To lower the cost of TFT fabrication, Nishikawa et al. has introduced a new way of TFT processing that uses a top gate TFT in which the gate electrode is defined on top of the gate insulator. According to this process denoted “3MSTFT”(Fig.1) [3][4][5], the gate insulator is etched using gate line photo resist as a mask. The 3MS-TFT process makes it possible to produce a TFT array with 3PEPs in the case of small panels up to about 10 inches which do not require low resistance data bus lines. In order to fabricate TFT LCD panels over 10 inches, one more PEP step is necessary to build low resistance data bus line. One major caveat of the 3MS-TFT is its large leakage The authors belong to, * LCD Technical Development, Display Business Unit, IBM Yamato Laboratory, IBM Japan ** IBM Watson Research Center, IBM Corporation

current which deteriorates the charge retention performance of liquid crystal cell. As a result the TFT size cannot be made large enough to drive pixel against the gate line delay. In this paper, the leakage current mechanism caused by 3MS-TFT structure is analyzed and the leakage current is reduced by employing a novel TFT design to achieve, for the first time, the fabrication of a 14.1 inch XGA TFT LCD panel with fewest process steps in the industry.

Light Shield Glass

1PEP Data 2PEP

metal Data

3PEP Gate

metal

Gate a-Si

Fig.1 3MS-TFT structure

II. TFT STRUCTURE COMPARISON A. Conventional TFT structures Because cost reduction is one of the most important issues for TFT LCD production, considerable research and development has been reported in this area. In the early stage, when the TFT LCD operation first began to be reported, the number of PEP steps required for array fabrication was greater than 8. [6][7] After it was demonstrated that the light shielding layer on TFT is not necessary if a black matrix is built on the color filter side, and that the back-channel cut type TFT [7] process eliminates the etch stopper formation step, the typical number of PEP steps was reduced to 7 or 8. [8][9][10][11][12] Process step reduction leads to investment cost reduction, which results in lower depreciation cost, and to lower material cost, since each PEP step requires expensive photo resist, developer rinse and stripper rinse. Various strategies have been reported in the area of PEP reduction, most of which result in a final number of 5 or more PEP steps [13]. Reduction of the process to 4PEPs or less has been reported by Ban [14], Ono [15], Glueck [16], Calster [17] and Nishikawa [3][4][5], but Glueck and Calster’s paper does not count the “non-critical” PEP steps that could be patterned

Takatoshi Tsujimura, Osamu Tokuhiro, Mitsuo Morooka, Takashi Miyamoto, Kohichi Miwa, Yuhsuke Yoshimura, Paul Andry and Frank Libsch, "FLOATINGISLAND THIN FILM TRANSISTOR LEAKAGE CAUSED BY PROCESS STEP REDUCTION", IEEE Transactions on Electron Devices, Vol.49, No.4, p.576 (2002)

without photo etching process in the future and the PEP steps are practically equal to 6 or 7 PEPs. Ban and Ono’s ideas are based on the ITO data bus line. Since ITO has about 1000 times larger resistivity than the typical metal used for TFT bus lines like aluminum, the data line pulse is degraded at the opposite side of the data driver in the screen and this creates gray level error if the panel size and the resolution is large. In fact, Ban’s paper describes the limitation of the ITO data bus line and shows that operation is limited to a maximum 11 inch SVGA panel. Oritsuki deduced the minimum number of PEP steps required by taking into account how many thin film layers could be etched at once [18]. He claims 4 PEP is the minimum for a bottom gate TFT array, and 3 PEP is the minimum for top gate TFT array. In this assumption, a light shielding layer pattern was not counted for the top gate case, so the practical minimum PEP steps required for large-area TFT LCD production would be 4PEP for both bottom gate and top gate TFTs. Recently, novel patterning method using a “Half-tone” process has been reported. (Fig.2)[19][20] This process makes use of a photo mask with a narrowly-spaced grid to deliver intermediate-level exposure to the photo resist resulting in three levels of photo resist thickness, that is, zero, intermediate and full thickness. After patterning the underlying film using the zero thickness photo resist pattern, the photo resist is thinned by O 2 plasma ashing to decrease the intermediate-region photo resist thickness to zero, but leaving a portion of the full thickness region photo resist to define the pattern of the next etching step. This half-tone process is very difficult for manufacturing for the following reasons: (1) The photo resist thickness distribution across a given substrate is usually poor, due to the large substrate size for TFT LCD fabrication (substrate dimensions typically range from 300 cm to 1000 cm). (2) The ashing rate uniformity of photo resist is usually poor. (3) The photo mask precision for the grid is poor because a pattern spacing below the minimum design rule is necessary to make the half-tone grid. Because of these processing difficulties, the half-tone process has a disadvantage in the area of production yield.

1PEP 2PEP

Gate

Half-tone exposure

Photo resist Data metal n+ a-Si a-Si Gate insulator

Ashing+Etching

3PEP

Passivation

4PEP

ITO (Pixel)

Fig.2 Half-tone 4PEP process

To overcome these problems, we adopted a top gate TFT array process. The bottom gate TFT process requires a silicon nitride passivation layer to cover the TFTs and metal lines in order to prevent back-channel effects caused by ionic contamination in the liquid crystal [21]. Because the gate electrode is on top of the gate insulator / aSi stack in the top gate TFT, any ionic contamination in the liquid crystal does not influence the channel, so the passivation layer is not required. Though top gate TFT is attractive to avoid back channel leakage, 4PEP TFT has not been used for large area LCD monitor because of the poor pixel charge retention performance. It is important to analyze the leakage mechanism of 4PEP top gate TFT to apply to large area monitors. B. Structural weak point of 4PEP top gate TFT in leakage current Fig.1 shows the 3MS-TFT that has been reported previously by Nishikawa et al. Because this structure does not allow for a low resistance data line, and because of the large data bus line pulse delay, TFTs far from the data driver cannot adequately charge the pixel capacitor when the panel size is larger than 10 inches.


1PEP 2PEP

Gate

Half-tone exposure

Photo resist Data metal n+ a-Si a-Si Gate insulator

Ashing+Etching

3PEP

Passivation

4PEP

ITO (Pixel)

Fig.3 4PEP top gate TFT structure

5) The Mo/Al/Mo is etched with etchant composed of a mixture of phosphoric acid, acetic acid, nitric acid and water (PAN etch). 6) Silicon nitride gate insulator and amorphous silicon are etched by plasma etch (PE) or RIE using the gate line photo resist as etching mask with selectivity to MoW source/drain metal. 7) ITO is deposited and patterned to form the pixel electrode. To improve the data line delay, our 4PEP structure employs MoW for the drain / source electrodes. The MoW resistivity of ~15 µΩ-cm is sufficiently low to allow pixel charging to the correct gray level. The 4PEP TFTs made with this process flow may have large ON currents because the top gate TFT channel length may be made quite short, about 5 µm, but they may also have very large OFF currents as shown in Fig.5. In order to operate an LCD panel with TFT leakage this large, a large storage capacitor would be necessary, but to charge such a capacitor, the TFT width would have to be increased resulting in the aperture ratio decrease.

Light Shield metal deposition Light Shield PEP (1PEP) Light Shield Etching Insulator deposition Signal Line metal deposition Signal Line PEP (2PEP) Signal Line Etching a-Si\Gate Insulator deposition Gate Line PEP (3PEP) Gate Line Etching a-Si\Gate Insulator Island Etching ITO deposition ITO PEP (4PEP) ITO Etching

1) The MoW electrode is defined and etched by CDE (Chemical Dry Etcher) to produce a smooth tapered surface 2) After etching, the MoW is exposed to PH3 / H2 plasma to supply P atoms to the MoW electrode surface. (Plasma doping) 3) Immediately after plasma doping, the amorphous silicon layer is deposited without interruption to assure a good contact. Phosphorus atoms on the MoW electrode are incorporated into the amorphous silicon / MoW interface region and take the place of the n+ doping layer to achieve an ohmic contact. Due to the gentle taper shape of MoW source and drain electrode, electrons can be injected from phosphor doping region to the amorphous silicon very easily. 4) Silicon nitride gate insulator is deposited on top of the amorphous silicon without interruption and the substrate is transferred to sputtering equipment to deposit Mo/Al/Mo data metal. Photo resist is coated on Mo/Al/Mo metal, exposed and developed to form gate line etching mask.

Drain current [A]

Fig.3 shows our 4PEP top gate TFT structure which includes an additional data metal PEP to allow fabrication of large panel sizes. Data metal is made of MoW (Molybdenum Tungsten) alloy. The process flow is shown below. (Fig.4)

10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 -10

Conventional TFT

-5

0

10 15 5 Gate voltage [V]

20

Fig.5 Conventional 4PEP top gate TFT Characteristics(Channel width:10µm, Channel length:8µm,Vds=15V)

For example, if the diagonal size of an LCD panel is D and the resolution is Mh (horizontal resolution) × Mv (vertical resolution),

Mh = Mv ×

4 (B.1) 3

The subpixel size x (horizontal size) and y (vertical size) will be,

4 D (B.2) × 5 3M h 3 D (B.3) y= × 5 Mv

x=

The capacitance of the liquid crystal is,

C LC =

ε 0 ε LC d LC

xy

(B.4)

( ε o :permittivity of vacuum, ε LC :dielectric constant of liquid crystal, d LC : gap distance of liquid crystal cell)


When the ratio of liquid crystal and storage capacitor is defined as

γ =

C LC and the parasitic capacitance like CS

Leakage path

between pixel and signal bus line is negligible compared with Cs , the capacitance to be charged by a TFT is approximately, (B.5) C all ≅ C S + C LC = C LC (1 / γ + 1) On the other hand, the pixel voltage shift allowed is approximately equal to one LSB (least significant bit) and can be written as,

Vallowed =

Va N

Gate Drain Gate insulator/a-Si

(Va: Signal line amplitude, N: Number of gray scales) Amount of charge to be supplied by a TFT to Call can be written using (B.6) as,

I OFF max

C all 36ε o ε LC D 2 (1 / γ + 1) = = ≈ 2 × 10 −12 [ A] 2 TN 100d LC TNM v (B.8) −4

(Mv=768, N=256, d LC = 5 × 10 [cm] ,

D = 14 × 2.54[cm] ,γ = 1.0, ε LC =10 was used.) With this rough calculation, TFT OFF current lower than

2 × 10 −12 [ A] must be achieved to apply to TFT LCD. In the case of display sizes larger than 10 inches, the gate line delay problem would result in a lower pixel charging level far from the gate driver side, because the large pixel capacitor required by the leakage constraint cannot be charged perfectly. Thus, leakage path detection and reduction of 4PEP TFT structure is important to apply for large area monitor. III. LEAKAGE PATH DETECTION In order to shed light on the cause of the leakage related to the 4PEP top gate structure, the OBIC (Optical Beam Induced Current) method measurement was applied. OBIC uses a laser beam scanned across the driving TFT to detect a leakage path. When the spot irradiated by the laser beam is not within the leakage path, induced electron-hole pairs quickly recombine, but when the spot irradiated is within the leakage path, electrons flow to the drain electrode and are detected. Fig.6 shows the OBIC image of a 4PEP top gate TFT. The OBIC current is detected in amorphous silicon around gate electrode, and we denote this region as the “Floating-Island” region.

Fig.6 PEP top gate TFT OBIC image

To prove that the Floating-Island region is the cause of the leakage path, boron atom doping was applied to the TFT. Since the channel region is protected by gate electrode, no boron is implanted into the channel. Conversely, since the Floating-Island region is not covered by the gate metal, boron may be effectively implanted into the Floating-Island amorphous silicon region; thus selective doping into Floating-Island region is possible. It is well known that PECVD-deposited amorphous silicon shows weakly n-type behavior as the dangling bond behaves as a donor. Boron doping of amorphous silicon acts to compensate this, and increases the OFF resistance along with threshold voltage. As shown in Fig.7, with 1018-1019[atoms/cm3] boron doping, the Floating-Island conductance is decreased. 10-05 17 3 10-06 10 [atoms/cm ] 10-07 Initial 10-08 -09 10 1021[atoms/cm3] 10-10 10-11 1018[atoms/cm3] 10-12 1019[atoms/cm3] 10-13 -14 10 10-15 -10 -5 0 5 10 15 20 25 Gate voltage [V] Drain current [A]

can be allowed) With (B.7) (B.2), (B.3), (B.4), (B.5), (B.6), maximum leakage current that is not visible by human eye can be calculated as,

ITO

Leak path

(B.6)

Va (B.7) Q = I OFF max T = C all N (T: one frame period, I OFF max :Maximum OFF current that

Source

Fig.7 Leakage current suppression with Boron doping (W/L=10/8µm,Vds=15V)

The increase in leakage current in Fig.7 does not go with the trend and could be due to the damage by ion implantation. The 1018-1019[atoms/cm3] data further demonstrates that the 4PEP top gate leakage path exists in Floating-Island region. IV. DISCUSSION The Floating-Island region has unique features, 1) Almost no electrode is attached to the amorphous silicon except some influence by the drain electrode at the drain edge 2) Almost no electrode is indirectly attached to amorphous silicon via gate insulator except for some small influence from the gate electrode at the gate edge


B. Floating Island region consideration Most of the area in amorphous silicon is attached to electrode or indirectly attached to amorphous silicon via gate insulator, so its potential is dominated by the gate electrode. As negative voltage is applied to gate electrode in the OFF state, the amorphous silicon region whose potential is dominated by the gate is in electron depletion, so the amorphous silicon conductance is very small. In the Floating Island case, the area close to gate electrode has gate field influence and the area close to drain electrode has drain electrode influence, but a significant portion of the Floating-Island region has less influence from these electrodes and is close to the floating situation. When the edge connected to the gate line is large compared with the edge connected to the drain electrode, the Floating-Island region potential will mainly be governed by the gate electrode. Since the gate electrode potential is negative in the OFF state, the leakage will be decreased. However, when the edge connected to the drain electrode is large compared with the edge connected to the gate line, the Floating-Island region potential will mainly be governed by the drain electrode. Since the drain electrode potential is positive and larger than threshold voltage in most cases, the leakage will be increased. To suppress leakage that is caused by these features, processing and designing analysis were carried out. V. LEAK CURRENT REDUCTION WITH AMORPHOUS SILICON EDGE TERMINATION

Since the amorphous silicon edge in the Floating-Island region is not covered by insulator, dangling bonds may attract positive charge to switch on the amorphous silicon conduction. To terminate the dangling bond, O 2 annealing[22] was employed. As shown in Fig.8, the TFT after O 2 annealing shows more than an order of magnitude improvement compared with the reference in Fig.5. It is supposed that the positive charge due to the dangling bond is precluded by O 2 annealing, as the sample without floating island edge does not show leakage reduction by O 2 annealing. Though O 2 annealing works to reduce one order of leakage, the leakage value is not still low enough for large monitors, then new TFT design was adopted for low leakage as discussed in the next section.

Drain current [A]

A. Floating Island edge consideration The floating island edge is not covered with any insulator and is directly exposed to polyimide and liquid crystal materials. The dangling bond at the edge of the amorphous silicon may have positive charge which “turns on” the amorphous silicon conduction, so the floating-island edge amorphous silicon should be terminated by some means.

10-05 10-06 10-07 10-08 10-09 10-10 10-11 10-12 10-13 10-14 10-15 -10

-5

0

5 10 15 Gate voltage [V]

20

25

Fig.8 Leakage current suppression due to O2 annealing(Channel width/ length=40/6mm,Vds=15V)

VI. T-SHAPED TFT TO REDUCE FLOATING-ISLAND LEAK CURRENT A. Channel length dependence The Floating-Island region amorphous silicon is almost floating but somehow influenced by the gate electrode and drain electrode. Since the gate electrode potential is negative in the OFF state, it will not increase the leakage current. The drain electrode is positive however, and since it is larger than the threshold voltage it is possible for it to affect the FloatingIsland region causing leakage. This phenomenon is similar to the back-channel effect, and the Ids-Vg curve shows a bump in the subthreshold slope similar to that seen in back-channel effect leakage [22]. To suppress this leakage, the channel length (L) dependence was measured as shown in Fig.9. With larger channel length, the OFF current is improved and the back-channel-like leakage is reduced. 10-05 10-06 10-07 10-08 L=3.8 10-09 10-10 L=8.6 10-11 -12 10 10-13 L=18.7 10-14 L=28.8 -15 10 -10 -5 0 5 10 15 20 25 Gate voltage [V] Drain current [A]

3) The amorphous silicon edge is not terminated by any film and is directly exposed to liquid crystal Leakage mechanism due to the floating island should be investigated taking these features into consideration.

Fig.9 Channel length dependence (Channel width/ length=10/8µm,Vds=15V)

B. Simulation The Floating-Island leakage was simulated with the ATLAS device simulator to verify the assumptions made in the discussion above. As shown in Fig.10a-c, the potential at the Floating-Island edge is decreased as the channel length is increased. Thus, when the Floating-Island edge is long, the gate electrode potential influence dominates over the drain such that a low potential region is formed on the FloatingIsland edge creating high resistance leakage path. This high


resistance region decreases the conduction between source and drain in the OFF state.

Fig.10a Potential distribution of 4PEP TFT (Short channel length)

C. T-shaped TFT structure Although the OFF current can be reduced by increasing L, the ON current is also reduced because the channel length for both currents is equal in this TFT structure. For the introduction of process-step-reduced top gate structure TFT for wide-screen high-resolution display, it is inevitable to apply idea to achieve both low off current as shown in (B.8) and high on characteristics with the existence of floating-island region. The solution to this problem was to design a TFT structure where the ON and OFF (edge-defined) channel lengths would be different. Fig.12 shows the conventional TFT equipped with the same ON channel length (Lon) and OFF channel length (Loff) and a T-shaped TFT to define ON channel length and OFF channel length independently. The feature of TFT that Loff is greater than Lon has been already reported [23], however Tshaped TFT provides higher Loff / Lon ratio that is sufficient enough to create low leakage current along with good ON characteristics.

LOFF Fig.10b Potential distribution of 4PEP top gate TFT (Medium channel length)

LOFF LON

LON

Fig.12 Conventional TFT(Left) and T-shaped TFT(Right)

With this structure, Loff can be enlarged without sacrificing the ON current. As shown in Fig.13, low OFF current along with high ON current is achieved with T-shaped structure.

Gate electrode

10-5

-6

10-6

10-7

10-7

current

10-8 -9

10

-10

10

Conventional TFT

10-12 -13

10

10-14

Floating Island region

102/cm3

-9

10

10-10

T-shaped TFT

10-12 -13

10

-14

10

-15

10-15

10 -10

Gate insulator

-8

10

10-11

10-11

Drain

Fig.11 shows the cross section of the simulation result. As expected, the charges exist at the sidewall farthest away from gate electrode.

-5

10

10

Drain current [A]

Fig.10c Potential distribution of 4PEP top gate TFT (Long channel length)

-5

0

5

10

15

Gate voltage [V]

20

25

-10

-5

0

5

10

15

20

25

Gate voltage [V]

Fig.13 OFF current improvement with T-shaped TFT(Channel width/ length=40/6µm,Vds=15V)

VII. RELIABILITY TEST 1014Fig.14 /cm3 shows the maximum OFF gate voltage needed to 108/cm3 10 Electron Concentration 10 /cm3 1012/cm3suppress retention-related white haze after bias temperature Amorphous Silicon testing. Topgate TFT with no O2 plasma treatment and with conventional structure that has the same Lon and Loff length shows white haze from the beginning with this test because of Glass Substrate large leakage current as shown in Fig.5. In the case of LCD module with bottom gate TFT without passivation, white haze appears in 100 hours. But the voltage Fig.11 Charge concentration distribution (simulation) with T-shaped oxidized topgate TFT shows almost no degradation without using a final passivation SiNx layer in the top gate 4PEP TFT process. It indicates that the leakage

106/cm3


improved by T-shaped TFT and O2 annealing is not sufficiently large be visible in the 16.7 msec frame period. This result effectively demonstrates that the passivation SiNx is not required to operate the 4PEP top gate TFT LCD.

processing support , Mr.A.Terukina and Mr.H.Nakasima for design support, and Mr. H.Suzuki and Mr.T.Ueki for their valuable advice.

OFF gate voltage driving margin change [V]

XI. REFERENCE + 4 + 2 0

Topgate TFT w/o

[1]

Bottom gate TFT w/o Passivation

[2] [3] [4] [5]

2 4

0

[6]

100

200 Time [hours]

300 [7]

Fig.14 OFF gate voltage margin transition (LCD module driving in 70C chamber, Initial=0V)

[8]

VIII. RESULT

[9]

By employing Floating-Island edge oxidation with O 2 anneal, and a T-shaped TFT to reduce leakage current, a 14.1 inch XGA (1024X768 pixels) TFT LCD was successfully produced. A photo of the panel is shown in Fig.15.

[10]

[11]

[12]

[13]

[14]

[15] [16] Fig.15 14.1 inch TFT LCD panel with 4PEP top gate TFT

[17]

IX. CONCLUSION OFF state leakage in the 4PEP top gate TFT is caused by the existence of Floating Island. Oxygen annealing is effective in terminating the amorphous silicon dangling bonds. In order to achieve a low OFF current without sacrificing ON current, a T-shaped TFT has been shown to be advantageous because the ON channel length and the OFF channel length may be independently defined. Using these process and design improvements, a 14.1 inch XGA TFT-LCD was successfully produced using the fewest number of process steps in the industry to date.

[18]

[19] [20]

[21]

[22]

X. ACKNOWLEDGEMENTS

Miura et al., International Workshop on Active-Matrix Liquid-Crystal Displays 95 (1995) p.75 Y.Yamaguchi et al., Society for Information Display’98 (1998) p.30 Nikkei-Sangyo Newspaper Sep/27/1994 R.Nishikawa et al., Denshi Zairyou’95 p.82 (1995) N.Koma et al., “Development of a Simple Process to Fabricate High-Quality TFT-LCDs”, Society for Information Display ’96(1996), p.558 F.Funada et al., “An Amorphous-Si TFT Addressed 3.2-in. Full-Color LCD”, Society for Information Display86 digest (1986), p.293 Sakai et al., “A COLOR LC PANEL USING A VERY THIN FILM TRANSISTOR (V-TFT)”, International Display Research Conference85 digest (1985), p.30 Sugata et al., “A TFT-Addressed Liquid Crystal Color Display”, Japan Display’83 (1983), p.210 M.Takeda et al., “12.5” LCD Addressed by a-Si TFTs Employing Redundancy Technology”, Japan Display86 (1986), p.204 M.Akiyama et al., “An Active-Matrix LCD with Integrated Driver Circuits Using a-Si TFTs”, Japan Display '86(1986), p.212 Sunata et al., “A LARGE AREA, HIGH RESOLVING POWER, ACTIVE MATRIX COLOR LCD ADDRESSED BY A-SI TFTS”, International Display Research Conference ’85 (1985), p.18 C.W.Kim et al., “Pure Al and Al-Alloy Gate-Line Processes in TFT-LCDs”, Society for Information Display ’96 (1996), p.337 P.Fryer et al., “A SIX-MASK TFT-LCD Process Using Copper-Gate Metallurgy”, Society for Information Display ’96 (1996), p.333 A.Ban et al., “A Simplified Process for SVGA TFT-LCDs with Single-Layered ITO Source Bus-Lines”, Society for Information Display ’96 (1996), p.93 K.Ono et al., “A Simplified 4 Photo-Mask Process for 24cm Diagonal TFT-LCDs”, Asia Display’95 (1995), p.693 J.Glueck et al., “A 14-in.-Diagonal a-Si TFT-AMLCD for PAL-TV”, Society for Information Display’94 (1994), p.263 A.V.Calster et al., “A SIMPLIFIED 3-STEP FABRICATION SCHEME FOR HIGH MOBILITY AMLCD PANELS”, International Display Research Conference ’94 (1994), p.289 Oritsuki, “Geometrical study of the staggered type aSi TFTs structure for low cost AMLCDs process”, International Display Research Conference ’94 (1994), p.432 C.W.Han et al., “A TFT manufactured by 4 masks process with new photolithography”, Asia Display’98 (1998), p.1109 C.W.Kim et al., “A Novel Four-Mask-Count Process Architecture for TFT-LCDs”, Society for Information Display’00 (2000), p.1006 Nishida et al., “Simulations on back gate effects of a-Si TFT off-current under illumination”, Journal of NonCrystalline Solids (1993), p.755 S.Yamakawa(Sharp) et al.,"The Effect of Plasma Treatment on the Off-Current Characteristics of a-Si TFTs", SID'98,p.443

The authors wish to thank the Array team members at Display Technology Inc., the IBM LME team for their Takatoshi Tsujimura, Osamu Tokuhiro, Mitsuo Morooka, Takashi Miyamoto, Kohichi Miwa, Yuhsuke Yoshimura, Paul Andry and Frank Libsch, "FLOATINGISLAND THIN FILM TRANSISTOR LEAKAGE CAUSED BY PROCESS STEP REDUCTION", IEEE Transactions on Electron Devices, Vol.49, No.4, p.576 (2002)

[23]

Shinjou et al., “A High Aperture Ratio 11.3 inch-diagonal SVGA TFT-LCDs Fabricated by Reduced Process Method”,

AMLCD ’96 (1996), p.20
