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Four-Switch Three-Phase PMSM Converter with Output Voltage Balance and DC-Link Voltage Offset Suppression Fadil Hicham 1, *, Driss Yousfi 1 , Elhafyani Mohamed Larbi 1 and Aite Driss Youness 2 1 2

*

National School of Applied Sciences, Mohammed First University, Oujda BP 669, 60000, Morocco; [email protected] (D.Y.); [email protected] (E.M.L.) National School of Applied Sciences, Cadi Ayyad University, Marrakech BP 575, 40000, Morocco; [email protected] Correspondence: [email protected]; Tel.: +212-650-953-137

Academic Editor: Willy Susilo Received: 15 October 2016; Accepted: 12 January 2017; Published: 17 January 2017

Abstract: High power quality, efficiency, complexity, size, cost effectiveness and switching losses of the direct current to alternating current (DC–AC) conversion system are crucial aspects in industrial applications. Therefore, the four-switch three-phase inverter (4S3P) has been proposed as an innovative inverter design. However, this topology has been known to have many performance limitations in the low-frequency region, because of the generation of an unbalanced voltage leading to an unbalanced current due to the fluctuation and offset of the centre tap voltage of the DC-link capacitors. Those drawbacks are investigated and solved in this paper in order to provide pure sinusoidal output voltages. The generated output voltages are controlled using proportional-integral (PI) controllers to follow the desired voltages. Furthermore, the DC-link capacitor voltage offset is mitigated by subtracting the direct component from the control reference voltage using low pass filters, where this direct voltage component provides the direct current component which leads to DC-link capacitor voltage divergence. A simulation model and experimental setup are used to validate the proposed concept. Many simulation and experimental results are carried out to show the effectiveness of the proposed control scheme. Keywords: four-switch three-phase inverter; inverter cost reduction; permanent magnet synchronous motor (PMSM); current unbalance; vector control

1. Introduction The 4S3P inverter is a low-cost attractive power topology that has attracted the interest of many researches in the last decades. It was first proposed by [1] for the purpose of minimizing the components’ cost; one motor terminal is connected to the centre tap of the DC-link capacitors so that it utilizes two less Insulated Gate Bipolar Transistors (IGBT) [2]. This converter was applied to many fields such as Brushless direct-current (BLDC) motor drives [3,4] and unified power quality conditioners [5]. In addition, the 4S3P power topology could be achieved from standard three-phase topology, which made it very attractive in fault-tolerant control to solve the open/short circuit fault of standard inverter IGBTs [6,7]. The 4S3P inverter conception applied to the fault-tolerant control is very valuable in some critical applications such as wind energy conversion systems [8] and alternating current (AC) motor drives [9]. However, the cost reduction ensured by 4S3P inverters is at the expense of output performance, and they are known to have numerous limitations and drawbacks compared to the 6S3P inverter; the voltage utilization factor is halved compared to the six-switch inverter. On the other hand,

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the capacitor centre tap voltage is fluctuating and presents an offset which destroys the balance among the motor motor phase phase currents currents [10]. [10]. That caused by by the the That voltage voltage fluctuation fluctuation and and offset offset are are caused the third third load load current current alternative and direct component which flow through capacitors that are exploited to create fixed alternative and direct component which flow through capacitors that are exploited to create a a fixed power supply mid-point. As a result, voltage fluctuations as well as current unbalance are increased power supply mid-point. As a result, voltage fluctuations as well as current unbalance are increased as as the torque becomes the frequency lower. Thisand current and voltage the loadload torque becomes higherhigher or the or frequency becomesbecomes lower. This current voltage unbalance unbalance lead to inverter failure, torqueand pulsation, system could lead could to inverter failure, torque pulsation, systemand break downbreak [11]. down [11]. In order to overcome those shortcomings, much research has been done, In order to overcome those shortcomings, much research has been done, as as shown shown in in the the literature. literature. In [11], a motor current unbalance is investigated and a current distortion compensation scheme is In [11], a motor current unbalance is investigated and a current distortion compensation scheme is proposed. Authors Authors in in [12] [12] proposed method by by adjusting adjusting switching switching times, times, considering considering proposed. proposed aa compensation compensation method the capacitor centre tap voltage fluctuation. In [13] the cause and effect of the capacitor centre tap tap the capacitor centre tap voltage fluctuation. In [13] the cause and effect of the capacitor centre voltage fluctuation fluctuation in in an an analytical analytical point point of of view view was was investigated, investigated, and and the the capacitor capacitor voltage voltage offset offset was was voltage suppressed by employing certain switching states. However, the capacitor voltage offset suppression suppressed by employing certain switching states. However, the capacitor voltage offset suppression was achieved achieved at was at the the cost cost of of the the inverter inverteroutput outputperformance. performance. In this paper, the main reasons invoking motor current unbalance unbalance and and torque torque pulsation pulsation as as well well as as In this paper, the main reasons invoking motor current DC-link capacitors voltage offset are investigated. A voltage control method that utilizes 4S3P inverter DC-link capacitors voltage offset are investigated. A voltage control method that utilizes 4S3P inverter output voltage voltage feedback feedback is is proposed proposed and and associated associated to to low low pass pass filters filters to to eliminate eliminate capacitors’ capacitors’ voltage voltage output offset. This organized as as follows: follows: in general model model of of the the four-switch four-switch inverter inverter is is offset. This paper paper is is organized in Section Section 2, 2, aa general illustrated and non-ideal behaviours of the four-switch inverter are discussed; then, its impact on the illustrated and non-ideal behaviours of the four-switch inverter are discussed; then, its impact on the PMSM behaviour is revealed. The voltage balance and the offset suppression are shown in Section 3. PMSM behaviour is revealed. The voltage balance and the offset suppression are shown in Section 3. Section 4 shows the simulation results of both the traditional and proposed balancing schemes, and Section 4 shows the simulation results of both the traditional and proposed balancing schemes, and corroborates the expected features of the proposed method through experimental results. Finally, some corroborates the expected features of the proposed method through experimental results. Finally, some conclusions are presented. conclusions are presented.

2. Four-Switch Three-Phase Inverter Inverter for for PMSM PMSM Drives Drives 2. Four-Switch Three-Phase 2.1. 4S3P Inverter Configuration and Operation The 4S3P inverter is one of the solutions used for the inverter one-leg fault-tolerant control while transistor open/short legleg is is separated and thethe associated phase is connected to the transistor open/shortcircuit; circuit;the thefaulty faulty separated and associated phase is connected to capacitor midpoint. This strategy is of interest to the authors of [3–11]. finalThe power inverter the capacitor midpoint. This strategy is of interest to the authors ofThe [3–11]. final powerstructure inverter is shown in 4S3P1.inverter includes fourincludes groups of IGBT and anti-paralleled diodes, as well structure is Figure shown1.inThe Figure The 4S3P inverter four groups of IGBT and anti-paralleled as two capacitors. Thecapacitors. switches’ and mid-points are mid-points connected in to the diodes, as well as two Thecapacitors’ switches’ and capacitors’ areparallel connected in PMSM. parallel In to addition, the topology presented in Figure 1 caninbeFigure considered as considered a cost-reduction solution with the PMSM. Inpower addition, the power topology presented 1 can be as a cost-reduction only fourwith switches. The switches. low component cost is requiredcost in many applications; that however, will alter solution only four The low component is required in manyhowever, applications; the output performance. that will alter the output performance.

S1 vc1

S2

C1 a ia

Vdc

v c2

u ac

c ic

C2

S1

b ib

u bc

Ls

R

ea

Ls

R

eb

Ls

R

ec

s

S2

Figure 1. Power circuit of the four-switch three-phase inverter. inverter.

In Figure 1, the 4S3P inverter line-to-line output voltages are denoted by uac and ubc. The vas, vbs In Figure 1, the 4S3P inverter line-to-line output voltages are denoted by uac and ubc . The vas , vbs and vcs are the line-to-neutral output voltage. The capacities of C1 and C2 are equal to C, and their and vcs are the line-to-neutral output voltage. The capacities of C1 and C2 are equal to C, and their voltages are denoted by Vc1 and Vc2 respectively. The direct current (DC) bus voltage is denoted by Vdc. Moreover, the switches’ states can be denoted by Boolean variables

s1 , s1 , s2 , s2 . Therefore, the

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voltages are denoted by Vc1 and Vc2 respectively. The direct current (DC) bus voltage is denoted by Vdc . Moreover, the switches’ states can be denoted by Boolean variables s1 , s1 , s2 , s2 . Therefore, the binary value “1” of each switch will indicate the closed state, and the binary value “0” will indicate the opened state. As a result, the generated voltage can be depicted as follows. Vdc 2 (2s1 ) − vc2 Vdc ubc = 2 (2s2 ) − vc2 Vdc Vdc 2 (2s1 − 1) − 2 (2s2

u ac =

u ab =

(1)

− 1)

The DC-link capacitor voltages can be decomposed as a fluctuating voltage and a direct voltage (vc1 = Vdc /2 − vc , vc2 = Vdc /2 + vc ). In addition, and from [11], the voltage fluctuation is depicted as follows. Z vc = −1/2C ic (t)dt (2) The fluctuating voltage amplitude depends on the DC-link capacitor value, the ic currant amplitude, and the PMSM speed. Using the average method, the average output voltage can be written as. re f u ac = v a + vc re f

ubc = vb + vc u ab = re f

where v a

re f

and vb

re f va

(3)

re f − vb

are respectively the a and b leg reference voltage modulated using PWM, and re f

the obtained pulsations are given to the related leg transistors; pulsations are obtained from the v a re f modulation control s1 and s1 , while pulsations are obtained from the vb modulation control s2 and s2 . To generate a balanced voltage by the 4S3P inverter, according to the standard control strategy [11], the reference voltages presented in Equation (4) must be applied. re f

va

=

re f vb

=

√ √

3Vm cos(θr − π/6 − ϕ) 3Vm cos(θr − π/2 − ϕ)

(4)

where θr is the PMSM electrical rotor position, Vm and ϕ are respectively the reference voltage amplitude and phase; they are used to control direct and quadratic PMSM currents as is described in [14]. As a result, from Equation (3), the relation between the line-to-neutral voltages vas , vbs and vcs , re f re f and the reference voltages (v a , vb ), can be computed as is shown in Equation (5) re f

re f

re f

re f

re f (−v a

re f − vb

v as = (2v a − vb − vc )/3 vbs = (2vb − v a − vc )/3 vcs =

(5)

+ 2vc )/3

Equation (5) can be schematized in the rotating reference frame as is shown in Figure 2. The ideal inverter behavior where capacitors’ fluctuating voltage is neglected is presented in the left one, and the real case where the presence of capacitors’ fluctuating voltage leads to the generation of unbalanced voltages is presented in the right one. As is exposed in Equation (2), the Vc depends on the PMSM rotor position, as a result, the line-to-neutral generated voltages include an instantaneous voltage ripple, which leads to PMSM current and torque pulsation as well as motor vibration.

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Figure Vectordiagrams. diagrams. Figure 2.2. Vector

2.2.As PMSM Modelling and Current is exposed in Equation (2),Ripple the VcDetermination depends on the PMSM rotor position, as a result, the lineto-neutral generated voltages include an instantaneous voltage ripple, whichatleads PMSM current Generally, PMSM speed control, rotor position estimation and control fault to detection require a and torque pulsation as well as motor vibration. machine model with an average complexity level. Indeed, controllers exploited to achieve the motor speed and current monitoring, tolerate several modelling simplifications and uncertainty, such as the 2.2. PMSM Modelling and Current Ripple Determination perfect sinusoidal distribution of stator winding. In addition, the produced magneto-motive-forces andGenerally, the magnitude flux linkage through stator winding canand be assumed The electrical PMSM speed control, rotorthe position estimation control atsinusoidal. fault detection require of a permanent magnet synchronous motor in the synchronously rotating reference frame a dynamics machine model with an average complexity level. Indeed, controllers exploited to achieve the motor (abc axis) can be expressed bytolerate [13–15].several modelling simplifications and uncertainty, such as the speed and current monitoring, perfect sinusoidal distribution of stator winding. In addition, the produced magneto-motive-forces v asthe (t) stator = Ri a (winding t) + dψa (can t)/dt and the magnitude flux linkage through be assumed sinusoidal. The electrical (6) dynamics of a permanent magnet synchronous motor the rotating reference frame vbs (t) = Ri dψ )/dt b ( t ) +in b (tsynchronously (abc axis) can be expressed by [13–15]. vcs (t) = Ric (t) + dψc (t)/dt vas (t ) = Ria (t ) + dψ a (t) / dt where R is the rotor resistance, i a,b,c (t) are the stator currents and ψa,b,c (t) are the stator flux. v (t ) = Ri (t ) + dψ b (t) / dt (6) However, the flux ψa,b,c (t) is a resultbsof statorb windings and rotor permanent magnet flux. They can vcs (t ) = Ric (t ) + dψ c (t) / dt be presented in the rotating reference frame linked to the stator as:

and ψ a ,b ,c (t) are the where R is the rotor resistance,  i a ,b ,c (t ) are thestator currents   stator flux. L M M cos(θr ) However, the flux ψ a ,b ,c (t) is a result of stator magnet flux. They  windings and  rotor permanent  (7) [ψa,b,c (t)] =  M L M [i a,b,c (t)] + Ψm  cos(θr − 2π/3)  can be presented in the rotating reference frame linked to the stator as: M M L cos(θr + 2π/3) cos(θ r )  L M M   where L and M are respectively, the self-inductance of the stator winding and the mutual-inductance ψ a ,b , c (t )  =  M L M  ia ,b , c (t )  + Ψ m  cos(θ r − 2π / 3)  (7) between the windings. Ψm is the maximal of thecos( permanent magnet flux, and θ r is the  M M amplitude  L  θ 2 π / 3) + r   electrical rotor position. whereAs L and are respectively, self-inductance of paper the stator and the mutual-inductance theM synchronous motorthe investigated in this is a winding surface mounted permanent magnet motor, the quantities L and M are constants. Consequently, the notation Ls = L − M can andbeθrmade is theto between the windings. Ψm is the maximal amplitude of the permanent magnet flux, simplifyrotor modelling Equation (8). electrical position. Asthe onesynchronous can observe motor from Equation (5), the generated voltages aremounted a combination of the magnet involved As investigated in this paper is a surface permanent re f motor, thev as,bs,cs quantities and M are constants. Consequently, theDC-link notationcapacitor Ls = L − M can befluctuation made to voltage , and Lthe other voltage component caused by voltage simplify modelling Equation which can be depicted by v0c (8). in Equation (8) [16,17]. So, the PMSM final model, in stationary reference As considering one can observe from Equation (5), generated voltages are a combination of the involved frame voltage fluctuation, canthe appear as: ref voltage v as ,bs ,cs , and the other voltage component caused by DC-link capacitor voltage fluctuation re f re f re f 0 0 v as be − depicted v0c = Ri a + 2v a −vb , a /dt + e a − Ri c − L s di c /dt re f which can byLvs di model, in stationary reference v as = c in Equation (8) [16,17]. So, the PMSM final 3 re f 0 0 re f re f vbs − v0c = voltage Rib + Lsfluctuation, dib /dt + eb can − Riappear vc frame considering as:c /dt where re f c − Ls di 2vb −v a and v0c = (8) v = re f 3 bs 3 0 0 0 vcs + 2vc = Ric + Ls dic /dt + ec +2Ric + 2Ls dic /dt re f re f | {z }| {z } −v −v re f vcs = a 3 b wanted behavior current ripple

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where ic0 is the current ripple caused by the capacitor fluctuating voltages. This current has the same PMSM rotor electric pulsation, which leads to rotor vibration and torque pulsation. ii ee ∑ | {z }

Tem =

+

wanted Torque

3ic0 ec |{z}

(9)

Torque ripple

The torque ripple shown in Equation (9) is a product of ic0 and ec which have the same pulsation. r As a result, this torque ripple 3ic0 ec manifests as an alternative component with a frequency of 2 dθ dt = 2ω in the actual torque. 3. Four-Switch Three-Phase Inverter Voltage Balance By assuming that the used switches are ideal [18,19], and the power and voltage losses are neglected, consequently, the PMSM behavior can be modelled as in Equation (8), due to the DC-link fluctuating voltage which affects the generated voltage as is clearly seen in Equation (3). To mitigate this voltage fluctuation v0c as well as the current ripple component ic0 , two PI controllers are added to re f re f control the generated voltages u ac , ubc to be equal to the reference voltages v ac , vbc . In the ideal case, the output of controllers is as follows. re f

re f

re f

re f

u ac = PI (v ac − u ac ) ubc = PI (vbc − ubc )

(10)

R where (PI) denoted in the time-domain by K P (.) + K I (.) is a PI controller, where Kp and KI are the proportional and integral gains, respectively. However, the newest generated voltage references can be affected by sensors’ offset at speed transient states. As a result, a supplementary DC component can appear at the inverter output, and it can be intensified by the integral gains at references. Therefore, the DC-link capacitor voltage becomes imbalanced. To overcome that effect, low pass filters are added, and their outputs are subtracted from the reference voltages. As a result, only AC reference components are sent to the PWM module, and generated by the 4S3P inverter. The response time is chosen in order to ensure good performance, and the open loop transfer function is depicted in Equation (11). sK P + K I HO = (11) s(1 + τs) where s is the derivative operator, and τ is the low pass filter response time, it equates to τ = 0.25s, taken as an optimal value. If a small value was used, the sinusoidal component at a low range of speed would not be filtered. However, if a large one is utilized, the offset suppression would become slow. The presented method’s effectiveness is validated by simulation and experimentally in the following section. 4. Simulation and Experimental Results The proposed scheme [13], presented in Figure 3, and the power configuration were tested in simulation; the power structure was assembled in PSIM which had been interconnected to Matlab/Simulink. In addition, the control scheme and the proposed voltage balance were built in Simulink. The validated algorithm was then implemented by means of the test bench shown in Figure 4.

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Ω

Iq-ref

Iq

PI

UqUd

Eq. (4)Eq. (4)

PI

IdPI

-1

vacref

P(θ) v (t) α

P-1(θ) vβ(t)

Uq

vβ(t)

Iq

vacref

vbcref vbcref

Vdc

uacref*

PI PI

u ref*

PI

ubc

S1 S

ac

S1 S1 ubcref* S 2 1 S2 S2 ref*

PI

PWM

Ω

PI Ω-ref

PI

Ud

vα(t)

PWM

Ω-ref

Id Iq-refId-ref = 0

decoupling and compensation compensation

PI

Id-ref = 0

decoupling and

Vdc

P(θ)

P(θ)

iα(t) iαβ(t)(t)

posetion iβ(t)

αβ αβ

4S3PAC inverter

ubc(t) ia(t)

abc

abc

ic(t)

iia(t)b(t) ib(t) c(t)

Encoder

d/dt d/dt

Encoder

charge charge

Speed

AC

u4S3P ac(t) inverter uac(t)ubc(t)

posetion

Speed

DC

S2

θr θr

DC

PMSM PMSM

Ω Ω

PMSM

PMSM

Figure 3. Vector diagrams. Figure Figure3.3.Vector Vectordiagrams. diagrams.

Figure 4. Experimental setup including 80 W PMSM and a power inverter.

Figure 4. Experimental setup including 80 W PMSM and a power inverter.

Figure 4. Experimental setup including 80 W PMSM and a power The drive system is controlled by a 32-bit fixed-point TMS320-F28335 DSPinverter. board, based on a 150

The is controlled by ausing 32-bit fixed-point TMS320-F28335 DSP board,®based on a 150 MHz MHzdrive clock;system it has been programed rapid prototyping tools of Matlab/Simulink . A Matlab/GUI ®. A The system islocally controlled byrapid aused 32-bit TMS320-F28335 DSPThe board, based on a 150 real-time interface built was to fixed-point make results easyoftoMatlab/Simulink record [14]. power structure clock; it drive has been programed using prototyping tools Matlab/GUI ®. A includes a four-switch three-phase inverter associated to split capacitors. The 4S3P inverter is feeding a MHz clock; it has been programed using rapid prototyping tools of Matlab/Simulink Matlab/GUI real-time interface locally built was used to make results easy to record [14]. The power structure PMSM with Surface Magnet Mounted. Parameters and other configuration requirements are presented real-time locally built wasinverter used to make results easy to record [14]. The powerisstructure includes ainterface four-switch three-phase associated to split capacitors. The 4S3P inverter feeding a in with Table 1 and 2.Magnet To operate around theassociated nominaland point, thecapacitors. PMSM wasThe loaded byinverter a DC generator includes a four-switch three-phase inverter toother split 4S3P is feeding a PMSM Surface Mounted. Parameters configuration requirements are presented supplied by a current source to establish a fixed load torque. An incremental encoder was used to PMSM with Surface Magnet Mounted. and otherthe configuration in Tables 1 and 2. To operate aroundParameters the nominal point, PMSM wasrequirements loaded by a are DCpresented generator measure the rotor position (2000 pulses per revolution). This equipment is illustrated in Figure 4. in Table 1 by and 2. To operate the nominal point, the PMSM was loadedencoder by a DC generator supplied a current sourcearound to establish a fixed load torque. An incremental was used to supplied by a current source to establish a fixed load torque. An incremental encoder was used measure the rotor position (2000 Table pulses per revolution). This equipment is illustrated in Figure 4. to 1. Inverter and controller parameters. measure the rotor position (2000 pulses per revolution). This equipment is illustrated in Figure 4. ComponentsTable 1.Values Components Values Inverter and controller parameters. DC-voltageTable 1. Inverter 24 V and controller DC-link upper capacitor C1 parameters. PWM frequency F PWM = 12 kHz DC-link lower capacitor C2 Components Values Components Components Values Components Sampling Fs Inverter rated power C DC-voltage 24 =V10 kHz DC-link upper capacitor

PWMDC-voltage frequency FPWM =2412VkHz Sampling = 10 kHz PWM frequency FFsPWM = 12 kHz

Sampling

Fs = 10 kHz

1

DC-link capacitor DC-link upper lower capacitor C2C1 Inverter rated power C2 DC-link lower capacitor Inverter rated power

4400 µF 4400 µF Values 1Values kW 4400 µF

4400 µFµF 4400 kW 44001 µF 1 kW

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Table 2. PMSM parameters.

Table 2. PMSM parameters. Values Components

Values

Components Components Values Rated power pValues = 80 W Pole pairs 4 Ratedpower speed Viscous friction fr = 0.04·10 Rated p4000 = 80rpm W Pole pairs 4 −3 Kg·m2 Resistance inductance R = 0.43 Ω, Lrpm = 1.35 mH Rotationfriction inertia J ==0.5 ·10−3 −3Nm/rad Ratedand speed 4000 Viscous fr 0.04·10 Kg·m2 −3 Resistance and inductance R = 0.43 Ω, L = 1.35 mH Rotation inertia J = 0.5·10 Nm/rad 4.1. Simulation Studies 4.1. Simulation Studies The proposed control scheme has two important roles: the first is to control and balance the generated two-phase voltage, and the is to eliminate DC-link offset voltage The proposed control scheme hassecond two important roles: the first is tocapacitors’ control and balance the caused by two-phase PI controllers which add to theisproduced voltage low. Tocapacitors’ evaluate and to voltage choose generated voltage, and theDC second to eliminate the DC-link offset the PI voltage controllers’ gains, a simulation test was done at the speed of 200 rpm kp = the 2.2 caused by PI controllers which add DC to the produced voltage low. To evaluate andusing to choose andvoltage kI = 600 obtained from simulation Figure 5 shows phase voltage current PI controllers’ gains,many a simulation testtestes. was done at the speedthe of 200 rpm using and kp = 2.2 and in the α-β reference frame at 200 rpm operation. It shows the voltage delivered voltage as ktrajectories I = 600 obtained from many simulation testes. Figure 5 shows thethat phase and current well as the obtained are frame perfectly balanced, which is Itachieved by the inverter output trajectories in the α-βcurrent reference at 200 rpm operation. shows that the4S3P delivered voltage as voltage control. well as the obtained current are perfectly balanced, which is achieved by the 4S3P inverter output voltage control.

Figure 5. Simulation Simulation of of voltage voltageand andcurrent currenttrajectories trajectoriesininthe the α-βreference reference frame rpm; (a,are b) Figure 5. α-β frame at at 200200 rpm; (a,b) are the voltage and current wave form without voltage regulation; (c, d) are the voltage and current the voltage and current wave form without voltage regulation; (c,d) are the voltage and current wave wave formthe with the proposed voltage scheme. form with proposed voltage controlcontrol scheme.

The output of the PI voltage controllers is a combination of a sinusoidal term used to ensure The output of the PI voltage controllers is a combination of a sinusoidal term used to ensure reference voltage tracing, and a direct component which comes from the voltage sensors’ offset, from reference voltage tracing, and a direct component which comes from the voltage sensors’ offset, from the unbalance of the DC-link capacitor voltage and from PI controllers that usually control direct the unbalance of the DC-link capacitor voltage and from PI controllers that usually control direct quantities. The dc PI output component leads to a disturbance in the DC-link voltage by adding an quantities. The dc PI output component leads to a disturbance in the DC-link voltage by adding an offset voltage. This phenomenon can lead to the system breaking down if one of the capacitors offset voltage. This phenomenon can lead to the system breaking down if one of the capacitors reaches reaches a low voltage value. In the proposed voltage control scheme, a low pass filter is added in a low voltage value. In the proposed voltage control scheme, a low pass filter is added in order to order to extract the direct component, additionally, this component is subtracted from the reference extract the direct component, additionally, this component is subtracted from the reference voltage. voltage. This voltage offset suppression strategy is confirmed by simulation when the PMSM is under This voltage offset suppression strategy is confirmed by simulation when the PMSM is under a load a load at the speed of 800 rpm. The results are shown in Figure 6. The voltage offset had been obvious at the speed of 800 rpm. The results are shown in Figure 6. The voltage offset had been obvious before applying the suppression method. After the voltage offset suppression algorithm is triggered at before applying the suppression method. After the voltage offset suppression algorithm is triggered at t = 4.45 s, the two-capacitor voltages converge to 12 V at t = 5 s, flowing through a transient state. t = 4.45 s, the two-capacitor voltages converge to 12 V at t = 5 s, flowing through a transient state. Conclusively, it can be confirmed by simulation that the proposed scheme ensures a balanced inverter output voltage and current as well as dc link voltage offset suppression.

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Figure 6. Simulation result of the capacitors’ voltage Vc1, Vc1 and Vdc behaviors at the activation of the voltage offset suppression, at 800 rpm. Figure 6. Simulation result of the capacitors’ voltageVVc1,, V Vc1 and Vdc behaviors at the activation of the Figure 6. Simulation result of the capacitors’ voltage c1 c1 and Vdc behaviors at the activation of the voltage offset suppression, at 800 rpm. Conclusively, it can be confirmed by simulation that the proposed scheme ensures a balanced voltage offset suppression, at 800 rpm.

inverter output voltage and current as well as dc link voltage offset suppression.

Conclusively, it can be confirmed by simulation that the proposed scheme ensures a balanced

4.2. Experimental Evaluation inverter output voltage and current as well as dc link voltage offset suppression. 4.2. Experimental Evaluation After simulation of the proposed DC-link capacitor voltage offset suppression and the 4S3P 4.2. Experimental Evaluation After simulation ofcontrol the proposed capacitor voltage offsetevaluations suppressionhave and the 4S3P inverter inverter output voltage schemeDC-link algorithms, the experimental been carried out output voltage control scheme algorithms, the experimental evaluations have been carried out in the After simulation of the proposed DC-link capacitor voltage offset suppression and the 4S3P inverter in the experimental setup presented previously on an 80 W industrial PMSM. During experimental experimental setup presented previously on the an 80 Wfor industrial PMSM.at During experimental output voltage scheme experimental evaluations have carried intests, the we tests, we started bycontrol adjusting PI algorithms, controllers gains loaded PMSM 200been rpm. The out simulated PI experimental setup presented previously on an 80PMSM W industrial PMSM. During experimental tests, wegains started by adjusting PI controllers gains for loaded at 200 rpm. The simulated PI controller controller gains have been taken as a first trial value; those gains are experimentally adjusted using started by adjusting PI trial controllers gains forgains loaded PMSM at 200 rpm. The simulated PItrial controller gains until haveand beenerror taken as adiscovering first value; those are experimentally adjusted using and error trial until the best performance. The PI controllers’ performance is showed in have been taken as a first trial value; those gains are experimentally adjusted using trial and error discovering theobvious, best performance. The7(a1,a2), PI controllers’ performance is showed in algorithm Figure 7. Itofisuntil obvious, Figure 7. It is from Figure that when the standard control the 4S3P discovering the best performance. The PI controllers’ performance is showed in Figure 7. It is obvious, from Figure 7(a1,a2), that when the standard control algorithm of the 4S3P since inverter is used, the inverter topology is used, the output voltages’ waveforms are thetopology generated from Figure 7(a1,a2), that when the standard control algorithm of non-ideal the 4S3P inverter topology is used,voltages the output voltages’ waveforms are non-ideal since the generated voltages are not following the reference are not following thewaveforms referenceare voltages; assince a result, it can lead to theare over low speed. output voltages’ non-ideal the generated voltages not modulation following the at reference voltages; as a result, it can lead to the over modulation at low speed. However, once PI controllers are However, once controllers aretotriggered, the 4S3P at output voltages are monitored to follow voltages; as aPIresult, it can lead the over modulation low speed. However, once PI controllers are the triggered, the 4S3P output voltages are monitored to follow the references’ voltages as is depicted in triggered, the 4S3P voltages are monitored to follow the references’ voltages as is at depicted in and references’ voltages as output is depicted in Figure 7(b1,b2). The three-phase current form, 500 rpm Figure 7(b1,b2). The three-phase current form, at 500 rpm and when the PMSM is under a load, with and 7(b1,b2). The three-phase current form, at 500 the rpmproposed and when the PMSM is underand a load, with and whenFigure the PMSM is under a load, with and without control method with a standard without the proposed control method and with a standard 6S3P inverter, is shown in Figure 8. Itbe can be without the proposed control method and with a standard 6S3P inverter, is shown in Figure 8. It can 6S3P inverter, is shown in Figure 8. It can be noticed from Figure 8a that the current is unbalanced noticed from Figure 8a that the current isunbalanced unbalanced when when aa4S3P inverter is used; it isitcaused by the DCnoticed from Figure 8a that the current is 4S3P inverter is used; is caused by the when a 4S3P inverter is used; it is caused by the DC-link capacitor voltage fluctuation, and one DCcan link capacitor voltage fluctuation, and onecan cannote notethat that iibb is significantly smaller than the the others, and there link capacitor fluctuation, and one significantly than others, and there note that ib is voltage significantly smaller than the others, and is there is almostsmaller no phase difference between ia is almost no phase difference betweenia iand a and ic. Therefore, the torque pulsation is very significant at the is almost no phase difference between i c. Therefore, the torque pulsation is very significant at the and icnormal . Therefore, the torque pulsation is very significant at the normal operation. Conversely, that operation. Conversely, that torque is smooth with the compensation method in Figure 8b, as well normalisoperation. Conversely, that torquemethod is smooth with the compensation method in Figure 8b, as well torque smooth with the as when a traditional 6Scompensation inverter is utilized Figurein 8c.Figure 8b, as well as when a traditional 6S inverter asutilized when a traditional is Figure 8c. 6S inverter is utilized Figure 8c. V

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Figure 7. 7. Experimental controlled 4S3P 4S3P output output voltages voltages compared compared to to their their Figure Experimental results results at at 200 200 rpm rpm of of controlled references: (a1, a2) are without compensation; (b1, b2) are with the proposed scheme. references: (a1,a2) are without compensation; (b1,b2) are with the proposed scheme.

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Figure8. Experimental waveforms waveforms of of the three-phase Figure and when the load Figure 8.8.Experimental Experimental waveforms of the the three-phase three-phase motor motor current current IIIaaa,,,IIIbbband andIIcIc,c, ,when whenthe theload loadisis is applied at 500 rpm. (a) Motor phase current with control scheme; (b) Motor phase applied at 500 rpm. (a) Motor phase current with the standard control scheme; (b) Motor phase applied at 500 rpm. (a) Motor phase current with the standard control scheme; (b) Motor phase current current with theproposed proposed control scheme; scheme; (c)phase Motorcurrent phase when currentthe when the three-phase current the control (c) Motor when the six-switch six-switch three-phase with thewith proposed control scheme; (c) Motor six-switch three-phase inverter inverter is used. inverter is used. is used.

Figure99shows showsthe the experimental experimental results results of of the torque at 200 rpm Figure rpm when when the the machine machine isisunder under 9 shows the experimental results of the torque at 200 rpm when the machine is under load.Figure Thetop top rowfigures figures show the the results results of the load. The row show of torque behaviours in in three three condition; condition; in inthe thefirst, first, load. The top row figures show the results of the torque behaviours in three condition; in the first, the PMSM is supplied by a 4S3P inverter controlled by an ordinary control algorithm Figure 9a; the PMSM is supplied by a 4S3P inverter controlled by an ordinary control algorithm Figure 9a;in in the PMSM supplied by 4S3P inverter controlled byusing an ordinary control algorithm Figure 9a;ininthe the thesecond, second,isFigure Figure 9b,the theatorque torque shown is is generated generated the 9b, shown using the the proposed proposed control control scheme; scheme;and and in the second, Figure 9b,9cthe torque shown is generated using thethe proposed control scheme; and in the last lastone, one, Figure presents the generated generated torque when last Figure 9c presents the torque when the PMSM PMSM is is fed fed by by the the 6S3P 6S3P inverter. inverter. one, Figure 9c presents the generated torque when the PMSM is fed by the 6S3P inverter. However, However,totoquantify quantify the the distortion distortion of of the the generated generated torque torque at However, at 200 200 rpm, rpm, aa FFT FFT analysis analysis using usingthe the to quantifytool thewith distortion of the generated torque at 200Hz rpm,done, a FFT analysis using theshown Simulink the tool Simulink thefundamental fundamental harmonic of 13.33 13.33 Simulink tool with the harmonic of Hz is is done, and and the the results results are are shownin in the with the row fundamental harmonic of 13.33 Hzthose is done, andthat the results are shown in the 26.66 bottom row bottom figures. One One can observe observe from results bottom row figures. can from those results that aa second second harmonic harmonic with with 26.66 Hz Hzisis figures. One can observetorque from those results that a second harmonic with 26.66 Hz isNevertheless, added to the added to the produced with total harmonic distortion (THD) equals 36.8%. added to the produced torque with total harmonic distortion (THD) equals 36.8%. Nevertheless, produced torque withalgorithm total harmonic distortion equals 36.8%. Nevertheless, when the proposed whenthe theproposed proposed applied, torque(THD) ripples are reduced when algorithm isisapplied, torque ripples are reduced to to THD THD == 8.5%. 8.5%. algorithm is applied, torque ripples are reduced to THD = 8.5%.

Figure of the the motor motor torque torque and andtheir theirfrequency frequencyanalyses analysesunder underaaload loadatat Figure9.9.Experimental Experimental waveforms waveforms of 200 rpm. (a) With the standard control scheme; (b) With the proposed control scheme; (c) When the Figure 9. Experimental waveforms of the motor torque and their frequency analyses under a load at 200 rpm. (a) With the standard control scheme; (b) With the proposed control scheme; (c) When the six-switch three-phase inverter is used. 200 rpm. (a) With the standard control scheme; (b) With the proposed control scheme; (c) When the six-switch three-phase inverter is used.

six-switch three-phase inverter is used.

Figure10 10shows showsthat thataa half-voltage half-voltage variation variation is is about 12 V. V. Also, Also, note that vc1 c1 and Figure andvvc1c1fluctuate fluctuateinin Figure 10 shows thattheir a half-voltage variation is about V. Also,Vnote that vand c1 and vc1 fluctuate in opposite directions since their sum(DC-link (DC-link voltage) is kept12constant dc = 24 V and opposite currents opposite directions since sum voltage) is = 24 V opposite currents dc opposite directions their sum (DC-link voltage) is kept constant Vdc = 24 V and opposite currents areflowed flowed throughsince capacitors. are through capacitors. are flowed through capacitors.

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Figure 10. 10. Capacitor Capacitor voltages’ voltages’ fluctuation fluctuation at at 200 200 rpm rpm when when the the proposed proposed control control scheme Figure scheme is is applied. applied. Figure 10. Capacitor voltages’ fluctuation at 200 rpm when the proposed control scheme is applied.

With the proposed control scheme, the DC-link fluctuation is neither eliminated eliminated nor nor attenuated, attenuated, With the proposed control scheme, the DC-link fluctuation is neither eliminated nor attenuated, but the fluctuations are kept at around half of the supply voltage which is the purpose of much but the fluctuations are kept at around half of the supply voltage which is the purpose of much research [20,21]. research [20,21]. Figure 11 speed tracking capability and reliability of the proposed algorithm. Indeed, Figure 11presents presentsthethe speed tracking capability and reliability of the proposed algorithm. Figure 11 presents the speed tracking capability and reliability of the proposed algorithm. Indeed, starting a steady at 200state rpm,at1000 and deceleration were profiles applied Indeed, from starting from state a steady 200 rpm rpm,acceleration 1000 rpm acceleration and profiles deceleration starting fromatrespectively at =steady 200 rpm, rpm acceleration and deceleration profiles were applied respectively 2 s andstate t at = 8tat s.= The results that the proposed controllers guarantee efficient speed were applied 2 s and t =1000 8show s. The results show that the proposed controllers guarantee respectively at tprofile = 2 scurrent and t = 8harmonic s. and The current results show that the proposed controllers guarantee efficient speed profile tracking and elimination through the range speed,the Figure In contrast, the efficient speed tracking harmonic elimination through range11c. speed, Figure 11c. profile tracking and current harmonic elimination through the range speed, Figure 11c. In contrast, the current performance of the conventional without compensation deteriorates significantly at low In contrast, the current performance of scheme the conventional scheme without compensation deteriorates currentdue performance ofPI thegains conventional scheme without compensation deteriorates significantly at low speed, toatthe fixed and large sampling time to the voltage loop response time. significantly low speed, due to the fixed PI gains and compared large sampling time compared to the voltage speed, due to the fixed PI gains and large sampling time compared to the voltage loop response time. loop response time. Mesured Mesured

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Figure 11. Experimental result of speed profile following. (a) Reference and measured speed; (b) Figurecurrents 11.Experimental Experimental result speed profile following. (a) Reference and measured speed; (b) motor in the d-q frame without compensation scheme; (c) motor currents in the d-q Figure 11. result of of speed profile following. (a) Reference and measured speed; (b) frame motor motor in the d-qwithout frame without compensation motor currents the d-q frame with thecurrents proposed scheme. currents in the d-q frame compensation scheme; scheme; (c) motor(c)currents in the d-qinframe with the with the proposed proposed scheme. scheme.

5. Conclusions 5. Conclusions Conclusions 5. The important features required in an industrial inverter are low cost and high efficiency. In the The important features required required in been an industrial industrial inverter are low cost and high high since efficiency. In the the 4S3P The inverter, the cost-effectiveness has ensured inverter by usingare two split capacitors, the middle important features in an low cost and efficiency. In 4S3P inverter, the cost-effectiveness has been ensured by using two split capacitors, since the middle point is reachable. However, this power topology suffers number ofsince limitations such 4S3P inverter, the cost-effectiveness has converter been ensured by using twofrom splitacapacitors, the middle point is reachable. However, thistap power converter from abalance numberparticularly. of limitations as a fluctuating capacitor centre voltage, whichtopology destroyssuffers the current In such this as a fluctuating capacitor centre tap voltage, which destroys the current balance particularly. In this

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point is reachable. However, this power converter topology suffers from a number of limitations such as a fluctuating capacitor centre tap voltage, which destroys the current balance particularly. In this work, PI controller based schemes were designed and utilized to ensure the output voltage balance. Moreover, low pass filters were used to eliminate the DC-link capacitors’ voltage offset. The effectiveness of the proposed algorithm is validated through a series of simulation and experimental tests. The results demonstrate that the generated voltages are balanced without disturbing either the normal operation or the DC-link voltage balance in the entire speed range. Furthermore, the direct and quadratic currents as well as the torque, are enhanced in terms of ripple and the second harmonic is highly mitigated. Author Contributions: Fadil Hicham initiated the idea of the work. Ait Driss Youness conducted the literature review. Driss Yousfi prepared the experimental test bench. Mohamed Larbi Elhafyani supervised the work. All authors have read and approved the final manuscript. Conflicts of Interest: The authors declare no conflict of interest.

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