FPGA Embedded Soft-Core Processor Implementation of a Digital Controller for a DC-DC Converter I. Urriza, L.A. Barragán, D. Navarro, J.I. Artigas, O. Lucía, and O. Jiménez Departamento de Ingeniería Electrónica y Comunicaciones, Universidad de Zaragoza María de Luna 1, 50018-Zaragoza, SPAIN E-mail:
[email protected] Abstract- This paper presents the implementation of a digital controller in an FPGA for a switching power converter. The design consists of a MicroBlaze embedded soft-core processor that executes the control algorithm, and a customized peripheral that generates the PWM and drives the ADC. This customized peripheral is described using a Hardware Description Language (VHDL). The control algorithm is written in C and uses floating point math what makes straightforward the implementation with regard to fixed-point implementations. Numerical format conversions must be done since PWM and ADC work with unsigned integer data. These format conversions are performed in different ways and its impact on control code execution time and FPGA resources utilization is analyzed. The closed loop system as a whole is simulated and the firmware debugged. Finally, the digital circuit is implemented in the FPGA, and the simulations are experimentally verified. Keywords- Embedded Controllers, Field Programmable Gate Array (FPGA), Hardware Design Languages, System-onProgrammable-Chip (SoPC)
I.
INTRODUCTION
Digital controllers for switching power converters can offer some interesting advantages compared with their analog counterparts. They potentially offer immunity to component variations, programmability, elimination of passive components for tuning, ability to implement sophisticated control techniques, easier integration with other digital systems, and straightforward scaling with the advances of fabrication technologies [1]. Most of the digital controllers developed up to now have been implemented on Digital Signal Processors (DSPs) or Field-Programmable Gate Arrays (FPGAs) [1]-[5]. The DSP user develops software code using high level languages such as C. The FPGA user describes digital hardware using a Hardware Description Language (HDL). The advances in silicon technology have resulted in FPGAs, which in addition to the configurable logic elements, integrate hardware multipliers, embedded processors, and block RAMs on a single chip [6]. This technology allows the designer to use an FPGA to combine intellectual property (IP) processor cores along with customized hardware peripherals to implement a System-on-Programmable-Chip (SoPC) solution [7]. The utilization of FPGA embedded processors allows Hardware/Software (HW/SW) partitioning on a single chip what opens new possibilities in the design space exploration. FPGA embedded processors can be classified on hard-core and soft-core processors. A hard-core processor is laid out on the
chip in dedicated silicon. In contrast, a soft-core processor uses existing configurable logic elements from the FPGA to implement the processor. Only specific high performance FPGAs integrate a hard-core; however, a soft-core processor can be implemented in any FPGA as long as there are enough configurable logic resources available. This work presents the design and implementation of a digital control for a dc-dc converter, using an FPGA embedded soft-core processor. The controller combines MicroBlaze [8] with a specific peripheral. As in any FPGA, the designer describes in an HDL his own custom peripherals that meet the exact design requirements, and connect them to MicroBlaze through an on chip bus. Besides, describing the customized peripheral in HDL allows high flexibility and technology independence. The entire design can be mapped to different FPGA platforms. Like using a DSP, the designer programs MicroBlaze in C language. Floating-point to fixed-point conversion has been identified [9] as the most difficult aspect of implementing an algorithm on an FPGA. By writing the control algorithm in C language using float type variables, the control law implementation is straightforward with regard to a fixed-point implementation. Since PWM and ADC work with unsigned integer data, format conversions must be done. Unlike using a DSP, these format conversions can be performed by MicroBlaze or can be implemented hardware on the peripheral. The impact of how they are done on the control code execution time and FPGA resources utilization is analyzed. In order to verify the functionality, the power converter, the ADC, and the controller (MicroBlaze + firmware + peripheral) have been simulated in closed-loop using ADVance MS from Mentor Graphics. It is a mixed-signal simulation tool that can simulate any combination of SPICE or SPICE-like models and mixed-signal hardware description languages (MS-HDL) [10], such as VHDL-AMS [11]. This paper is organized as follows. Section II shows the reference example and presents the digital compensator design. Section III presents HW/SW partitioning and implementation. The software that runs on the microprocessor, the hardware customized peripheral, and the format conversion implementations are described. In section IV, the whole system is simulated using a mixed-signal simulation tool. The VHDL description of the controller used for simulation is also used for synthesis. Finally, section V presents experimental results and some conclusions are drawn.
II. DIGITAL CONTROLLER DESIGN Fig. 1 shows the reference example used along the paper. The power stage is a buck converter with the following parameters: input voltage Vg = 12 V, L = 47 μH, C = 200 μF, capacitor ESR (equivalent series resistance) RC = 25 mΩ, inductor DC resistance RL = 30 mΩ, load resistance R = 1.35 Ω, and switching frequency fsw = 100 kHz. The output voltage vout has to be regulated at Vo_ref = 5 V. The output sense network H scales the output voltage vout to the ADC input voltage range [0, VFS]. The full scale voltage VFS is 3.3 V. The ADC converts the output voltage to a digital word. The error between the desired and measured output voltage is processed by MicroBlaze to determine the value of the switch duty cycle. The digital pulse width modulator (DPWM) generates the driving signal qc that controls the switch SW of the converter. The FPGA clock frequency is 50 MHz. L
SW
RL
Vg
+ -
RC
+ -
R
-
H⋅vout
ADC controller
ADC
d(n)
PLB Bus CLK
MicroBlaze®
FPGA
Fig. 1. Reference example: Buck converter controlled by MicroBlaze.
The continuous time transfer function of the plant Gp(s), including the buck converter, the voltage sensing gain H, the ADC transfer function Gadc, and the PWM transfer function Gpwm is: (1) Gp ( s ) = G pwm (s ) ⋅ Gvd (s ) ⋅ H ⋅ Gadc (s ) The small signal model of the buck converter in s domain is [12]:
(1 + sRC C )Vg
R R + RL Gvd (s ) = ⎛ L ⎞ 2 ⎛ R + RC ⎟ + s LC ⎜⎜ 1 + s⎜⎜ RC C + (R // RL )C + + R RL ⎟⎠ ⎝ ⎝ R + RL
(2) ⎞ ⎟⎟ ⎠
The ADC resolution is 7 bits. The result is taken as an unsigned integer. The delay is neglected in the transfer function, thus, Gadc is approximated by the ADC gain Kadc [3], [12]: Gadc (s ) = K adc e − s⋅T
adc
=
n pwm
2 − s⋅T e 500
pwm
≈
512 500
(4)
The discrete-time transfer function Gp(z) is obtained from the continuous-time transfer function Gp(s) using the zeroorder hold transformation with a sample time of T = 1/fsw. The digital controller C(z) is designed using the direct digital design method introduced in [13]. This method unifies the design procedures for both root locus and Bode. The sampling period is T = 1/fsw. The system bandwidth is set at 5 kHz with a phase margin (PM) of 60º. Thus, according to [13] the controller must satisfy the following angle and magnitude criteria:
(
)
(
)
∠C e jω T + ∠Gp z = e jω T = −180º + PM
(
Ce
c
j ω cT
c
)⋅ Gp(z = e ) = 1 j ω cT
(5)
where ωc is the gain crossover frequency. Considering a PIlead compensator with an integrator term to get zero steady state error, the obtained controller is: (z − 0.8597 )(z − 0.97 ) (6) C ( z ) = 0.12223
III. HW/SW IMPLEMENTATION
H
C
qc
DPWM
=
vout
D
VSW
− s⋅T pwm
(z + 0.1)(z − 1)
+
iL
G pwm (s ) = K pwm e
2n e − s⋅T VFS adc
adc
≈
128 −1 V 3.3
(3)
The DPWM resolution is equal to the FPGA clock frequency divided by the switching frequency, 500 in this case. The 9-bit duty cycle command is considered as an unsigned fraction. The delay is also neglected in the transfer function, thus, Gpwm is approximated by the PWM gain Kpwm [3], [12]:
As mentioned above, the design will be implemented using a MicroBlaze soft-core processor. It is a 32-bit reduced instruction set computer (RISC) optimized for embedded applications in Xilinx FPGAs. The Xilinx Embedded Development Kit (EDK) [14] provides a graphical user interface that allows the designer to create embedded systems based on MicroBlaze cores shortening the design cycle of a SoPC. EDK also provides a library of commonly used peripheral cores, and several interface solutions to interconnect them. Moreover, it allows the designer creating custom peripherals to implement functionality not available in the EDK peripheral library and use them in the embedded system. Furthermore, EDK includes GNU-based software development tools for MicroBlaze such as the C compiler, assembler, debugger, and linker. Synthesis and implementation tools are also integrated. The first step is partitioning the system into hardware and software components, that is, choosing the hardware or software implementation for each component of the system. Fig. 2 shows the HW/SW partitioning selected for the controller. The software is written in C and it runs into the MicroBlaze. The hardware (custom IP) has been described in VHDL and is connected to the MicroBlaze through the PLB (Peripheral Local Bus). The MicroBlaze has been configured with 50 MHz of processor clock frequency, and 50 MHz of bus clock frequency. Besides, an FPU has been included, this way, any operation on the C data type ‘float’ will be automatically inferred by the compiler to use the FPU. The peripheral is mapped into memory. There are two peripheral registers that are addressable through software (REG_tmp and ADC_REG). The main function initializes the variables, enables the interrupt, and then executes an infinite
loop. The Interrupt Service Routine (ISR) is the function which is called when the peripheral generates an interrupt. FPGA
SW (C language) main
Interrupt
A. Interrupt Service Routine The ISR is the function which is called when the peripheral generates an interrupt. It reads register ADC_REG, executes the control law to compute the new duty command, and writes it into REG_tmp register. To map the digital controller function into software code, the transfer function (6) is implemented in a direct-form realization, which results in the following difference equation:
ISR
HW (VHDL)
32
32
Float2Uint 9
Uint2Float 7
REG_tmp
ADC_REG
d (k ) = 0.9 ⋅ d (k − 1) + 0.1 ⋅ d (k − 2 ) + 0.1222 ⋅ e(k ) − 0.2236 ⋅ e(k − 1) + 0.1019 ⋅ e(k − 2 )
REG_D
7
9
ADC control
StartC
DPWM generator
2
(7)
where d is the duty cycle, e is the error voltage, and k denotes the current sampling cycle.
Custom IP SDATA
3) the ADC conversion is triggered. When the conversion is completed, an interrupt is generated by the peripheral and MicroBlaze runs the ISR. The duty cycle is updated at the start of the subsequent switching cycle.
qc
NCS & SCK
Fig. 2. HW/SW partitioning of the controller.
The customized peripheral consists basically of two blocks, the DPWM generator and the ADC interface. The first block is a counter based constant frequency DPWM. It has a freerunning counter CNT_TS, a register REG_D that stores the duty command, and a digital comparator. The signal qc that controls the converter switch is generated comparing the duty command with the counter value. Besides, this block generates the signal StartC that starts the A/D conversion. The second block generates the signals NCS and SCK that control the ADC converter and reads its serial data output SDATA. When the conversion is done, it generates a software interrupt. MicroBlaze works with floating-point numbers and the peripheral with unsigned integer data. If the format conversions are done in the peripheral, blocks Uint2Float and Float2Uint must be implemented. The block Uint2Float returns a float encoding of ADC_REG. The block Float2Uint returns an unsigned integer encoding of the duty command. CNT_TS
Fig. 4- Interrupt Service Routine C listing.
TSW=500⋅TCLK
499
200
tADC 0
t1 StartC
tISR t2
time Update Duty
ADC Interrupt SW
main
ISR
main
Fig. 3. Controller task scheduling.
Fig. 3 shows the controller task scheduling. There is a single ISR synchronous with the DPWM switching. The DPWM period TSW and the sampling period are equal to 500 clock periods. When CNT_TS counter is equal to 200 (time t1 in Fig.
Fig. 4 shows the C listing of the ISR function when format conversions are done by the peripheral. Every time it is executed, the float encoding of the ADC conversion result is read and moved to variable ADC_F using the C function memcpy. Then, the error between the desired and measured digital output voltage is computed. The desired digital output voltage, constant V_REF in Fig. 4, is the ADC digital output code corresponding to the scaled version of the target converter output voltage. Initial error values of zero are set in the main function. The new duty cycle d(k) is computed using (7). The duty is clamped, and the variables are updated for the next calculation cycle. This subroutine is executed every switching period, i.e., every 500 clock cycles.
B. Type Conversions It is assumed that MicroBlaze parameter C_USE_FPU is set to 1 in order to include an FPU. This parameter is set in the Microprocessor Hardware Specification file. MicroBlaze works with floating-point numbers and the peripheral with unsigned integer data. The format conversions can be implemented in different ways. Table I shows the hardware resources and the ISR bandwidth utilization for the implementations analyzed. The ISR utilization is defined [15] as TISR/TSW, where TISR is the ISR execution time (see Fig. 3). Column v.0 shows the results when type conversions are performed in the ISR by type casting in C. Function memcpy in Fig. 4 must be replaced by the following instructions: ADC_F = (float) ADC; PWM = (int) (DUTY_0 *(float)512.0);
The ISR utilization is greater than one and then it is not feasible. TABLE I COMPARISON OF 3 TYPE CONVERSION IMPLEMENTATIONS Version
V.0
C_USE_FPU Slices MUL18x18 ISR utilization
V.1
V.2
1
2
1
1442
1756
1542
7
7
7
1.05
0.548
0.516
register value and the ADC_F C float variable. It basically describes a barrel shifter. Since ADC_REG represents an unsigned integer of 7 bits, its value ranges from 0 to 127. Thus, the exponent of the float representation will be in the range from 127 to 133. First, the exponent is initialized to 133 and the significand is initialized to ADC_REG. Thus, the significand is shifted one bit to the left and the exponent decremented until the significand most significant bit is equal to 1, thus, the rest of the significand bits are the fractional part. Fig. 7 shows the VHDL description of the Float2Uint block that implements the conversion between DUTY_0 C float variable and REG_tmp 9 bit register value. The exponent of the floating point variable must be in the range [123, 126] since the duty cycle has been clamped to the range [0.1, 0.9] in the ISR. The register REG_tmp must store the fractional value of the float number. First, the mantissa variable is initialized to the 9 most significant bits of the significand, taking into account the normalization bit. This way, if the floating point exponent is 126, according to (8), the register must store mantissa. In other case, mantissa is shifted one bit to the right and the variable exp decremented while it is positive. After that, variable mantissa is assigned to REG_tmp.
If MicroBlaze parameter C_USE_FPU is set to 2 the FPU also implements the square root and some format conversions. Specifically, instructions flt and fint are available. Instruction flt implements the conversion from signed integer to floating point, and the instruction fint implements the conversion from floating point to signed integer. Column v.1 shows the results in this case. A significant benefit in ISR utilization is obtained. Column v.2 shows the results when the type conversion is done by the custom peripheral. It decreases the ISR utilization and the hardware resources utilization with regard to the above implementation. Below, we are going to explain how the blocks Uint2Float and Float2Uint that implement the format conversions have been implemented in HW. C's float type corresponds to singleprecision format of standard IEEE-754 [16]. 1 bit
8 bits
23 bits
s
e
f
MSB
Fig. 6. VHDL code for HW unsigned integer to floating point conversion. LSB
Fig. 5. IEEE single-precision floating-point number layout.
Fig. 5 shows the data format of a single precision floating point number in this standard. It is encoded in 32 bits where s is the sign bit, e is the exponent, and f is the fractional part of the significand. It uses a hidden bit, so the significand is 1+f. The exponent is biased 127. Then the value of the normalized number is: (8) (− 1)s ⋅ (1. f ) ⋅ 2 e−127 Fig. 6 shows the VHDL description of the Uint2Float block that implements the conversion between the ADC_REG 7 bit
Fig. 7. VHDL code for HW floating point to unsigned integer conversion.
IV. MODELING AND SIMULATION RESULTS EDK supports simulation of the embedded system by exporting VHDL models of the embedded hardware. The models include block RAM (BRAM) memory peripherals that are initialized with the embedded software. In addition to this, EDK includes scripts to simplify simulator usage. The power stage described above has been simulated along with the VHDL models of the embedded system using the mixed-signal simulation tool ADVance MS from Mentor Graphics. The buck converter has been modeled in Eldo, a spice-like analog simulator from Mentor Graphics. Switch SW is modeled as a voltage-controlled switch. The sense network H is implemented as a resistor divider.
the serial data transfer, the register ADC_REG that stores the conversion result, the interrupt request from the custom made peripheral that call the ISR, the write control signal from the MicroBlaze to write the duty command in the peripheral that is mapped into memory, and the duty command updated at the end of the switching cycle.
Fig. 9. Simulated signals during a switching period.
Fig. 10 shows the transient response simulation of the closed loop when the load resistor is stepped from 1.35 Ω to 2.7 Ω. From top to bottom, it is shown the buck converter output voltage, the load current, the result of the ADC conversion (7 bits) and the duty cycle command (9 bits). It can be seen that oscillations stop inside the zero error bin after the load change since the ADC_REG value equals the reference (see V_REF constant declaration in Fig. 4).
Fig. 8. Interface in VHDL-AMS.
Fig. 8 shows the VHDL-AMS model of the interface connections between the buck converter modeled in Eldo and the digital controller modeled in VHDL. The controlling voltage VSW of switch SW is generated from digital signal qc. Another voltage VSWL controls a second switch to put in parallel an additional load resistor and generate step load changes. The analog to digital converter is also modeled. It converts the scaled by H output voltage HVO into 7 bits. In order to take into account quantization and delay effects in the testbench, the transfer function and the serial interface timing of the ADC have been modeled. Fig. 9 shows the tasks scheduling during a switching period. From top to bottom, it is shown the gating signal qc, the digital ramp corresponding to the free running 9-bit counter CNT_TS, the signal StartC that initiates the ADC conversion and frames
Fig. 10. Load step simulation.
V. EXPERIMENTAL RESULTS A buck converter prototype has been implemented for testing purposes. The proposed controller has been implemented in a Xilinx FPGA XC3S400 Spartan-3 embedded in a Digilent Spartan-E System Board. The 12 bits 1 MSPS ADCS7476 ADC from National Semiconductor has been used. As analyzed in [1], a necessary condition to avoid limit cycle oscillations is that the DPWM will be able to find an output voltage that lies within the ADC zero error bin. Thus, the resolution of the DPWM must be greater than the resolution of the ADC. In order to fulfill this condition, only the 7 most significant bits of the ADC are used. Fig. 11 shows the simulated (a) and measured (b) response of the converter output voltage to a step-load change, where
the load has been stepped from 1.35 Ω to 2.7 Ω. It can be seen that simulations closely match experimental results.
flexibility for lower hardware resources and ISR bandwidth utilization. The customized peripheral is described in VHDL to allow high flexibility, reusability, and technology independence. Thus, it can be utilized in other embedded control applications. ACKNOWLEDGMENT This research was supported in part by the Spanish MEC under Project TEC2007-64188 and FPU Grant AP2007-03276, by DGA under Project PI008/08, and by Bosch and Siemens Home Appliances Group. The authors are members of the Instituto de Investigación en Ingeniería de Aragón (I3A). REFERENCES [1]
(a)
[2] [3] [4] [5]
[6] [7] (b) Fig. 11. Load transient response. (a) Simulation (b) Measured, voltage: 50 mV/div, current: 0.9 A/div, time: 50 μs/div.
[8] [9]
CONCLUSIONS FPGA-based systems are able to combine general-purpose microprocessors and dedicated hardware cores as a SoPC solution. In this work, a SoPC has been designed and implemented on an FPGA. It is composed of a soft-core MicroBlaze microprocessor that executes by software the digital control algorithm of a dc-dc converter, and a customized peripheral that reads the ADC and generates the corresponding DPWM. The system was tested by simulations and experiments, demonstrating good closed-loop stability and performance. Since MicroBlaze works with floating-point numbers and the peripheral with unsigned integer data, format conversions must be done. Hardware resources and the ISR bandwidth utilization for different implementations have been analyzed. Implementing format conversions on the peripheral trades
[10] [11]
[12] [13] [14] [15] [16]
A. Prodic, D. Maksimovic, R.W. Erickson, “Design and Implementation of Digital PWM Controller for a High-Frequency Switching DC-DC Power Converter,” Proc. IEEE IECON, pp. 893-898, 2001. A. Mohammed, “Digital Control of Power Converters,” IEEE APEC, vol. 1, Seminar 4, February 2008. H. Al-Atrash, I. Batarseh, “Digital Controller Design for a Practicing Power Electronics Engineer,” Proc. IEEE APEC, pp. 34 – 41, 2007. C. Paiz, M. Porrman, “The utilization of Reconfigurable Hardware to Implement Digital Controllers: a Review,” Proc. IEEE ISIE, pp. 23802385, 2007. A. de Castro, P. Zumel, O. García, T. Riesgo, and J. Uceda, “Concurrent and Simple Digital Controller of an AC/DC Converter with Power Factor Correction Based on FPGA,” IEEE Trans. on Power Electronics, vol. 18, no. 1, pp. 334-343, January 2003. J.J. Rodríguez-Andina, M.J. Moure, and M.D. Valdes, “Features, Design Tools, and Application Domains of FPGAs,” IEEE Trans. Industrial Electronics, vol. 54, no. 4, pp. 1810-1823, August 2007. S. Sánchez-Solano, A.J. Cabrera, I. Baturone, F.J. Moreno-Velo, and M. Brox, “FPGA Implementarion of Embedded Fuzzy Controllers for Robotic Applications,” IEEE Trans. Industrial Electronics, vol. 54, no. 4, pp. 1937-1945, August 2007. XILINX Inc.: “MicroBlaze processor reference guide” UG081, 2007. http://www.xilinx.com T. Hill, “AccelDSP synthesis tool floating-point to fixed-point conversion of MATLAB algorithms targeting FPGAs,” Xilinx WP239, 2006. L.A. Barragán, I. Urriza, D. Navarro, J.I. Artigas, J. Acero, and J.M. Burdío, “Comparing simulation alternatives of FPGA-based controllers for switching converters,” Proc. IEEE ISIE, pp. 419-424, 2007. F. Pêcheux, C. Lallement, and A. Vachoux, “VHDL-AMS and VerilogAMS as Alternative Hardware Description Languages for Efficient Modeling of Multidiscipline Systems,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst , vol. 24, no. 2, pp. 204-225, February 2005. W. Al-Hoor, J. Abu-Qahouq, L. Huang, I. Batarseh, “Design Considerations and Dynamic Technique for Digitally Controlled Variable Frequency DC-DC Converter,” Proc. IEEE PESC, pp. 846 – 850, 2007. R.T. O'Brien, and J.M. Watkins, “A unified procedure for Discrete-Time Root Locus and Bode Design,” Proc. American Control Conference, pp. 4935-4940, 2005. XILINX Inc.: “EDK Concepts, Tools, and Techniques. A Hands-On Guide to Effective Embedded System Design,” 2007. http://www.xilinx.com D. Figoli, "Software Design for Digital Power- Programming 101 for Analog Designers", Texas Instruments Seminar, 2006, http://www.ti.com IEEE Standard for Binary Floating-Point Arithmetic, ANSI/IEEE Std., IEEE 754-1985, 1985.
