FPGA implementation of Hilbert transformer based on lattice wave digital filters Meenakshi Aggarwal
Richa Barsainya
Tarun Kumar Rawat
Division of Electronics and Communication Engineering Netaji Subhas Institute of Technology New Delhi-110078 Email:
[email protected]
Division of Electronics and Communication Engineering Netaji Subhas Institute of Technology New Delhi-110078 Email:
[email protected]
Division of Electronics and Communication Engineering Netaji Subhas Institute of Technology New Delhi-110078 Email:
[email protected]
Abstract—The minimum hardware and low power dissipation have always been the main concern for the efficient filter implementation. In this paper, an effective way of implementing the lattice wave digital structure of the Hilbert transformer with canonic signed digit code (CSDC) coefficients is proposed. Further, the proposed structure is implemented using carry save adders rather than slow ripple carry adders. This increases the speed of overall filter structure compared to the conventional way of implementing the filter with CSDC coefficients. The proposed Hilbert transformer is implemented and successfully tested on Xilinx Spartan XC3s200-4ft256 field programmable gate array (FPGA) device. The effectiveness of the proposed design method is proven with an example.
Keywords:-Hilbert Transformer, FPGA, Lattice Wave Digital Filter, Carry-save adder, Canonic signed digit code. I.
I NTRODUCTION
The Hilbert transform is an important tool in signal processing and find applications in different areas like digital communication where it is used for single side-band modulation and edge detection of digital images [1], [2], [3]. Previously finite impulse response (FIR) and infinite impulse response (IIR) digital based Hilbert transformer has been developed using several methods such as the Remez exchange algorithm [4], eigen filter method [5], and weighted least square method [6]. It is known that IIR filter realization has an advantage over FIR filter realization with respect to the number of coefficients and better statistical performance [7], [8]. Various methodologies for implementing the Hilbert transformer were also investigated which comprises of switched-capacitor implementation [9], neural network [10], and multiplier-less triangular array realization [11]. Wave Digital Filter (WDF) is an excellent way for implementation of IIR digital filters because of its closeness to classical filter networks [12]. A wide variety of WDFs are available and find application in systems requiring digital filters and shown many beneficial properties like low coefficient sensitivity, good stability and good dynamic range [13]. A specific class of WDFs is called the lattice wave digital filters (LWDFs). To reduce the hardware cost as well as to increase the speed, the coefficients of the filter are represented in canonic signed digit code (CSDC). The resulting digital filters can be easily implemented using shifts and add multipliers. The minimum number of nonzero bits is observed in CSDC c 978-1-4673-7231-2/15/$31.00 ⃝2015 IEEE
coefficients compared to other radix-2 representations. This in turn again reduces the number of adders [16]. The CSDC representation has three digits, −1, 0 and +1 as opposed to the two’s-complement representation which has only two digits, 0 and +1. A property of the CSDC representation is that two consecutive bits in a CSDC number can not be nonzero. The nonzero bits in a CSDC number are approximately reduced to 𝑊3𝑑 while a two’s-complement number has on average 𝑊2𝑑 nonzero bits, where 𝑊𝑑 is the coefficient wordlength [17], [18]. It is well known that the delay of ripple carry adders (RCAs) is large due to carry propagation [19], [20]. It is observed that the carry-save arithmetic avoids time consuming carry propagation. Therefore, it is efficiently implemented in many DSP algorithms [21]. The use of carry-save adders (CSAs) instead of RCAs reduce the computation latency of the critical loop, resulting a reduced propagation delay [22]. The carrysave mapping of first- and second-order allpass sections are presented in [23]. In this paper, an effective way of implementing the lattice wave digital structure of the Hilbert transformer with CSDC coefficients is proposed. Further, the proposed structure is implemented using CSAs rather than RCAs. This increases the speed of overall filter structure compared to the conventional way of implementing the filter with CSDC coefficients [2]. The paper is organized in six Sections, including introduction. Section II describes the basic concepts of Hilbert transform. The Lattice wave digital filters are described in Section III. In Section IV, FPGA implementation of Hilbert transformer is presented. One design examples of fixed coefficient represented in Section V. The paper is concluded in Section VI. II.
H ILBERT TRANSFORMER
It is known that there exists an explicit relation between the discrete Hilbert transformer and complex half-band filter. Complex half-band filter satisfies frequency domain constraints of the Hilbert transformer [8]. The frequency response of ideal Hilbert transformer is characterized as { 𝑗, −𝜋 < 𝜔 < 0 𝐻𝐻𝑇 (𝑒𝑗𝜔 ) = (1) −𝑗, 0 < 𝜔 < 𝜋 Complex half-band filter could be simply obtained by adding a shift of 𝜋2 radians in the frequency response of a real half-band
TABLE I.
filter [8]. The real half-band filter 𝐺(𝑧) can be expressed as
𝛾 range
Adaptor Type
1 [𝐴1 (𝑧 2 ) + 𝑧 −1 𝐴2 (𝑧 2 )] (2) 2 where 𝐴1 (𝑧) and 𝐴2 (𝑧) are stable magnitude allpass filters. The complex half band filter is obtained by frequency transformation of real half-band filter [15] using 𝐺(𝑧) =
𝐻(𝑧) = 𝑗𝐺(−𝑗𝑧)
T YPE OF A DAPTORS
− 12
Type I
Type III Type IV
(3)
≤𝛾
