16th IEEE International Conference on Control Applications Part of IEEE Multi-conference on Systems and Control Singapore, 1-3 October 2007
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Fractional Delay Based Repetitive Control with Application to PWM DC/AC Converters Yigang Wang, Danwei Wang∗ , Bin Zhang and Keliang Zhou Abstract— In repetitive control system, the period of exogenous signals must be the integer number of sampling points. However, it can not be always satisfied in real applications. In this paper, a systematic approach for non-integer delay repetitive control system with fixed sampling rate is proposed. The proposed fractional delay based repetitive control scheme employs the design techniques in digital signal processing theory and two different implementation structures are presented. One is easy to design and the other has optimized performance. Application of the proposed method to PWM DC/AC converter systems is studied to illustrate the design procedure and performance. Experimental results demonstrate the effectiveness of the proposed approach.
I. I NTRODUCTION Repetitive control [1] has been proven to be a useful technique for asymptotic tracking and/or rejection of exogenous periodic signals. The repetitive control employs the internal model principle [2] and consists of a periodic signal generator enabling perfect rejection of periodic disturbances. It has been successfully applied to many areas, including hard disk and optical disk driver [3], [4], non-circular turning [5], industrial robot [6] and PWM inverter and rectifier [7]. Repetitive control system introduces infinitely large feedback gain at periodic signal’s fundamental frequency and its harmonics, so that perfect performance can be achieved on the periodic signal as long as the closed loop system is stable. A prototype discrete-time repetitive controller design was proposed [8] by using zero phase error tracking compensation (ZPETC) technique. To improve the robust stability, zero-phase low-pass filter Q(z) was introduced in the prototype repetitive control scheme [9]. The tradeoff between robustness stability and disturbance rejection performance is made in the design of Q filter. In repetitive control system, the period of exogenous signals must be the integer number of sampling points. In real applications, however, it can not be always satisfied. Moreover, in many applications, the periodic signal changes dynamically in period so the period can never always be integer. For the non-integer delay cases, there are two simple approaches to handle it: 1) Adjust the sampling rate of repetitive control system. This method is easy but not Yigang Wang is with School of EEE, Nanyang Technological University, 639798, Singapore
[email protected] Danwei Wang is the corresponding author and with Faculty of School of EEE, Nanyang Technological University, 639798, Singapore
[email protected] Bin Zhang is with School of EEE, Nanyang Technological University, 639798, Singapore Keliang Zhou is with Delft University of Technology, Faculty of EWI, Mekelweg 4, 2628 CD DELFT, The Netherlands
1-4244-0443-6/07/$20.00 ©2007 IEEE.
practical in general, since it requires to redesign the whole control system. 2) Round to the nearest integer. It is the most conventional method and easy to implement, but with limited performance. On the other hand, [10], [11] studied the similar phenomena and proposed different algorithms to reject uncertain periodic signals. In this paper, a Fractional Delay based Repetitive Control (FD-RC) scheme is proposed. FD-RC supplies a systematic approach for non-integer delay case in repetitive control system with fixed sampling rate. This method is based on the fractional delay filter design [12], [13], which is a technique for bandlimited interpolation between samples, in digital signal processing theory. Two different realizations are introduced in this paper, one realization is Lagrange Interpolator method, which can be considered as the comprehensive version of linear interpolation method; the other is least square FIR optimized approximation method. The advantage of Lagrange Interpolator method lies in easy explicit formulas for the coefficients and good approximations at low frequency range. The least square FIR method is, in principle, with the smallest least square error in the defined approximation band. A similar optimal interpolation approach was also proposed for repetitive control in [14] with application to repetitive acoustic noise cancelation. A possible application of proposed FD-RC could be autotuning or adaptive repetitive control system, i.e., the period of signal is changing with time. The online estimation of period could be non-integer number of sampling points. Some results of adaptive repetitive control scheme or similar topics were reported in [15], [16]. The outline of the article is as follows. Section II analyzes the relationship between the period-time N and repetitive system closed-loop sensitivity function. Section III gives two different design methods of FD-RC: Lagrange Interpolation method and Least Square method. In Section IV, experimental results are presented to confirm the effectiveness of proposed algorithms. Comparisons between the two design methods are also given. Section V summarizes the article. II. P ERIOD S ENSITIVITY A NALYSIS Figure 1 shows the block diagram of conventional plugin repetitive control system. Where P (z) is the nominal plant model. The periodic signal generator consists of Q(z), z −N +L and z −L , where N is an integer and denotes the period of disturbance. L is the linear phase lead. Without loss of generality, assume N ≫ L. Q(z) is a unity gain low-pass filter. kg is learning gain and Φ(z) is a compensator. kg , L, Φ(z) and Q(z) are parameters to be determined during the
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TuC04.4 Interpolator method and least square method. Lagrange Interpolator method has simple implicit formula and is easy to implement, but with limited performance. Least square method has the smallest least square error in the defined approximation band and hence has better performance. Fig. 1.
Block Diagram of Repetitive Control System
A. Problem Formulation
design of a repetitive control system. The sensitivity function can be easily obtained, Srep (z) = = =
where 0 ≤ d < 1. Here we need only consider the fractional part d. The transfer function of an ideal delay element may be written as Hi (z) = z −d (4)
E(z) D(z) 1 − Q(z)z −N 1 − Q(z)z −N [1 − kg z L T (z)Φ(z)] 1 − Q(z)z −N 1 − Q(z)z −N Γ(z)
(1)
where T (z) = K(z)P (z)/(1 − K(z)P (z)). The repetitive control requires the exact knowledge of the period-time of the external signals. The tracking performance is highly dependent on the exactness of period-time N . The relationship can be illustrated from the the period sensitivity function Sp (ejω ), which is defined as follows, Sp (ejω )
Define N as the integer part of D and d as the fractional part, i.e., D = N + d = ⌊D⌋ + d (3)
The magnitude response of (4) is unity for all frequencies, while the phase response is linear with a slope of −d. The corresponding impulse response is obtained via inverse discrete-time Fourier transform, hi (n) =
(5)
Unfortunately, the ideal impulse response is not only infinitely long but also noncausal, which makes it impossible to implement it in real-time applications. A finite-order FIR (2) filter can be used to approximate the ideal response in Equation (3), i.e.,
∆Srep (ejω )/Srep (ejω ) ∆N →0 ∆N/N 2πQ(ejω )e−jN ω [1 − Γ(ejω )] ≈ [1 − Q(ejω )e−jN ω Γ(ejω )][1 − Q(ejω )e−jN ω ] =
sin[π(n − d)] = sinc(n − d) π(n − d)
lim
z −d ≈ H(z) =
jω
Period sensitivity function Sp (e ) evaluates the sensitivity of Srep (ejω ) to the perturbation in N . It is easy to find that if ω = (2k + 1)π/N , Sp (ejω ) = 0, which means that small change of N will not effect Srep at this frequency point. If ω = 2kπ/N , Sp (ejω ) = ∞. It means that Srep is rather sensitive to N at the neighborhood of ω = 2kπ/N , i.e., small perturbation of N will effect the tracking performance dramatically. Where k = 0, 1, ..., N/2 − 1 for N even or k = 0, 1, ..., (N −1)/2 for N odd. Numerical examples show that 1% variation of N will degrade the error suppression ratio from −∞dB to −20dB at fundamental frequency, i.e., k = 1. It can be even worse with k increasing. In real applications, the period N = F/Fs can not always be integer, where F is the fundamental frequency of reference signal and Fs is the sampling frequency, and it is often rounded to the nearest integer. However, from the pervious analysis, the performance is sacrificed. III. F RACTIONAL D ELAY BASED R EPETITIVE C ONTROL In this paper, the Fractional Delay based Repetitive Control (FD-RC) scheme, which is based on the fractional delay filter design theory in digital signal processing [12], is proposed for both integer and non-integer period applications. In this scheme, a fractional delay low-pass FIR filter QF D (z) is introduced to replace the original Q(z) filter in Figure 1 and the performance with non-integer period is improved. Two different QF D (z) design methods are introduced: Lagrange
N X
h(n)z −n
(6)
n=0
where N is the order of filter. It is now desired to determine the coefficients h(n) such that the chosen norm of the frequency-domain error function E(ejω ) = H(ejω ) − Hi (ejω )
(7)
is minimized. B. Lagrange Interpolator Method The error function can be made maximally flat at a certain frequency, typically at ω0 = 0, so that the approximation is at its best close to this frequency. This means that the derivatives of frequency-domain error function shown in Equation (7) are set to zero at this point, that is dn E(ejω ) (8) |ω=ω0 = 0 f or n = 0, 1, .., N dω n The solution of Equation (8) is equal to the classical Lagrange interpolation formula and given in an explicit form as N Y D−k f or n = 0, 1, .., N (9) hli (n) = n−k k=0,k6=n
The case N = 1 corresponds to linear interpolation between two samples. In this case the two coefficients are
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h(0) = 1 − D, h(1) = D
TuC04.4 where
Hence, in this realization, QLI F D (z)
= HLI (z)Q(z)
(10)
where HLI (z) is the z-transformed hli (n) and Q(z) is the zero-phase low-pass filter. Lagrange interpolation method is easy to implement. However, we may find that it is far from the ideal all-pass filter since HLI (ejω ) = 1 only if ω = 0. It means that the sensitivity function (1) is not zero even at low frequency range. Hence, Lagrange interpolation is with limited performance. C. Least Square Method In this method, we combine the design of fractional delay filter z −d and the low-pass filter Q(z) together, i.e., Hid (z) = z −d Q(z)
(11)
where Q(z) is zero-phase low-pass filter with bandwidth ωp . Then Hid (z) is a complex-valued function that specifies both the magnitude and the phase responses as kHid (ejω )k = 1, for ω ≤ ωp kHid (ejω )k = 0, for ω > ωp arg{Hid (ejω )} = −dω, for ω ≤ ωp
(12)
where 0 ≤ ωp ≤ π. It is now desired to determine the coefficient hls such that the L2 -norm of the frequency domain error function E ′ (ejω ) ′
1 π
jω
E (e ) =
+
Z
ωp
|QF D (ejω ) − Hid (ejω )|2 dω
0
1 π
Z
π
|QF D (ejω )|2 dω
(13)
ωp
is minimized. To formulate the solution in a compact form, introduce vector notation as hls = e =
[hls (0) hls (1) · · · hls (M )] [1 e−jω · · · e−jM ω ]
C = Re{eeH }
(14) (15) (16)
Then Equation (13) is rewritten as E ′ (ejω )
=
1 π
Z
Z 1 π C dω π 0 Z ωp 1 [Re{Hid (ejω )}c − Im{Hid (ejω )}s] dω π 0 Z 1 π |Hid (ejω )|2 dω π 0 [1 cos(ω) · · · cos(M ω)]T [0 sin(ω) · · · sin(M ω)]T
P = P1
=
P0
=
c = s =
The error function in Equation (17) is quadratic with a unique minimum-error solution. It can be derived by setting the derivative with respect to hls to zero, then we have hls = P−1 P1
Here is the optimal solution for the least square error function (13). Hence, the lease square realization of QF D (z) is as follows, QLS (19) F D (z) = HLS (z) where HLS (z) is the z-transformed hls Compared with Equation (10), Lease square realization has better performance at low frequency range. Although the matrix inversion in (18) requires lots of computations, it can be calculated off-line. In addition, HLS itself is a lowpass filter and does not need cascade additional low-pass filter Q(z), which helps to reduce the computational cost of repetitive controller. IV. A PPLICATION TO CVCF PWM DC/AC C ONVERTERS The effectiveness of the proposed FD-RC scheme is illustrated by the application to constant-voltage-constantfrequency pulse-width modulated (CVCF PWM) DC/AC converter systems, which are widely used in various power supplies. For converters, output voltage total harmonics distortion (THD) is one important index to evaluate the performance. High THD may lead to communication interference, excessive heating in capacitors and transformers etc. Nonlinear loads, such as rectifier loads, causing periodic distortion, are major sources of THD in AC power systems. The repetitive control scheme [17], [18], [19] has been employed to improve tracking accuracy of PWM converters and significantly reduce THD. The dynamics of the CVCF PWM DC/AC converters in Figure 2 can be described as follows : The sampled-data form of converter model is as follows: x(k + 1) = Ax(k) + Bu(k) y(k) = Cx(k) + Du(k)
ωp
[hls e − Hid (ejω )][hls e − Hid (ejω )]∗ dω
0 Z 1 π [hls e][hls e]∗ dω + π ωp Z 1 ωp = [hls T Chls − 2hls T Re{Hid (ejω )e∗ } π 0 Z 1 π jω 2 [hls T Chls ]dω +|Hid (e )| ]dω + π ωp
= hls T Phls − 2hls T P1 + P0
(18)
(20)
where x(k) = [vc (k) v˙ c (k)]T , u(k) = vin (k), and " # 2 2 1 − 2LTn Cn T − 2CTn Rn A= 2 2 Cn Rn T2 1 − 2LTn Cn + T −2T − T + 2 R2 2Cn n " Ln Cn 2 2Ln Cn2 Rn# B=
(17)
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T 2Ln Cn
T Ln Cn
C = [1 0] D=0
−
T2 2R 2Ln Cn n
TuC04.4 The comparison of these two realizations is shown in Figure 3. It shows that lease square realization has better approximation at low frequency, which coincides with the theoretical analysis in section II. 0
Magnitude (dB)
−5
−10
LI FD
Q
LS FD
Q
−15
−20
−25 0
0.2
0.4
0.6
0.8
1
Normalized Frequency (×π rad/sample)
Fig. 2.
DC/AC Converter System
The corresponding plant transfer function is A B P = C D
Fig. 3.
(21)
i.e., P (z) = C(zI − A)−1 B + D. The parameters for experiment are shown in Table I. parameter Ln Cn Rn E Ts
value 20mH 45µF 18Ω 80V 0.1mS
parameter Lr Cr Rr yd
value 1mH 500µF 50Ω 50V ,60Hz
TABLE I PARAMETERS OF THE SYSTEM
Plug (22) and (23) into Equation(1), we have the closedloop sensitivity function. Figure 4 shows the sensitivity function comparison between conventional RC and Least square FD-RC. Conventional RC (dashed line) places the first notch at 59.88Hz and the attenuation ratio at 60Hz is about -60dB; In the sensitivity function of Least square FD-RC (Solid line), the first notch appears exactly at 60Hz and Srep (ejω ) ≈ 0 with ω = 120π. This figure shows the effectiveness of proposed fractional delay based repetitive controller with least square realization. Figure 5 shows the comparison between least square and Lagrange Interpolation implementations. Both of the two implementations can exactly reject the disturbances at 60Hz and the harmonics. However, least square method has better performance since it has deeper notches at 60Hz and harmonics, which is also illustrated in Figure 3.
The system is designed to track an ideal sine wave with 60Hz frequency and the sampling rate is 0.1ms. Hence, an non-integer delay 500/3 is required. In conventional RC scheme, it will be rounded to the nearest integer, i.e., N = 167. Other repetitive controller parameters are chosen as follows: L = 2, Φ(z) = 1 and Q = (z + 8 + z −1 )/10. On the other hand, in our proposed FD-RC scheme, N = 166, d = 2/3, ωp = 1.6π and a 4th order fractional delay low-pass FIR filter QF D (z) will be designed. The feedback controller design follows the Three-Step Robust Repetitive Controller (TSRRC) design procedure [20], [21] and the details are omitted here. When QF D is designed by Lagrange Interpolation method, we have QLI F D (z)
20
0
Magnitude (dB)
−20
−40
−60 −20 −80 −70 −100
= HLI (z)Q(z) = −0.0111 − 0.0333z −1 + 0.4889z −2 + 0.5000z −3 +0.0556z −4
LS QLI F D and QF D Comparison
(22)
When QF D is designed by Least square method, we have
−120 59
−120 1 10
2
10
60
61
3
10
Frequency (Hz)
Fig. 4.
Sensitivity Function Comparison
The experiment setup of the PWM converter system consists of DSPACE (DS1102) DSP development toolkits, QLS F D (z) = HLS (z) H-bridge IGBT switches converter, oscilloscope and etc. = 0.0292 − 0.1518z −1 + 0.4681z −2 + 0.6839z −3 Figure 6(a), 7(a) and 8(a) show the steady state output −0.0294z −4 (23) voltage and load current waveforms comparison with rectifier
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20 60
← V
c
40
Output Voltage (V)
Magnitude (dB)
0 −20 −40 −60
20
← I
o
0
−20
−40
−40 −80
−60 3
3.0083
3.0167
Time (s)
−80 −100 −120 59
−120 1 10
2
10
60
(a) Conventional RC Controlled Output Voltage and Load Current
61
3
10
Frequency (Hz) 0.09
Sensitivity Function Comparison
0.08
V. C ONCLUSION In this paper, we have shown that the newly proposed fractional delay based repetitive control scheme for both integer and non-integer delay cases. By using fractional delay filter design theory in digital signal processing, two different structures are introduced and the performances are compared. The Lagrange Interpolation method is easy to design and implement whereas Least square method has better performance. The application to the PWM DC/AC converters illustrates the design procedure of the proposed method in details. Experiments of PWM converter system are provided to demonstrate the effectiveness of the proposed method.
Harmonics Magnitude
0.06 0.05 0.04 0.03 0.02 0.01 0 −500
0
500
1000
1500
2000
2500
3000
Frequency (Hz)
(b) Conventional RC Controlled Output Voltage Harmonics Spectrum Fig. 6.
Conventional RC Steady State Response with Rectifier Load
60
← V
c
40
Output Voltage (V)
load. Less waveform distortions can be found in FD-RC controlled voltage. Figure 6(b), 7(b) and 8(b) show the harmonics spectrums of output voltages. The THD with conventional RC is 9.28% while with LS FD-RC is 1.52% and with LI FD-RC is 1.67%. It is clear that the FD-RC controlled voltage contains less harmonics than conventional RC scheme. The LS FD-RC is a little bit better than LI FDRC. The transient response of tracking error convergence with conventional RC and FD-RC are shown in Figure 9 10 and 11, respectively. The peak of error has been forced to 8V with conventional RC and to 1V with proposed FD-RC. Since FD-RC admits larger learning gain, the transient state lasts less than 0.1s, which compared with 0.3s in conventional RC controlled output. It is clear that the proposed FDRC method shows much better tracking performance over conventional scheme.
THD=9.28%
0.07
20
← I
o
0
−20
−40
−60 3
3.0083
3.0167
Time (s)
(a) LS FD-RC Controlled Output Voltage and Load Current
−3
9
x 10
8
Harmonics Magnitude
Fig. 5.
R EFERENCES
THD=1.52%
7 6 5 4 3 2 1
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0 −500
0
500
1000
1500
2000
2500
3000
Frequency (Hz)
(b) LS FD-RC Controlled Output Voltage Harmonics Spectrum Fig. 7.
Least Square FD-RC Steady State Response with Rectifier Load
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Output Voltage (V)
60
← V
c
Output Voltage (V)
40
20
← I
o
0
10 5 0 −5 −10
−20 1
−40
1.05
1.1
1.15
1.2
Time (s)
−60 3
3.0083
3.0167
Time (s)
Fig. 11.
LI RC controlled tracking error history
(a) LI FD-RC Controlled Output Voltage and Load Current
0.014
Harmonics Magnitude
0.012
THD=1.67%
0.01 0.008 0.006 0.004 0.002 0 −500
0
500
1000
1500
2000
2500
3000
Frequency (Hz)
(b) LI FD-RC Controlled Output Voltage Harmonics Spectrum
Output Voltage (V)
Fig. 8. Lagrange Interpolation FD-RC Steady State Response with Rectifier Load
10 5 0 −5 −10
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
Time (s)
Output Voltage (V)
Fig. 9.
Conventional RC controlled tracking error history
10 5 0 −5 −10
1
1.05
1.1
1.15
Time (s)
Fig. 10.
LS RC controlled tracking error history
1.2
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