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Galois Field Circuits and Realization of Multiple-Valued Logic Functions

by

Zeljko Zilic

A thesis submitted in conformity with the requirements for the degree of Master of Applied Science in the Department of Electrical and Computer Engineering University of Toronto September 1993

© Copyright by Zeljko Zilic, 1993

Galois Field Circuits and Realization of Multiple-Valued Logic Functions Abstract This thesis deals with several aspects of the utilization of finite (Galois) fields in multiplevalued logic (MVL). Current-mode CMOS circuits are proposed that realize operations in Galois fields with four elements. A synthesis technique with such circuits and a transform method are presented; they are based on the Galois field polynomial representation. Methods for obtaining such representations are discussed in two steps, dealing with one-dimensional and multidimensional cases separately. A new method is developed for representation of single variable functions. It is limited to fields of small sizes (2 to 4), which is acceptable because only these fields are readily implementable with today’s MVL technology. The method provides a natural way of dealing with incompletely specified functions and has better computational properties than other similar methods. A natural extension of the method to the multidimensional case is derived. The multidimensional representation algorithm has all the properties of the fast discrete transforms.

Acknowledgements

First and foremost, for his guidance, help and encouragement, I thank my advisor, Zvonko G. Vranesic. Not only did he introduce me to the multiple-valued logic and switching theory, but by serving as a positive example, he taught me how to perform research work. Essential is his material support, guidance through some of the very difficult moment during my studies, and an optimism that he tried to imbue on any occasion. Without him, nothing like this thesis could happen. I thank Prof. Molle, Prof. Rose and Prof. Zaky for their understanding while studying in Toronto. Many credits go to Professor Leo Budin in Zagreb who showed me the basics of the modern Computer Engineering. Many students helped me in many ways: Uma, Mark, Keith, Mike, John, Gennady and Steve are just a few of them.

1 Prologue 1 1.1 1.2 1.3

Motivation 1 Multiple-Valued Logic and Current-Mode CMOS 2 Polynomial Representation and Transform Methods 3 1.3.1 Algebraic Realization of Discrete Functions 3 1.3.2 Transform Methods 4 1.3.3 Reed-Muller Transform 5 1.3.4 Various Reed-Muller Forms 5 1.3.5 Historical Remarks 7

1.4

Thesis Overview 8

2 Current-Mode CMOS Circuits 9 2.1 2.2 2.3 2.4

Basics 9 Current-Mode MVL Primitives 10 Current Mirrors 13 Synthesis with Current-Mode Circuits 15 2.4.1 Cost-Table Approach 15 2.4.2 Pass Transistor Networks 16 2.4.3 Direct Cover Method 19

3 Current-mode Galois Field Circuits 21 3.1 3.2 3.3

Motivation 21 Galois Fields 22 Galois Field Circuits 23 3.3.1 GF4 Adder 23 3.3.2 GF4 Multiplier 27 3.3.3 Other GF4 Circuits 28

3.4 3.5 3.6

GF16 Circuits 32 Circuit Performance 34 Concluding Remarks 36 3.6.1 What Have We Learned about the MVL Synthesis? 36

4 Small Galois Fields Representation Algorithm 39 4.1 4.2 4.3 4.4

Background 39 Polynomial Expansion - the Basic Algorithm 41 Newton Interpolation Polynomial 43 Direct Method for Polynomial Determination 44 4.4.1 Performance 50 4.4.2 Software Implementation 50

4.5 4.6 4.7

Hardware Implementation 51 Hardware Polynomial Evaluation 53 Concluding Remarks 56

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5 Multidimensional Representation Algorithm 58 5.1 5.2

Extending the One-Dimensional Algorithm 58 History of the Subject 59 5.2.1 Emphasis on Implementation 59 5.2.2 Emphasis on Transforms 60

5.3

Our Approach 63 5.3.1 Functions of Two Variables 64 5.3.2 The General Case 66

5.4

Implications of Our Approach 71 5.4.1 Implications to the Binary Case 71 5.4.2 Incompletely Specified Functions 71 5.4.3 Remarks on the Fast Fourier Transform 73 5.4.4 Miscellaneous - Future Research 74

5.5 5.6

Software Implementations 75 Conclusions 76

6 Concluding Remarks 77 Appendix A: VHDL Description of GF4 Circuits 80 Appendix B: C++ Code for One-Dimensional Algorithm 92

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Chapter 1

Prologue

This thesis deals with multiple-valued logic (MVL) from an algebraic point of view. The basic idea is that a discrete function can be represented as a purely algebraic object, such as a polynomial. Interestingly, this idea was presented first here in Toronto, at the 1924 International Congress of Mathematicians [9]. Since then, many aspects of this approach have been discovered, some of them dealing with function realization, but the predominant recent activity has been directed towards transform methods, not unlike Laplace or Fourier transforms in real analysis. This thesis deals with the basics of all these approaches, reexamining the underlying mechanisms and pointing towards the implementations that exploit some properties of the objects that are dealt with. Since the work is motivated by the implementation, a lot of attention is paid to examining the technology and circuits that are suitable for supporting our approach.

1.1 Motivation The development of multiple-valued logic is stalled by both technological and conceptual factors. In the technology domain, robust, cheap and reliable multiple-valued circuits are still not available, although some technologies are very close to this goal. However, a more serious problem is the absence of efficient synthesis methodologies. One basic difficulty is that there is 1

still no clear methodology for extending Boolean logic to the multiple-valued domain. Researchers have been working with many theories, such as lattice algebra [27], Post algebra [118] and many technology dependent ad-hoc proposals for discrete sets with a meaningful set of operators that will yield an efficient foundation for logic synthesis. Even though there exist significant results [94], the design techniques are usually partial and driven by a particular technology. This thesis is an attempt to reduce the gap between the theoretical and practical design issues. The Galois field [69] polynomial representation [79], [92], [7] is considered and currentmode CMOS circuits are developed that allow such realization of multiple-valued functions. Next, we will give the motivation for both current-mode CMOS technology and Galois field representation.

1.2 Multiple-Valued Logic and Current-Mode CMOS Today, CMOS is a well developed and stable technology platform with a huge fabrication base. There have been many attempts to derive a reasonable MVL technology based on the ordinary (voltage-mode) CMOS. The biggest obstacle to acceptance of any such technology lies in the fact that for encoding more than two levels of logic the available room for a voltage swing is decreased. One possible way to overcome this limitation is to use the current-mode techniques, which use current as a signal carrier, either alone or in combination with voltage. Current-mode techniques have been used extensively in analog design for two decades; recently they have also been used in the CMOS digital design. For example, due to the advantages in transmission line propagation delay [101], many modern SRAMs have current-sensing amplifiers in the output stage [57]. It is expected that the advantages of current-mode techniques will become even more important with increased speed requirements and decreased power supply voltages [36], [103].

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The current-mode approach has been considered for MVL circuits for two decades. In the seventies and eighties, bipolar I2L technology [28] held promise, but it became less interesting with the advancement of CMOS. Current-mode CMOS [26] is the most promising MVL technology today. It is difficult to predict what kind of current-mode technology will prevail in the future. For example, Smith and Gulak [103] predict a greater role to be played by current-mode BiCMOS technology.

1.3 Polynomial Representation and Transform Methods This thesis considers two concepts in circuit synthesis and analysis that are in our case related: realization of circuits by algebraic means and utilization of transform methods. We will outline them first and discuss how they are related in our case. A short historical overview will illustrate the development of these two concepts.

1.3.1 Algebraic Realization of Discrete Functions In everyday arithmetic we use a few basic operations to realize all the necessary functions. Mathematical formalization of these methods leads to the notion of algebraic structures [72] that are defined as a set “armed” with one or more operations in that set. Only two basic operations over numbers, multiplication and addition, are enough for us to develop the whole mathematical universe. Such a structure, that has two invertible operations is called a field. Our goal is to deal similarly with discrete functions, not necessarily the arithmetic ones. For this purpose, we have to deal with the algebraic structure of a finite, or Galois, field. It can be shown that the two basic Galois field operations indeed form a functionally complete set of operations for realizing functions over discrete domains [125]. Therefore, Galois field operations suffice for the realization of MVL circuits. The important question is how to realize all the functions needed using the basic operations. Some functions can be obtained by simply inverting and composing the basic ones; however, most of the functions must be interpolated by some standard procedure. Polynomial

3

interpolation (the terms representation and expansion are also used) is one such procedure. Once having a polynomial, it is routine to realize it using the basic field operations - addition and multiplication. Therefore, Galois field polynomial representation, as a general procedure for realizing arbitrary discrete functions, will be of our foremost interest in this thesis. This algebraic framework can also be extended to sequential logic. See [43], [52], [69] and [89] for an overview of the results obtained using this approach. The most notable results are based on the link with the general systems theory that can be easily accomplished using Galois fields.

1.3.2 Transform Methods Transform methods have been used in many disciplines. They are [75] mappings from functional spaces, or sets of functions, into a transform domain. Such a domain must possess the property that all functions can be uniquely represented by combining some set of basic elements in the transform domain. Mathematically, this requires that the transform domain possesses the structure of a vector space. A transform is performed in such a way that for each function a proper mix (linear combination) of vectors in the transform space is found. In switching theory we are concerned with the synthesis of functions, optimization of circuits, testing, decompositions, and so on. Generally, when dealing with logic functions, the exhaustive search approaches are computationally expensive. Transform methods promise that at least some of the problems (like the sequential synthesis application described in [113]) can be handled in a better way. This is especially important when the size of a function increases. Transforms have also been shown to be useful in classification, complexity estimation [15], decompositions [90], machine circuit learning [70] and fault detection [61]. Transform methods have a long history in binary logic; they are summarized in monographs like [60], [56] and texts like [65]. There are several transforms [60], [56] that can be used in switching theory for the realization of Boolean functions. Transforms such as Walsh, Hadamard and Haar, are defined by means of a set of orthogonal waveform functions that can take

4

only two values. There exists an extension to the MVL case, which is the Christensen transform [60]. However, the definition of these particular transforms makes it impossible to find a unified approach for transforming both binary and MVL functions.

1.3.3 Reed-Muller Transform A possible approach to unify binary and MVL transforms is to use the polynomials over arbitrary Galois fields as a set of representation vectors in the transform domain. Indeed, it can be shown that the polynomials over Galois fields form a vector space. This transform is traditionally known as the Reed-Muller transform, and has its origins [81] in Boolean logic, where it is defined as a canonical exclusive sum of products form. Only two operations, binary AND and XOR are used to represent any Boolean function. These two operations, it will be shown later, form a Galois field with two elements, GF2. Therefore, the binary Reed-Muller transform is a special case of a Galois field polynomial representation [91]. A distinct feature of the Reed-Muller (RM) transform, compared to other transforms, is the fact that the transform domain is the same as the domain of the logic functions. This means that the transform can be used also for implementation purposes, to derive logic circuits that can implement any function. For two-valued functions, the Reed-Muller transform will yield a set of coefficients of canonical AND-XOR representation that is directly implementable. The only negative consequence of this duality is the fact that the relevant research (especially in the MVL domain) has often been artificially separated.

1.3.4 Various Reed-Muller Forms To achieve simpler implementations of circuits presented in the RM representation, several extensions over the basic form are possible. We will describe these forms shortly. The basic Reed-Muller form in binary logic can be extended by consistently inverting some of the variables (changing the polarity) in the polynomial [1]. The basic form is also known as a Positive Polarity Reed-Muller Expression (PPRME) and the latter is called a Fixed Polarity

5

Reed-Muller Expression (FPRME). In the case of MVL functions, the polarity change is generalized to an additive transformation, which is obtained by adding some number to a particular variable. In [46], it is shown how the multiplicative and exponential transformations can be used to augment the RM to the FPRME in the MVL case. Another class of expansions can be called “mixed polarity”, where any variable can inconsistently change the polarity throughout the expression. This form was introduced in [22], and it is very often is referred to as a Generalized Reed-Muller Expression (GRME). Related are the Kronecker Expressions that have the general EXOR-sum-of-products shape, but do not follow the polynomial expansion procedure. For example, it is possible to have two products of the highest degree, which is not permitted by the polynomial form. The most general of these classes are called the EXOR-sum-of-products (ESOP) in [96] and “ring expansions” in [27]. Good overviews of these forms are given in [96] for the binary case and in [27] and [50] for the MVL case. These forms are interesting when considering the implementations. By changing some of the polarities, consistently or inconsistently, the total expression can be “minimized”, which usually means that the total number of literals is minimized. There has been a lot of work done in this area. For an early overview see [27], more recent work is reviewed in [96], [111] and [74]. We are concerned in this thesis only with the basic Reed-Muller transform which is included in all the classes, and which is the only uniquely canonical form amongst them. Minimization is important when implementing binary designs with XOR circuits, and in the MVL case, there is still a lot of work to be done before these minimization methods become as important as in the binary domain. Many practical binary designs have more economical implementations when XOR circuits are present as building blocks. For example, the arithmetic circuits used in [96] require fewer product terms when implemented with AND-XOR than standard PLAs. In [98], a similar result is shown for randomly generated functions, strengthening the widely held conjecture that AND and XOR circuits are very powerful operations. Some authors [35], [7] conjecture that

6

Galois field circuits (that naturally generalize AND and XOR circuits) have the same position amongst MVL operations. It is difficult to prove or disprove such a conjecture, but we note a recent result [14] that shows that the Galois circuits are just as powerful as the threshold circuits in producing area and delay efficient designs. It is known that the threshold circuits are one of the most effective building blocks. Besides promising cheaper implementations, XOR (and, consequently, Galois field) circuits offer the opportunity to build easily testable designs [61].

1.3.5 Historical Remarks The original papers that deal with the algebraic representation of MVL functions fall clearly into two categories. The first of these deals with the idea of a direct implementation using the polynomials over Galois fields, while the second deals with the transform aspects, namely with the variants of the Reed-Muller transform. The key idea dates back to 1924 [9], but at that time it had only a theoretical significance. Later, two papers by Reed [93] and Muller [81] defined the basics for their transform in the binary domain. In 1959, Akers [1] tried to derive an analogon to Taylor-Maclaurin expansion in real analysis that enables performing the analysis of Boolean functions. From that moment, we will trace only the MVL-related contributions. In 1969, Menger [77] considered the problem from the MVL point of view and showed how to find a Galois field polynomial representation in the case of single-variable functions. Independently, Moisil published a similar study [79] that dealt with the algebraic representation of logic functions. Benjauthrit and Reed expanded Menger’s approach to functions of several variables [7], but their procedure was computationally tedious. More results in that direction were obtained by Pradhan [92] and Benjauthrit and Reed [8]. The first approach to deal with incompletely specified functions was Wesselkamper’s utilization of Netwon’s method [120]. Further results were achieved in minimization, but we will not follow these developments here. In the transform-oriented research community, the first steps were done in [45], [46], by examining the idea of using the Reed-Muller transform in MVL logic design. However, little

7

attention has been paid to the underlying mathematical mechanisms, and that situation changed only to adopt the “butterfly” method in [48], [49]. There was little work done on incompletely specified functions, although the minimization problems were covered in [33], [51] and several other publications. Recently, the interest in transform-based methods, and especially in the Reed-Muller transform, has been revived [114], [116], due to the link between the synthesis using XOR circuits and various Reed-Muller forms. New generations of programmable logic devices, such as the one produced by Xilinx [123], have XOR circuits besides OR circuits in the second-level logic array. Moreover, using modern lookup-table based Field Programmable Gate Arrays (FPGAs), XOR logic circuits have become readily available and as expensive as OR and AND gates. The promise of cheaper and easily testable implementations using XOR circuits promotes these methods as an alternative to classical synthesis approaches.

1.4 Thesis Overview The thesis is organized as follows. The relevant MVL implementation technology is presented first. In Chapter 2, current-mode CMOS technology is described, together with the available synthesis techniques. Chapter 3 defines the algebraic object of a finite (Galois) field and gives an implementation of circuits that perform the operations in one instance of such object, GF4, which is the Galois field with four elements. Chapter 4 presents the problem of Galois field polynomial representation and gives an algorithm pertinent for small fields. The extension of the algorithm for derivation of the representation of functions in several variables is given in Chapter 5, together with some comments that link the transform approach, polynomial representation and several other terms that deal with essentially the same problem, but which have been treated separately in the literature. Appendix A contains the VHDL description of the arithmetic GF4 circuits, while Appendix B shows an implementation of the one-dimensional representation algorithm in the C++ programming language.

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Chapter 2

Current-Mode CMOS Circuits

This chapter contains the description of the current-mode circuits used in this thesis. The basic notation is presented, together with some physical constants that define the circuits. The chapter also contains the description of the design techniques for MVL design that can be useful when designing the current-mode circuits.

2.1 Basics Current-mode CMOS technology is the predominant multiple-valued logic (MVL) technology being considered today. Current-mode CMOS circuits have been studied for a decade. Introduced in 1983, by Freitas and Current [40], [41], they have proven to be useful in many successful designs, including arithmetic circuits [62], [24], analog-to-quaternary converters [25] and MVL PLAs [88]. Recently, some promising features of current-mode circuits regarding switching noise generation [3] and transmission line propagation delay [101], [130] have been reported in the literature. In view of this, the current-mode CMOS technology was a natural choice for the implementation of our MVL circuits.

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Current-mode circuits are analog in nature. There is no naturally available stable state because the currents flowing can take on any value. This kind of logic circuits is non-restoring, and it is often necessary to introduce some correcting circuits that will quantify the amount of current at any stage. The current can also have two positive directions. It is possible to exploit them both, but in our designs we will use only one current polarity. The magnitude of the current will be defined in accordance with a common quaternary convention. Let the magnitude of the basic current be I. Then, the logic values {0,1,2,3} will be represented by currents with magnitudes {0, I, 2I, 3I}, respectively. Throughout our designs, the basic current will be defined as: I = 20µA . Other values can be used, provided that transistors operate in the desired mode of operation. A higher value of I increases the speed of the circuit, but also increases its power consumption. The value chosen here is very usual in the literature.

2.2 Current-Mode MVL Primitives Recent experience shows that current-mode circuits are attractive for the implementation of MVL functions, particularly when the radix is greater than 3. Most of the circuits and synthesis techniques in the literature have been intended for the 4-valued environment [21], [58], [66]. Current-mode circuits offer several advantages, but they also have some disadvantages. Perhaps the most important of these are the ease of summation of signals and the difficulty in distribution of signals caused by the fanout being equal to one. In practice, it is useful to augment currentmode circuits with some intermediate voltage-mode circuits, which often results in more effective designs. Figure 2.1 gives the basic blocks used in our design. All of these blocks have been used before [21], [58], [66]. Here, we will only summarize their characteristics and describe our implementation. Currents are summed by means of a simple wired connection. This is the cheapest operation and the goal in the design of the current-mode MVL circuits is to maximize the usage of this operation.

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Name Sum

Log. Expression

Symbol

y=x1+x2+ ... +xn

x1 x2 ...... xn

Circuit Realization y

x2 ...... xn

y

Vdd Current Source

Pref

c

y=c

C Nref

C x

y1

To

T1

y1 x

N

Current

yi=

...

...

Tn

yn

x if x>0 0 if x=K

z=

y

K

K

Pref

z

Nref y

x

High if x>=K

x

Low if xB Vdd 1

A/B

A>0 B−A>1

1

Figure 3.12 Pass Transistor Logic for GF4 Division The exponentiation function can be derived in a similar way. Starting from the definition given in Figure 3.13 (note that 00 is treated here as a “don’t care” and assigned a value of zero), the function can again be realized as a network of pass transistors controlled by literals. The defining equation is: AB = A

[ 1, 3 ]

+A

[ 2, 3 ]

B

[ 1, 2 ]

( 1 + ( A + B ) { 4} )

and the current mode realization requires 25 transistors. The propagation delay is affected by only one level of current mirrors (since there is no current subtraction). Figure 3.14 shows the pass

30

B

A

A / 0 1 2 3 0 0 1 1 1 1 0 1 2 3 2 0 1 3 2 3 0 1 1 1

B

Figure 3.13 Exponentiation in GF4 transistor logic for the circuit. All the circuits described above have been compared to their binary counterparts and to a current-mode implementation using the method proposed in [64] and [66]. In the binary case, functions have been mapped using a library-based technology mapper described in [32]. The target architecture is the macrocells [73]. It is supposed that XOR circuits consist of ten transistors and NAND and NOR circuits consist of four transistors. The following table shows the number of transistors required for each implementation. The first column contains the transistor count for circuits presented here. The second column contains the cost of the MVL multiplexer-based realization, as defined in [64]. The third column shows the results of mapping to binary macrocells. Table 3.1 GF4 Operations- Transistor Count Comparison Op

Ours

Lei

Binary

+

29

69

20

*

19

53

50

/

29

55

50

^

25

45

44

31

The GF4 adder is the only circuit that requires more transistors in the current-mode implementation. The reason is in that the binary implementation can be realized by using only two XOR circuits. Vdd 1

A+B