GaN

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 9, SEPTEMBER 2006

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Monolithically Integrated Enhancement/Depletion-Mode AlGaN/GaN HEMT Inverters and Ring Oscillators Using CF4 Plasma Treatment Yong Cai, Zhiqun Cheng, Wilson Chak Wah Tang, Kei May Lau, Fellow, IEEE, and Kevin J. Chen, Member, IEEE

Abstract—Fabrication and characterization of AlGaN/GaN HEMT inverters and ring oscillators utilizing integrated enhancement/depletion-mode (E/D-mode) AlGaN/GaN HEMTs are presented. The core technique is a CF4 plasma treatment that can effectively convert a D-mode AlGaN/GaN heterostructure to an E-mode heterostructure. A significant advantage of the plasma-treated E-mode HEMTs is that the gate current is reduced in both reverse- and forward-bias regions due to the effectively enhanced barrier height induced by the negatively charged fluorine ions in the AlGaN barrier. As a result, the input voltage swing is expanded by about 1 V for the E-mode HEMT, enabling convenient input/output logic level matching for multistage logic circuits such as ring oscillators. The fabricated 17-stage direct-coupled field-effect transistor logic ring oscillator using the 1-µm-gate technology can operate properly at a larger supply voltage of 3.5 V, and a minimum propagation delay of 130 ps/stage is achieved. Index Terms—AlGaN/GaN, depletion mode (D-mode), directcoupled field-effect transistor (FET) logic (DCFL), enhancement/depletion (E/D) inverter, enhancement mode (E-mode), fluorine ions, gate current, HEMT, plasma treatment, post-gate rapid thermal annealing (RTA), ring oscillator.

I. INTRODUCTION

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ITH the unique material characteristics associated with wide-bandgap III-nitride materials, AlGaN/GaN HEMTs have the potential to be used to construct ICs to perform reliable operations at high temperature that have not be possible for silicon- or GaAs-based technologies [1]–[3]. The high-temperature digital ICs can provide the enabling technology for intelligent control and sensing units used in automotive, aviation, chemical reactor, and oil exploration systems [4]. Due to the lack of p-channel AlGaN/GaN HEMTs, a circuit configuration similar to that based on CMOS cannot be implemented yet. Using n-channel HEMTs, direct-coupled

Manuscript received March 14, 2006; revised June 8, 2006. This work was supported in part by the Hong Kong Research Grants Council and the National Science Foundation of China under Grant N_HKUST616/04, and in part by a Competitive Earmarked Research Grant 611805. The review of this paper was arranged by Editor M. Anwar. The authors are with the Department of Electrical and Electronics Engineering, Hong Kong University of Science and Technology, Kowloon, Hong Kong (e-mail: [email protected]; [email protected]). Digital Object Identifier 10.1109/TED.2005.881002

Fig. 1. DCFL circuit schematics of (a) E/D inverter and (b) ring oscillator.

field-effect transistor (FET) logic (DCFL), as shown in Fig. 1, which features integrated enhancement/depletion-mode (E/Dmode) HEMTs, offers the simplest circuit configuration [5]. While high performances have been readily achieved in Dmode AlGaN/GaN HEMTs [6], [7], it is challenging to fabricate E-mode AlGaN/GaN HEMT [8] with high-performance characteristics including high transconductance, low on-resistance, low knee voltage, and large input voltage swing, all of which are required for digital applications. For a long time, the development of GaN-based digital ICs had been hindered by the lack of compatible integration process for both D-mode and E-mode AlGaN/GaN HEMTs. As a tradeoff, Hussain et al. [9] used an all-D-mode-HEMT technology and buffered FET logic (BFL) configuration to realize an inverter and a 31-stage ring oscillator that includes 217 transistors and two negative voltage supplies. Recently, with the development of low-damage Cl2 -based inductively coupled plasma reactive ion etching (ICP-RIE) technology [10] and a novel self-aligned E-mode AlGaN/GaN HEMT technology based on fluoride-based plasma treatment and post-gate rapid thermal annealing (RTA) [11], monolithic integration of E/D-mode GaN HEMTs has been successfully demonstrated by two research groups [12], [13]. Based on lowdamage Cl2 -based ICP-RIE technology, Micovic et al. [12] applied the technology of two-step gate recess etching and used plasma-enhanced chemical vapor deposition (PECVD)grown SiN as the gate metal deposition mask to fabricate the E-mode GaN HEMTs, which are integrated with the D-mode GaN HEMT. They showed a propagation delay of 127 ps/stage at a drain bias voltage of 1.2 V for a 31-stage DCFL ring oscillator with the 0.15-µm-gate technology. We previously reported [11] a technique featuring fluoride-based plasma treatment and

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Fig. 2. Epitaxial structure of the HEMTs used in this work.

post-gate annealing to realize high-performance self-aligned Emode AlGaN/GaN HEMTs. The fabricated E-mode devices showed comparable performance with the D-mode devices fabricated on the same epi-wafer. Based on this technique, a new technology of monolithic integration of E/D-mode AlGaN/GaN HEMTs for digital ICs has been demonstrated [13]. Using a 1-µm-gate technology, a 17-stage DCFL ring oscillator with an output buffer stage was realized with 36 transistors and only one positive voltage supply. When biased at 3.5 V, the oscillation frequency is 225 MHz, corresponding to a delay of 130 ps/stage. Compared to the technology of two-step gate recess etching, the technology of fluoride-based plasma treatment saves a mask for fabricating GaN-based digital ICs. In this paper, we present detailed characteristics of the DCFL circuits fabricated by the fluoride-based plasma treatment. For inverters, the dependences of circuit performance (e.g., logic levels, noise margins) on physical design parameters (e.g., drive/load ratio, β) and supply voltage were characterized. For ring oscillators, delay time and power consumption were measured for various β and supply voltage. One distinctive advantage of the plasma treatment technique, namely the effective enhancement of the gate Schottky barrier, was also discussed with a physical explanation. Such an enhancement plays the important role in allowing large supply voltage in the circuits, which is shown to improve the noise margin and shorten the gate delay. The large input voltage swing also eliminates the need for logic level adjustment between adjacent stages in ICs. II. DEVICE STRUCTURE AND FABRICATION As shown in Fig. 2, the AlGaN/GaN epitaxial heterostructures used in this work include the following: 2.5 µm GaN buffer layer and channel, 2 nm undoped Al0.25 Ga0.75 N spacer, 15 nm Al0.25 Ga0.75 N carrier supply layer with Si doping at 1 × 1018 cm−3 , and 3 nm undoped Al0.25 Ga0.75 N cap layer. The structures were grown on sapphire substrate in an Aixtron 2000 HT metal–organic chemical vapor deposition (MOCVD) system. Detailed monolithic integration procedures have been given in [13], and the process flow is shown in Fig. 3. The mesa and source/drain ohmic contacts were formed simultaneously for both E-mode and D-mode HEMTs, as shown in Fig. 3(a) and (b). The D-mode HEMTs’ gate electrodes were then formed by photolithography, metal deposition, and liftoff [Fig. 3(c) and (d)]. After defining the patterns of E-mode HEMTs’ gates and interconnections, samples were treated by CF4 plasma at a source power of 150 W for 150 s in an STS RIE system [Fig. 3(e)], followed by gate metallization

Fig. 3. Schematics showing the process flow of monolithic integration of E-mode and D-mode HEMTs for an inverter. (a) Mesa etching. (b) Ohmic contacts formation. (c) D-mode HEMT gate definition. (d) D-mode HEMT gate metallization. (e) E-mode HEMT gate definition and plasma treatment. (f) E-mode HEMT gate metallization and interconnections.

and lift-off for the E-mode HEMTs. Inspected by atomic force microscope (AFM) measurements, the AlGaN barrier thickness was reduced by 0.8 nm after the plasma treatment. Next, a postgate thermal annealing was conducted at 450 ◦ C for 10 min [Fig. 3(f)]. The CF4 plasma treatment is the key step that converts the treated GaN HEMT from D-mode to E-mode [11]. The magnitude of threshold voltage shift depends on the treatment conditions, e.g., plasma power and treatment time [14]. The post-gate annealing is employed to recover the plasma-induced damages in AlGaN barrier and channel. In principle, the higher

CAI et al.: E/D-MODE AlGaN/GaN HEMT INVERTERS AND RING OSCILLATORS USING CF4 PLASMA TREATMENT

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TABLE I GEOMETRY PARAMETERS OF INVERTERS AND RING OSCILLATORS

is the annealing temperature, the more efficient is the damage repair. However, in practice, the post-gate annealing temperature should not exceed the highest temperature (∼ 500 ◦ C, in our case) that the gate Schottky contact can endure. It was found that the D-mode HEMTs’ characteristics remain the same after the annealing, whereas the E-mode HEMTs’ drain current density increases significantly. The post-gate annealing was found to have no effect on the threshold voltage shift introduced by the plasma treatment [11]. For the E/D inverter and the ring oscillator, the most important physical design parameter is the drive/load ratio, β = (Wg /Lg )E-mode /(Wg /Lg )D-mode . Several E/D inverters and ring oscillators with β varying from 6.7 to 50 were designed and fabricated on the same sample. The geometric parameters of each design are listed in Table I. Discrete E-mode and D-mode GaN HEMTs with 1 × 100 µm gate dimension were simultaneously fabricated on the same sample for dc and RF testing. III. RESULTS AND DISCUSSION A. Characteristics of Discrete E/D-Mode HEMTs DC current–voltage (I–V ) characteristics of discrete devices were measured using HP4156A parameter analyzer. The transfer characteristics of the E/D-mode HEMTs are plotted in Fig. 4(a). On-wafer small-signal RF characterization of discrete devices were carried out in the frequency range of 0.1–39.1 GHz using Cascade microwave probes and an Agilent 8722ES network analyzer. The measured parameters of E/D-mode HEMTs are listed in Table II. The threshold voltage (Vth ) and peak transconductance (gm,max ) are 0.75 V and 132 mS/mm for the E-mode HEMT and −2.6 V and 142 mS/mm for the D-mode HEMT. The relatively low peak current density of 480 mA/mm for D-mode HEMT is due to relatively low Al composition of 25% and relatively low doping density of 1 × 1018 cm−3 in AlGaN barrier layer. Different from the AlGaN/GaN HEMTs used for RF/microwave power amplifiers, the digital ICs are less demanding on the current density. As shown in Fig. 4(b), a low knee voltage of 2.5 V is obtained for E-mode HEMTs. At a gate bias of 2.5 V, we obtain an on-resistance of 7.1 Ω · mm for the E-mode HEMT, which is the same as that for the D-mode HEMT at the same saturation current level. An important observation is that the gate current in both the reverse- and forward-bias conditions is significantly reduced in the E-mode HEMT [Fig. 5(a)] compared to the D-mode HEMT. The mechanism of this gate current suppression is the modulation of the potential in the AlGaN barrier by the negatively charged fluorine ions that are introduced by the plasma treatment. The conduction-edge band diagrams simulated for both D- and E-mode HEMTs by solving Poisson’s equation and Fermi–Dirac statistics. For the

Fig. 4. DC I–V (a) transfer characteristics. (b) Output characteristics of D-mode and E-mode AlGaN/GaN HEMTs with Lg = 1 µm. TABLE II PERFORMANCES OF FABRICATED E- AND D-MODE AlGaN/GaN HEMTS

simulated conduction band of E-mode HEMTs, the profile of fluorine distribution is approximated by a linear function that features a maximum F− concentration of 3 × 1019 cm−3 at the AlGaN surface and reaches zero (negligible) at the AlGaN/GaN interface. A total F− sheet concentration of ∼ 3 × 1013 cm−2 is sufficient to compensate not only the Si+ donors’ concentration of ∼ 3.7 × 1012 cm−2 but also the piezoelectric and spontaneous polarization-induced charges (∼ 1 × 1013 cm−2 ). It should be noted that the Schottky barrier height at the gate/AlGaN junction is assumed to remain the same in this work. An investigation on the effect of plasma treatment on the Schottky barrier is ongoing. As seen from the simulated conduction bands shown in Fig. 5(b) and (c), the potential of the AlGaN barrier can be significantly enhanced by the incorporation of the F− ions, resulting in an enhanced Schottky barrier and the subsequent gate current suppression. The gate current suppression in the forward bias is particularly beneficial to the digital IC applications. The suppressed gate current

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Fig. 6. Static voltage transfer characteristics for a typical E/D HEMT inverter. The output levels (VOH and VOL ), inverter threshold voltage (VTH ), and static noise margins (N ML and N MH ) are defined.

of the GaN-based HEMTs, can also affect the threshold voltage to a lesser degree. The deposition of silicon nitride passivation layer on the active region, in general, can alter the stress in the AlGaN and GaN layers. Subsequently, the piezoelectric polarization charge density and the threshold voltage of the device can be slightly modified. In general, the widely used SiN layer deposited by high-frequency PECVD introduces additional tensile stress in the AlGaN layer, resulting in a negative shift of the threshold voltage in the range of a few tenths of a volt. In practice, this effect should be taken into consideration in the process design. The plasma treatment dose can be increased accordingly to compensate the negative shift in threshold voltage by the SiN passivation layer. The stress of the SiN passivation layer can also be reduced by modifying the process parameters of the PECVD deposition so that the negative shift in the threshold voltage is minimized.

B. DCFL Inverter Fig. 5. (a) Ig −Vg characteristics of both D- and E-mode HETMs (the inset shows the forward gate current characteristics). Simulated conduction-edge band diagrams under the gate electrode at zero gate bias are also shown in (b) for conventional D-mode HEMT and in (c) for E-mode HEMT (where a linear distribution of fluorine concentration was assumed, which decreases from 3 × 1019 cm−3 at the AlGaN surface to zero at the AlGaN/GaN interface).

allows the E-mode devices’ gate bias to be increased up to 2.5 V. Such an increase results in a larger gate voltage swing, larger dynamic range for the input, and higher fan-out. The increased input voltage swing permits higher supply voltage that is an important factor in achieving higher operation speed and higher noise margins for digital ICs. Without the increased gate input swing, a larger supply voltage will lead to an output voltage (at logic “high”) that exceeds the turn-on voltage of the following stage’s input gate. The wider dynamic range for the input enables direct logic level matching between the input and the output, eliminating the need for level adjustment between adjacent stages. It should be noted that silicon nitride passivation, which is an important technique generally used for the stable operation

The circuit schematic of an E/D HEMT inverter is shown in Fig. 1(a), where the D-mode HEMT is used as load with its gate tied to its source and the E-mode HEMT is used as a driver. The fabricated inverters were characterized using an HP4156A parameter analyzer. Fig. 6 shows the static voltage transfer characteristics (the solid curve) for a typical E/D HEMT inverter. The rise in the output voltage at the large input voltages (> 2.1 V) is a result of the gate Schottky diode’s turn-on. The dashed curve is the same transfer curve with the axis interchanged and represents the input-output characteristics of the next inverter stage. The parameter definitions follow those given for GaAs- and InPbased HEMTs [15], [16]. The static output levels (VOH and VOL ) are given by the two intersections of the curves in stable equilibrium points, and the difference between the two levels is defined as the output logic voltage swing. The inverter threshold voltage (VTH ) is defined as Vin , where Vin is equal to Vout . The static noise margins are measured using the method of largest width [16] for both logic-low noise margin (N ML ) and logichigh noise margin (N MH ).


Fig. 7. Static voltage transfer characteristics of E/D HEMT inverters with β = 6.7, 10, 25, 50; the supply voltage is 1.5 V.

TABLE III NOISE MARGINS FOR INVERTERS WITH DIFFERENT β’S MEASURED AT VDD = 1.5 V

The measured static voltage transfer curves of E/D inverters with β varied from 6.7 to 50 at a supply voltage VDD = 1.5 V are plotted in Fig. 7. High output logic level (VOH ) is maintained at 1.5 V, indicating that the E-mode HEMTs are well switched off, whereas low output logic level (VOL ) is improved from 0.34 to 0.09 V as a result of β increasing from 6.7 to 50. As a result, the output logic swing defined as VOH − VOL increases from 1.16 to 1.41 V. As β is increased from 6.7 to 50, VTH decreases from 0.88 to 0.61 V, the dc voltage gain (G) in the linear region increases from 2 to 4.1. Table III lists the measured values of static noise margins, as well as VOH , VOL , output logic swing, VTH , and G. Both N ML and N MH are improved as β increases. The static voltage transfer curves of the inverter with β = 10 were measured at different supply voltages and are plotted in Fig. 8. The circuit performance parameters are listed in Table IV. When supply voltage increases, all the parameters of E/D inverter increase accordingly. This means that the increase of supply voltage improves the static performance of the E/D inverter. As well known, for HEMT and MESFET E/D inverters, the input voltage is always limited by the turn-on voltage of the gate Schottky diode. At a large input voltage, gate conduction causes an increased voltage drop across the parasitic source resistance of the E-mode device that is used as a driver, raising the voltage of the logic low level [15]. The rise in the output voltage can be observed in the static transfer curves as the supply voltage and the required input voltage increase, as shown in Fig. 8. The gate current, when increased by the large input voltage, can significantly degrade the inverter’s capability of driving multiple stages, reducing the fan-out. Usually, the turn-on voltage of the gate Schottky diode is around 1 V for a

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Fig. 8. Static voltage transfer characteristics of E/D HEMT inverters with β = 10 measured at supply voltage VDD = 1, 1.5, 2, 2.5 V.

TABLE IV NOISE MARGINS MEASURED AT DIFFERENT VDD S FOR THE I NVERTER W ITH β = 10

Fig. 9. Load current and input current of the inverter with β = 10 at VDD = 2.5 V.

normal AlGaN/GaN HEMT. For a gate-recessed E-mode GaN HEMT, the thinned AlGaN barrier further decreases the turnon voltage due to an enhanced tunneling current. As a result, for the inverter based on a gate-recessed E-mode GaN HEMT, the output voltage rises when the input voltage is beyond 0.8 V [12]. As mentioned in Section III-A, the E-mode GaN HEMT fabricated by CF4 plasma treatment possesses a suppressed gate current because of the enhanced Schottky barrier in the AlGaN layer, which is induced by the electronegative fluorine ions. Such a gate current suppression enables a larger input voltage swing for the E/D inverter. As can be seen in Fig. 8, the rise in output voltage does not occur until the input voltage is beyond 2 V, indicating about 1 V extension of input voltage swing.

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Fig. 10. (a) Frequency spectrum and (b) time-domain characteristics of a 17-stage ring oscillator with β = 10 biased at VDD = 3.5 V.

Fig. 9 shows the dependences of the load current and input current on the input voltage. The lower input current (gate current of the E-mode HEMT) implies a larger amount of fanout. At ON state, the input current exceeds 10% load current when the input voltage is larger than 2 V. C. DCFL Ring Oscillator Fig. 1(b) shows a schematic circuit diagram of a DCFL ring oscillator, which is formed with odd-numbered E/D inverter chain. Seventeen-stage ring oscillators were fabricated with inverters’ β = 6.7, 10, and 25. For each ring oscillator, 36 transistors were used including an output buffer. The ring oscillators were characterized on-wafer using an Agilent E4404B spectrum analyzer and an HP 54522A oscilloscope. The dc power consumption was also measured during the ring oscillators’ operation. Fig. 10 shows the frequency- and time-domain characteristics of the 17-stage ring oscillator with β = 10 biased at VDD = 3.5 V. The fundamental oscillation frequency is 225 MHz. According to the formula of propagation delay per stage τpd = (2nf )−1 , where the number of stages n is 17 in this paper, and τpd was calculated to be 130 ps/stage. The dependences of τpd and power–delay product on VDD were plotted in Fig. 11. With the increase of supply voltage, the propagation delay was reduced, whereas power–delay product increases. Compared to τpd (234 ps/stage) measured at 1 V, τpd measured at 3.5 V is reduced by 45%. The fact that the ring oscillator can operate at such a high VDD attributes to the larger input voltage swing realized by the CF4 plasma treatment technique used in the integration process. A minimum power–delay product of 0.113 pJ/stage was found at a VDD of 1 V. Fig. 11 also shows τpd and power–delay product characteristics of ring oscillators with β = 6.7 and 25. For the ring oscillator with β = 6.7, the larger τpd and power–delay product is due to the larger input capacitance determined by the larger gate length (1.5 µm) of the E-mode HEMT. For the ring oscillator with β = 25, the larger τpd is due to the lower charging current determined by the larger gate length (4 µm)

Fig. 11. Dependences of propagation delay and power–delay product on the supply voltage.

of the D-mode HEMT, whereas the power–delay product is at the same level as the one with β = 10. When this integration technology is implemented in the submicrometer regime, the gate delay time is expected to be further reduced. Recently, the discrete E-mode HEMTs and the DCFL ring oscillators have been tested at elevated temperature up to 375 ◦ C. No significant shift has been observed in the threshold voltage of the E-HEMT HEMTs, and the ring oscillator exhibits an oscillation frequency of 70 MHz at 375 ◦ C. The detailed results of high-temperature characterization will be reported elsewhere. IV. CONCLUSION We successfully demonstrated the monolithic integration of E/D-mode HEMTs in the GaN material system based on a novel technique of fabricating high-performance E-mode HEMT using fluoride-based plasma treatment. The integration technology was used to fabricate integrated inverters and ring oscillators for evaluating the performance of the digital IC technology. The fabricated E/D inverters show proper functions. In


particular, the input voltage swing was improved by ∼ 1 V, which is a unique advantage associated with the fluoride-based plasma treatment technique. The enlarged input voltage swing enables ring oscillators to operate at a higher supply voltage of 3.5 V, where a minimum propagation delay of 130 ps/stage, which corresponds to a 45% improvement over that measured at a supply voltage of 1 V, is achieved.

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Yong Cai was born in Nanjing, China, in 1971. He received the B.S. degree from the Department of Electronics Engineering, Southeast University, Nanjing, in 1993, and the Ph.D. degree from the Institute of Microelectronics, Peking University, Beijing, in 2003. He is currently a postdoctoral Research Associate with the Department of Electrical and Electronic Engineering, Hong Kong University of Science and Technology, working on wide-bandgap GaN-based devices and circuits.

R EFERENCES [1] I. Daumiller, C. Kirchner, M. Kamp, K. J. Ebeling, and E. Kohn, “Evaluation of the temperature stability of AlGaN/GaN heterostructure FET’s,” IEEE Electron Device Lett., vol. 20, no. 9, pp. 448–450, Sep. 1999. [2] P. G. Neudeck, R. S. Okojie, and L.-Y. Chen, “High-temperature electronics—A role for wide bandgap semiconductors?” Proc. IEEE, pp. 1065–1076, vol. 90, no. 6, Jun. 2002. [3] T. Egawa, G. Y. Zhao, H. Ishikawa, M. Umeno, and T. Jimbo, “Characterizations of recessed gate AlGaN/GaN HEMTs on sapphire,” IEEE Trans. Electron Devices, vol. 48, no. 3, pp. 603–608, Mar. 2003. [4] R. Kirschman Ed., High Temperature Electronics, New York: IEEE Press, 1999. [5] S. Long and S. E. Butner, Gallium Arsenide Digital Integrated Circuit Design. New York: McGraw-Hill, 1990. [6] Y. F. Wu, A. Saxler, M. Moore, R. P. Smith, S. Sheppard, P. M. Chavarkar, T. Wisleder, U. K. Mishra, and P. Parikh, “30-W/mm GaN HEMTs by field plate optimization,” IEEE Electron Device Lett., vol. 25, no. 3, pp. 117–119, Mar. 2004. [7] M. Kanamura, T. Kikkawa, T. Iwai, K. Imanishi, T. Kubo, and K. Joshin, “An over 100 W n-GaN/n-AlGaN/GaN MIS-HEMT power amplifier for wireless base station applications,” in IEDM Tech. Dig., Washington, DC, Dec. 4–7, 2005, pp. 572–575. [8] J. S. Moon, D. Wang, T. Hussain, M. Mocovic, P. Deelman, M. Hu, M. Antcliffe, C. Ngo, P. Hashimoto, and L. McCray, “Submicron enhancement-mode AlGaN/GaN HEMTs,” in Proc. 60th Device Research Conf. Dig., Santa Barbara, CA, 2002, pp. 23–25. [9] T. Hussain, M. Micovic, T. Tsen, M. Delaney, D. Chow, A. Schmitz, P. Hashimoto, D. Wong, J. S. Moon, M. Hu, J. Duvall, and D. McLaughlin, “GaN HFET digital circuit technology for harsh environments,” Electron. Lett., vol. 39, no. 24, pp. 1708–1709, Nov. 2003. [10] W. B. Lanford, T. Tanaka, Y. Otoki, and I. Adesida, “Recessed-gate enhancement-mode GaN HEMT with high threshold voltage,” Electron. Lett., vol. 41, no. 7, pp. 449–450, Mar. 2005. [11] Y. Cai, Y. G. Zhou, K. J. Chen, and K. M. Lau, “High-performance enhancement-mode AlGaN/GaN HEMTs using fluoride-based plasma treatment,” IEEE Electron Device Lett., vol. 26, no. 7, pp. 435–437, Jul. 2005. [12] M. Micovic, T. Tsen, M. Hu, P. Hashimoto, P. J. Willadsen, I. Milosavljevic, A. Schmitz, M. Antcliffe, D. Zhender, J. S. Moon, W. S. Wong, and D. Chow, “GaN enhancement/depletion-mode FET logic for mixed signal applications,” Electron. Lett., vol. 41, no. 19, pp. 1081–1083, Sep. 2005. [13] Y. Cai, Z. Cheng, C. W. Tang, K. J. Chen, and K. M. Lau, “Monolithic integration of enhancement-and depletion-mode AlGaN/GaN HEMTs for GaN digital integrated circuits,” in IEDM Tech. Dig., Washington, DC, Dec. 4–7, 2005. [14] Y. Cai, Y. G. Zhou, K. J. Chen, and K. M. Lau, “Threshold voltage control of AlGaN/GaN HEMTs by CF4 plasma treatment,” in Proc. 47th EMC, Santa Barbara, CA, Jun. 2005. [15] A. A. Ketterson and H. Morkoc, “GaAs/AlGaAs and InGaAs/ AlGaAs MODFET inverter simulations,” IEEE Trans. Electron Devices, vol. ED-33, no. 11, pp. 1626–1634, 1986. [16] A. Mahajan, G. Cueva, M. Arafa, P. Fay, and I. Adesida, “Fabrication and characterization of an InAlAs/InGaAs/InP ring oscillator using integrated enhancement-and depletion-mode high-electron mobility transistors,” IEEE Electron Device Lett., vol. 18, no. 8, pp. 391–393, Aug. 1997.

Zhiqun Cheng received the B.S. and M.S. degree in microelectronics from the Hefei University of Technology, Hefei, China, in 1986 and 1995, respectively, and the Ph.D. degree in microelectronics and solid-state electronics from the Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai, in 2000. He is currently a Professor with the Hangzhou Dianzi University, Hangzhou, China, and a Senior Visiting Scholar with the Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology (HKUST). Prior to joining HKUST, he was a Lecturer with the Hefei University of Technology from 1986 to 1997 and an Associate Professor with the Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences from 2000 to 2005, where he was involved in III–V, GaAs, and GaN HEMTs and HBTs and relative circuits and RF transceiver. He has authored and coauthored 50 technical papers in journals and conferences. His current interests focus on III–V high-power and low-noise devices and circuits for microwave and millimeter applications and high-speed Si and SiGe devices and T/R system for wireless communications.

Wilson Chak Wah Tang received the M.Sc. degree from the Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan, R.O.C. He has been a Research Engineer of growing GaNbased materials on sapphire and InP-based materials on GaAs and InP substrate. His current interest is design and growth of various high-speed device structures.

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Kei May Lau (S’78–M’80–SM’92–F’01) received the B.S. and M.S. degrees in physics from the University of Minnesota, Minneapolis, in 1976 and 1977, respectively, and the Ph.D. degree in electrical engineering from Rice University, Houston, TX, in 1981. From 1980 to 1982, she was a Senior Engineer with M/A-COM Gallium Arsenide Products, Inc., where she worked on epitaxial growth of GaAs for microwave devices, development of high-efficiency and millimeter-wave impact ionization avalanche transit-time diodes, and multiwafer epitaxy by the chloride transport process. In the fall of 1982, she joined the faculty of the Department of Electrical and Computer Engineering, University of Massachusetts Amherst (Umass Amherst), where she became a Full Professor in 1993. She initiated metal–organic chemical vapor deposition, compound semiconductor materials and devices programs at Umass Amherst. Her research group performed studies on heterostructures, quantum wells, strained layers, III–V selective epitaxy, as well as high-frequency and photonic devices. She spent her first sabbatical leave in 1989 at the Massachusetts Institute of Technology Lincoln Laboratory. She developed acoustic sensors at the DuPont Central Research and Development Laboratory, Wilmington, DE, during her second sabbatical leave (1995–1996). In the fall of 1998, she was a Visiting Professor with the Hong Kong University of Science and Technology (HKUST), where she joined the regular faculty in the summer of 2000. She established the Photonics Technology Center for R&D efforts in wide-bandgap semiconductor materials and devices. She became a Chair Professor of Electrical and Electronic Engineering at HKUST in July 2005. Prof. Lau was a recipient of the National Science Foundation Faculty Awards for Women Scientists and Engineers in the U.S. She served on the IEEE Electron Devices Society Administrative Committee and was an Editor of the IEEE TRANSACTIONS ON ELECTRON DEVICES (1996–2002). She also served on the Electronic Materials Committee of the Minerals, Metals and Materials Society of the American Institute of Materials Engineers.


Kevin J. Chen (M’95) received the B.S. degree from the Department of Electronics, Peking University, Beijing, China, in 1988, and obtained the Ph.D. degree from the University of Maryland, College Park, in 1993. From January 1994 to December 1995, he was a Research Fellow with the NTT LSI Laboratories, Atsugi, Japan, engaging in the research and development of functional quantum effect devices and heterojunction field-effect transistors (HFETs). In particular, he developed the device technology for monolithic integration of resonant tunneling diodes and HFETs (MISFET and HEMT) on both GaAs and InP substrates for applications in ultra-high-speed signal processing and communication systems. He also developed the Pt-based buried gate technology that is widely used in the enhancement-mode HEMT devices. From 1996 to 1998, he was an Assistant Professor with the Department of Electronic Engineering, City University of Hong Kong, carrying out research on high-speed device and circuit simulations. He then joined the Wireless Semiconductor Division, Agilent Technologies, Inc. (formerly HewlettPackard Company), Santa Clara, CA, in 1999, working on enhancementmode pseudomorphic HEMT RF power amplifiers used in dual-band global standard for mobile communications/digital cellular system wireless handsets. His work at Agilent covered RF characterization and modeling of microwave transistors, RF IC, and package design. In November 2000, he joined the Department of Electrical and Electronics Engineering, Hong Kong University of Science and Technology, where he is currently an Associate Professor. At HKUST, his group has carried out research on novel III-nitride device and fabrication techniques, silicon-based RF/microwave passive components, III-nitride and silicon-based microelectromechanical systems, RF packing technology, and microwave filter design. He has authored or coauthored over 130 publications in international journals and conference proceedings.