Ge-on-Insulator Lateral Bipolar Transistors J.-B. Yau, J. Yoon, J. Cai, T. H. Ning,
K. K.
Chan, S.
U.
Engelmann, D.-G. Park, R. T. Mo, and G. Shahidi
IBM Research Division, T J. Watson Research Center, Yorktown Heights, NY 10598
E-mail:
[email protected].
Abstract-We report the first demonstration of thin-base
symmetric lateral NPN bipolar transistors built on 8-inch Ge-on insulator
(Ge-OI)
wafers. A Ge-OI device can achieve the same
collector current as a Si-OI device but at
- 460 mV lower
V/JE due
to the bandgap of Ge being 460 meV smaller than that of Si.
Lower operation voltage should translate directly into lower power dissipation. CMOS-like process was used to fabricate lateral Ge-OI bipolar transistors. The measured collector and base currents are examined and compared with those of Si-OI and SiGe-OI devices to shed light on process-related device physics.
The
large
observed
base
current
at
small
V/JE is
attributed to recombination at the Ge/BOX interface in the emitter-base diode space-charge region.
Keywords-Bipolar transistors, SOl lateral bipolar transistors, Ge-Ollateral bipolar transistors
I.
Fig. I. (a) Schematic illustrating the structure of an SOl lateral NPN bipolar transistor with symmetric emitter and collector regions. The quasi-neutral base width Ws is narrower than the physical E-C separation by the depletion layers from both E and C sides (After [2]). (b) Outline of CMOS-like process flow used for Ge-Ol device fabrication.
INTRODUCTION
A symmetric lateral Si-on-insulator (Si-OI) bipolar transistor (Fig. lea)) with a self aligned base contact located on top of the intrinsic-base region, and base width of about 2 /-lm, was first demonstrated almost thirty years ago [1]. With the advancement of lithography capability in manufacturing at present, it is possible to fabricate Si-OI lateral complementary bipolar (NPN plus PNP) transistors with base widths much narrower than 100 nm [2, 3] using CMOS-like processes. Experimental data show that semiconductor-on-insulator (SOl) lateral bipolar devices have drive-current capability much higher than that of CMOS [3] and model studies [4] suggest them to be scalable in lateral dimension like CMOS, and could havefmax > 1 THz. In addition, it can be inferred from the current equations that the operation voltage for a bipolar transistor is proportional to the energy bandgap of the constituent semiconductor of the intrinsic-base region [4]. If a Si bipolar circuit operates with a power supply voltage of 1.0 V, the same circuit built with SiGe or Ge bipolar transistors can readily operate with a power supply significantly less than 1.0 V. Recently, a SiGe-on-insulator (SiGe-OI) (-25% Ge) lateral bipolar transistor was demonstrated to achieve the same collector current as a Si-Ol device but at -130 mV lower VSE [5], confirming that indeed the path towards reducing the power supply voltage for bipolar circuits is to build the transistors using small-bandgap semiconductors. In a control experiment [6], Dill et al. showed that Ge bipolar circuits could be three times faster than Si bipolar circuits because of the much higher electron and hole mobilities in Ge. This, together with the merits of SOl lateral bipolar transistors mentioned above suggests that symmetric
978-1-5090-0484-3/16/$31.00 ©2016 IEEE
lateral Ge-on-insulator (Ge-Ol) bipolar transistors could be an excltmg, scalable, high-performance, and low-power technology. In this paper, we report the first demonstration of Ge-Ol symmetric lateral NPN transistors, built using a fabrication process sequence similar to those used previously and successfully to fabricate Si-OI and SiGe-OI transistors [4, 5]. The measured Ge-Ol device currents are compared with those from the Si-OI and SiGe-OI devices, and examined to shed light on process-related device physics. II.
DEVICE
FABRlCATlON
Figure l(a) shows a schematic cross section an SOl lateral NPN transistor. The Ge-Ol transistors were fabricated using a CMOS-like process similar to those used to fabricate Si-OI and SiGe-OI lateral transistors [4, 5]. The process flow is as illustrated in Fig. l(b). The 8-inch Ge-OI wafers were supplied by Soitec and were formed by wafer bonding technique. A standard 90nm CMOS mask set was used for device fabrication, resulting in a patterned physical gate length (LG) of about 60nm with a mask dimension (LOES) of 80nm. After the gate is patterned (extrinsic base poly SiGe layer), a thin (1 nm) layer of AhO} is deposited by ALD on the exposed Ge surface to passivate the Ge surface [7]. Subsequently, a 55-nm composite dielectric of Si02 and SiNx was added before the vertical spacer (spacer 1) was formed by RIE. It should be noted that while the Ge surface under the spacer is passivated by AhO}, the Ge surface at the BOX is not. As fabricated, the Ge-Ol wafers have Ge in contact with
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